diff options
author | Jonathan Gray <jsg@cvs.openbsd.org> | 2015-12-07 06:34:15 +0000 |
---|---|---|
committer | Jonathan Gray <jsg@cvs.openbsd.org> | 2015-12-07 06:34:15 +0000 |
commit | 815d109977c344b64ad7a5f2f5eae3df2ecb75fc (patch) | |
tree | 97ddffa05e2231623185424eea47839bc3427056 /sys/arch/i386 | |
parent | daf1998fedc9e84f9564e77db99863efc9bebde3 (diff) |
Add cpuid bits documented in the August 2015 revision of
"Intel Architecture Instruction Set Extensions Programming Reference"
Diffstat (limited to 'sys/arch/i386')
-rw-r--r-- | sys/arch/i386/i386/cpu.c | 6 | ||||
-rw-r--r-- | sys/arch/i386/i386/machdep.c | 41 | ||||
-rw-r--r-- | sys/arch/i386/include/cpu.h | 5 | ||||
-rw-r--r-- | sys/arch/i386/include/specialreg.h | 23 |
4 files changed, 61 insertions, 14 deletions
diff --git a/sys/arch/i386/i386/cpu.c b/sys/arch/i386/i386/cpu.c index df06c49c2d2..626e388f0f3 100644 --- a/sys/arch/i386/i386/cpu.c +++ b/sys/arch/i386/i386/cpu.c @@ -1,4 +1,4 @@ -/* $OpenBSD: cpu.c,v 1.68 2015/11/06 02:49:06 jsg Exp $ */ +/* $OpenBSD: cpu.c,v 1.69 2015/12/07 06:34:14 jsg Exp $ */ /* $NetBSD: cpu.c,v 1.1.2.7 2000/06/26 02:04:05 sommerfeld Exp $ */ /*- @@ -375,10 +375,10 @@ cpu_init(struct cpu_info *ci) if (cpu_feature & CPUID_PGE) cr4 |= CR4_PGE; /* enable global TLB caching */ - if (ci->ci_feature_sefflags & SEFF0EBX_SMEP) + if (ci->ci_feature_sefflags_ebx & SEFF0EBX_SMEP) cr4 |= CR4_SMEP; #ifndef SMALL_KERNEL - if (ci->ci_feature_sefflags & SEFF0EBX_SMAP) + if (ci->ci_feature_sefflags_ebx & SEFF0EBX_SMAP) cr4 |= CR4_SMAP; #endif diff --git a/sys/arch/i386/i386/machdep.c b/sys/arch/i386/i386/machdep.c index 11ffb954ed0..755d4d09048 100644 --- a/sys/arch/i386/i386/machdep.c +++ b/sys/arch/i386/i386/machdep.c @@ -1,4 +1,4 @@ -/* $OpenBSD: machdep.c,v 1.576 2015/10/21 07:59:18 mpi Exp $ */ +/* $OpenBSD: machdep.c,v 1.577 2015/12/07 06:34:14 jsg Exp $ */ /* $NetBSD: machdep.c,v 1.214 1996/11/10 03:16:17 thorpej Exp $ */ /*- @@ -1068,6 +1068,7 @@ const struct cpu_cpuid_feature i386_ecpuid_ecxfeatures[] = { const struct cpu_cpuid_feature cpu_seff0_ebxfeatures[] = { { SEFF0EBX_FSGSBASE, "FSGSBASE" }, + { SEFF0EBX_SGX, "SGX" }, { SEFF0EBX_BMI1, "BMI1" }, { SEFF0EBX_HLE, "HLE" }, { SEFF0EBX_AVX2, "AVX2" }, @@ -1076,9 +1077,30 @@ const struct cpu_cpuid_feature cpu_seff0_ebxfeatures[] = { { SEFF0EBX_ERMS, "ERMS" }, { SEFF0EBX_INVPCID, "INVPCID" }, { SEFF0EBX_RTM, "RTM" }, + { SEFF0EBX_PQM, "PQM" }, + { SEFF0EBX_MPX, "MPX" }, + { SEFF0EBX_AVX512F, "AVX512F" }, + { SEFF0EBX_AVX512DQ, "AVX512DQ" }, { SEFF0EBX_RDSEED, "RDSEED" }, { SEFF0EBX_ADX, "ADX" }, { SEFF0EBX_SMAP, "SMAP" }, + { SEFF0EBX_AVX512IFMA, "AVX512IFMA" }, + { SEFF0EBX_PCOMMIT, "PCOMMIT" }, + { SEFF0EBX_CLFLUSHOPT, "CLFLUSHOPT" }, + { SEFF0EBX_CLWB, "CLWB" }, + { SEFF0EBX_PT, "PT" }, + { SEFF0EBX_AVX512PF, "AVX512PF" }, + { SEFF0EBX_AVX512ER, "AVX512ER" }, + { SEFF0EBX_AVX512CD, "AVX512CD" }, + { SEFF0EBX_SHA, "SHA" }, + { SEFF0EBX_AVX512BW, "AVX512BW" }, + { SEFF0EBX_AVX512VL, "AVX512VL" }, +}; + +const struct cpu_cpuid_feature cpu_seff0_ecxfeatures[] = { + { SEFF0ECX_PREFETCHWT1, "PREFETCHWT1" }, + { SEFF0ECX_AVX512VBMI, "AVX512VBMI" }, + { SEFF0ECX_PKU, "PKU" }, }; const struct cpu_cpuid_feature cpu_tpm_eaxfeatures[] = { @@ -1980,15 +2002,20 @@ identifycpu(struct cpu_info *ci) /* "Structured Extended Feature Flags" */ CPUID_LEAF(0x7, 0, dummy, - ci->ci_feature_sefflags, dummy, dummy); - max = sizeof(cpu_seff0_ebxfeatures) / - sizeof(cpu_seff0_ebxfeatures[0]); - for (i = 0; i < max; i++) - if (ci->ci_feature_sefflags & + ci->ci_feature_sefflags_ebx, + ci->ci_feature_sefflags_ecx, dummy); + for (i = 0; i < nitems(cpu_seff0_ebxfeatures); i++) + if (ci->ci_feature_sefflags_ebx & cpu_seff0_ebxfeatures[i].feature_bit) printf("%s%s", (numbits == 0 ? "" : ","), cpu_seff0_ebxfeatures[i].feature_name); + for (i = 0; i < nitems(cpu_seff0_ecxfeatures); i++) + if (ci->ci_feature_sefflags_ecx & + cpu_seff0_ecxfeatures[i].feature_bit) + printf("%s%s", + (numbits == 0 ? "" : ","), + cpu_seff0_ecxfeatures[i].feature_name); } if (!strcmp(cpu_vendor, "GenuineIntel") && @@ -2012,7 +2039,7 @@ identifycpu(struct cpu_info *ci) if (cpu_ecxfeature & CPUIDECX_RDRAND) has_rdrand = 1; #ifndef SMALL_KERNEL - if (ci->ci_feature_sefflags & SEFF0EBX_SMAP) + if (ci->ci_feature_sefflags_ebx & SEFF0EBX_SMAP) replacesmap(); #endif diff --git a/sys/arch/i386/include/cpu.h b/sys/arch/i386/include/cpu.h index 3da258a9567..3d27ce6b0af 100644 --- a/sys/arch/i386/include/cpu.h +++ b/sys/arch/i386/include/cpu.h @@ -1,4 +1,4 @@ -/* $OpenBSD: cpu.h,v 1.144 2015/07/13 17:45:01 mikeb Exp $ */ +/* $OpenBSD: cpu.h,v 1.145 2015/12/07 06:34:14 jsg Exp $ */ /* $NetBSD: cpu.h,v 1.35 1996/05/05 19:29:26 christos Exp $ */ /*- @@ -121,7 +121,8 @@ struct cpu_info { u_int32_t ci_family; /* extended cpuid family */ u_int32_t ci_model; /* extended cpuid model */ u_int32_t ci_feature_flags; /* X86 CPUID feature bits */ - u_int32_t ci_feature_sefflags; /* more CPUID feature bits */ + u_int32_t ci_feature_sefflags_ebx;/* more CPUID feature bits */ + u_int32_t ci_feature_sefflags_ecx;/* more CPUID feature bits */ u_int32_t ci_feature_tpmflags; /* thermal & power bits */ u_int32_t cpu_class; /* CPU class */ u_int32_t ci_cflushsz; /* clflush cache-line size */ diff --git a/sys/arch/i386/include/specialreg.h b/sys/arch/i386/include/specialreg.h index 1724f75fd11..31bd5c5bc57 100644 --- a/sys/arch/i386/include/specialreg.h +++ b/sys/arch/i386/include/specialreg.h @@ -1,4 +1,4 @@ -/* $OpenBSD: specialreg.h,v 1.52 2015/06/07 08:11:50 guenther Exp $ */ +/* $OpenBSD: specialreg.h,v 1.53 2015/12/07 06:34:14 jsg Exp $ */ /* $NetBSD: specialreg.h,v 1.7 1994/10/27 04:16:26 cgd Exp $ */ /*- @@ -164,8 +164,8 @@ * "Structured Extended Feature Flags Parameters" (CPUID function 0x7, leaf 0) * EBX bits */ - #define SEFF0EBX_FSGSBASE 0x00000001 /* {RD,WR}[FG]SBASE instructions */ +#define SEFF0EBX_SGX 0x00000004 /* Software Guard Extensions */ #define SEFF0EBX_BMI1 0x00000008 /* advanced bit manipulation */ #define SEFF0EBX_HLE 0x00000010 /* Hardware Lock Elision */ #define SEFF0EBX_AVX2 0x00000020 /* Advanced Vector Extensions 2 */ @@ -174,9 +174,28 @@ #define SEFF0EBX_ERMS 0x00000200 /* Enhanced REP MOVSB/STOSB */ #define SEFF0EBX_INVPCID 0x00000400 /* INVPCID instruction */ #define SEFF0EBX_RTM 0x00000800 /* Restricted Transactional Memory */ +#define SEFF0EBX_PQM 0x00001000 /* Quality of Service Monitoring */ +#define SEFF0EBX_MPX 0x00004000 /* Memory Protection Extensions */ +#define SEFF0EBX_AVX512F 0x00010000 /* AVX-512 foundation inst */ +#define SEFF0EBX_AVX512DQ 0x00020000 /* AVX-512 double/quadword */ #define SEFF0EBX_RDSEED 0x00040000 /* RDSEED instruction */ #define SEFF0EBX_ADX 0x00080000 /* ADCX/ADOX instructions */ #define SEFF0EBX_SMAP 0x00100000 /* Supervisor mode access prevent */ +#define SEFF0EBX_AVX512IFMA 0x00200000 /* AVX-512 integer mult-add */ +#define SEFF0EBX_PCOMMIT 0x00400000 /* Persistent commit inst */ +#define SEFF0EBX_CLFLUSHOPT 0x00800000 /* cache line flush */ +#define SEFF0EBX_CLWB 0x01000000 /* cache line write back */ +#define SEFF0EBX_PT 0x02000000 /* Processor Trace */ +#define SEFF0EBX_AVX512PF 0x04000000 /* AVX-512 prefetch */ +#define SEFF0EBX_AVX512ER 0x08000000 /* AVX-512 exp/reciprocal */ +#define SEFF0EBX_AVX512CD 0x10000000 /* AVX-512 conflict detection */ +#define SEFF0EBX_SHA 0x20000000 /* SHA Extensions */ +#define SEFF0EBX_AVX512BW 0x40000000 /* AVX-512 byte/word inst */ +#define SEFF0EBX_AVX512VL 0x80000000 /* AVX-512 vector len inst */ +/* SEFF ECX bits */ +#define SEFF0ECX_PREFETCHWT1 0x00000001 /* PREFETCHWT1 instruction */ +#define SEFF0ECX_AVX512VBMI 0x00000002 /* AVX-512 vector bit inst */ +#define SEFF0ECX_PKU 0x00000008 /* Page prot keys for user mode */ /* * Thermal and Power Management (CPUID function 0x6) EAX bits |