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authorTheo de Raadt <deraadt@cvs.openbsd.org>1999-02-24 22:05:16 +0000
committerTheo de Raadt <deraadt@cvs.openbsd.org>1999-02-24 22:05:16 +0000
commita0fcf9508b57827a0d9f28c9d3fb2a6a86f25b86 (patch)
tree52a2bef2d1e6002f5d428e34b657e9848f613cb1 /sys/arch/i386
parentda841c4f484cc81b9162427ab6e240a80f68d528 (diff)
pIII handling; testing by jdb@layer8.net
Diffstat (limited to 'sys/arch/i386')
-rw-r--r--sys/arch/i386/i386/machdep.c7
-rw-r--r--sys/arch/i386/include/specialreg.h3
2 files changed, 6 insertions, 4 deletions
diff --git a/sys/arch/i386/i386/machdep.c b/sys/arch/i386/i386/machdep.c
index d4df9ea63cd..880d014281b 100644
--- a/sys/arch/i386/i386/machdep.c
+++ b/sys/arch/i386/i386/machdep.c
@@ -1,4 +1,4 @@
-/* $OpenBSD: machdep.c,v 1.99 1999/02/23 21:18:27 marc Exp $ */
+/* $OpenBSD: machdep.c,v 1.100 1999/02/24 22:05:13 deraadt Exp $ */
/* $NetBSD: machdep.c,v 1.214 1996/11/10 03:16:17 thorpej Exp $ */
/*-
@@ -630,7 +630,7 @@ struct cpu_cpuid_nameclass i386_cpuid_cpus[] = {
{
0, "Pentium Pro", 0, "Pentium II",
"Pentium Pro", "Pentium II", "Pentium II",
- 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ "Pentium III", 0, 0, 0, 0, 0, 0, 0, 0,
"Pentium Pro" /* Default */
},
NULL
@@ -731,7 +731,8 @@ struct cpu_cpuid_feature i386_cpuid_features[] = {
{ CPUID_CMOV, "CMOV" },
{ CPUID_MMX, "MMX" },
{ CPUID_EMMX, "EMMX" },
- { CPUID_3D, "AMD3D" }
+ { CPUID_3D, "AMD3D" },
+ { CPUID_MMX2, "MMX2" }
};
void
diff --git a/sys/arch/i386/include/specialreg.h b/sys/arch/i386/include/specialreg.h
index f44dd5c2242..22e37f88f5e 100644
--- a/sys/arch/i386/include/specialreg.h
+++ b/sys/arch/i386/include/specialreg.h
@@ -1,4 +1,4 @@
-/* $OpenBSD: specialreg.h,v 1.5 1998/05/25 06:52:38 downsj Exp $ */
+/* $OpenBSD: specialreg.h,v 1.6 1999/02/24 22:05:15 deraadt Exp $ */
/* $NetBSD: specialreg.h,v 1.7 1994/10/27 04:16:26 cgd Exp $ */
/*-
@@ -109,6 +109,7 @@
#define CPUID_MMX 0x00800000 /* has MMX instructions */
#define CPUID_EMMX 0x01000000 /* has extended MMX (Cyrix) */
#define CPUID_3D 0x80000000 /* has AMD-3D instructions (AMD) */
+#define CPUID_MMX2 0x02000000 /* has Intel MMX-2 instructions */
/*
* the following four 3-byte registers control the non-cacheable regions.