Slight cmmu code cleanup; use shorter function names, remove parity_enable

and the DDB and DEBUG helpers which are of questionable usefulness, some
stylistic changes.

4 files changed, 133 insertions, 525 deletions

diff --git a/sys/arch/m88k/include/cmmu.h b/sys/arch/m88k/include/cmmu.h
index beb398c3f38..ae58c666b0b 100644
--- a/sys/arch/m88k/include/cmmu.h
+++ b/sys/arch/m88k/include/cmmu.h
@@ -1,4 +1,4 @@
-/*	$OpenBSD: cmmu.h,v 1.13 2005/12/03 19:06:08 miod Exp $ */
+/*	$OpenBSD: cmmu.h,v 1.14 2005/12/04 12:20:19 miod Exp $ */
 /*
  * Mach Operating System
  * Copyright (c) 1993-1992 Carnegie Mellon University
@@ -54,51 +54,45 @@ extern __cpu_simple_lock_t cmmu_cpu_lock;
 
 /* machine dependent cmmu function pointer structure */
 struct cmmu_p {
-	void (*cmmu_init_func)(void);
-	void (*setup_board_config_func)(void);
-	void (*cpu_configuration_print_func)(int);
-	void (*cmmu_shutdown_now_func)(void);
-	void (*cmmu_parity_enable_func)(void);
-	cpuid_t (*cmmu_cpu_number_func)(void);
-	void (*cmmu_set_sapr_func)(cpuid_t, apr_t);
-	void (*cmmu_set_uapr_func)(apr_t);
-	void (*cmmu_flush_tlb_func)(cpuid_t, unsigned, vaddr_t, u_int);
-	void (*cmmu_flush_cache_func)(cpuid_t, paddr_t, psize_t);
-	void (*cmmu_flush_inst_cache_func)(cpuid_t, paddr_t, psize_t);
-	void (*cmmu_flush_data_cache_func)(cpuid_t, paddr_t, psize_t);
-	int (*dma_cachectl_func)(pmap_t, vaddr_t, vsize_t, int);
-	int (*dma_cachectl_pa_func)(paddr_t, psize_t, int);
-	/* DDB only */
-	void (*cmmu_dump_config_func)(void);
-	void (*cmmu_show_translation_func)(unsigned, unsigned, unsigned, int);
-	/* DEBUG only */
-	void (*show_apr_func)(apr_t);
+	void (*init)(void);
+	void (*setup_board_config)(void);
+	void (*cpu_configuration_print)(int);
+	void (*shutdown_now)(void);
+	cpuid_t (*cpu_number)(void);
+	void (*set_sapr)(cpuid_t, apr_t);
+	void (*set_uapr)(apr_t);
+	void (*flush_tlb)(cpuid_t, u_int, vaddr_t, u_int);
+	void (*flush_cache)(cpuid_t, paddr_t, psize_t);
+	void (*flush_inst_cache)(cpuid_t, paddr_t, psize_t);
+	void (*flush_data_cache)(cpuid_t, paddr_t, psize_t);
+	int (*dma_cachectl)(pmap_t, vaddr_t, vsize_t, int);
+	int (*dma_cachectl_pa)(paddr_t, psize_t, int);
 };
 
 /* THE pointer! */
 extern struct cmmu_p *cmmu;
 
 /* The macros... */
-#define cmmu_init		(cmmu->cmmu_init_func)
-#define setup_board_config	(cmmu->setup_board_config_func)
-#define	cpu_configuration_print(a)	(cmmu->cpu_configuration_print_func)(a)
-#define	cmmu_shutdown_now	(cmmu->cmmu_shutdown_now_func)
-#define	cmmu_parity_enable	(cmmu->cmmu_parity_enable_func)
-#define	cmmu_cpu_number		(cmmu->cmmu_cpu_number_func)
-#define	cmmu_set_sapr(a, b)	(cmmu->cmmu_set_sapr_func)(a, b)
-#define	cmmu_set_uapr(a)	(cmmu->cmmu_set_uapr_func)(a)
-#define	cmmu_flush_tlb(a, b, c, d) 	(cmmu->cmmu_flush_tlb_func)(a, b, c, d)
-#define	cmmu_flush_cache(a, b, c)	(cmmu->cmmu_flush_cache_func)(a, b, c)
-#define	cmmu_flush_inst_cache(a, b, c)	(cmmu->cmmu_flush_inst_cache_func)(a, b, c)
-#define	cmmu_flush_data_cache(a, b, c)	(cmmu->cmmu_flush_data_cache_func)(a, b, c)
-#define	dma_cachectl(a, b, c, d)	(cmmu->dma_cachectl_func)(a, b, c, d)
-#define	dma_cachectl_pa(a, b, c)	(cmmu->dma_cachectl_pa_func)(a, b, c)
-#define	cmmu_dump_config	(cmmu->cmmu_dump_config_func)
-#define	cmmu_show_translation(a, b, c, d)	(cmmu->cmmu_show_translation_func)(a, b, c, d)
-#define show_apr(ap)		(cmmu->show_apr_func)(ap)
+#define cmmu_init			(cmmu->init)
+#define setup_board_config		(cmmu->setup_board_config)
+#define	cpu_configuration_print(a)	(cmmu->cpu_configuration_print)(a)
+#define	cmmu_shutdown_now		(cmmu->shutdown_now)
+#define	cmmu_cpu_number			(cmmu->cpu_number)
+#define	cmmu_set_sapr(a, b)		(cmmu->set_sapr)(a, b)
+#define	cmmu_set_uapr(a)		(cmmu->set_uapr)(a)
+#define	cmmu_flush_tlb(a, b, c, d) 	(cmmu->flush_tlb)(a, b, c, d)
+#define	cmmu_flush_cache(a, b, c)	(cmmu->flush_cache)(a, b, c)
+#define	cmmu_flush_inst_cache(a, b, c)	(cmmu->flush_inst_cache)(a, b, c)
+#define	cmmu_flush_data_cache(a, b, c)	(cmmu->flush_data_cache)(a, b, c)
+#define	dma_cachectl(a, b, c, d)	(cmmu->dma_cachectl)(a, b, c, d)
+#define	dma_cachectl_pa(a, b, c)	(cmmu->dma_cachectl_pa)(a, b, c)
+#define	cmmu_dump_config		(cmmu->dump_config)
+#define	cmmu_show_translation(a, b, c, d) \
+	(cmmu->show_translation)(a, b, c, d)
+#define show_apr(ap)			(cmmu->show_apr)(ap)
 
 /*
- * dma_cachectl modes
+ * dma_cachectl() modes
  */
 #define DMA_CACHE_SYNC		0
 #define DMA_CACHE_SYNC_INVAL	1
diff --git a/sys/arch/m88k/include/m8820x.h b/sys/arch/m88k/include/m8820x.h
index 8c0adc1e105..2b2421c76e0 100644
--- a/sys/arch/m88k/include/m8820x.h
+++ b/sys/arch/m88k/include/m8820x.h
@@ -1,4 +1,4 @@
-/*	$OpenBSD: m8820x.h,v 1.5 2005/12/02 21:16:45 miod Exp $ */
+/*	$OpenBSD: m8820x.h,v 1.6 2005/12/04 12:20:19 miod Exp $ */
 /*
  * Copyright (c) 2004, Miodrag Vallat.
  *
@@ -194,7 +194,7 @@ extern u_int cmmu_shift;
 extern u_int max_cmmus;
 
 void m8820x_setup_board_config(void);
-cpuid_t m8820x_cmmu_cpu_number(void);
+cpuid_t m8820x_cpu_number(void);
 
 #endif	/* _LOCORE */
 #endif	/* __M88K_M8820X_H__ */
diff --git a/sys/arch/m88k/m88k/db_interface.c b/sys/arch/m88k/m88k/db_interface.c
index 6ff3f64cef8..cc856fd0def 100644
--- a/sys/arch/m88k/m88k/db_interface.c
+++ b/sys/arch/m88k/m88k/db_interface.c
@@ -1,4 +1,4 @@
-/*	$OpenBSD: db_interface.c,v 1.2 2005/11/20 22:04:32 miod Exp $	*/
+/*	$OpenBSD: db_interface.c,v 1.3 2005/12/04 12:20:19 miod Exp $	*/
 /*
  * Mach Operating System
  * Copyright (c) 1993-1991 Carnegie Mellon University
@@ -598,67 +598,6 @@ m88k_db_frame_search(addr, have_addr, count, modif)
 	db_printf("(Walked back until 0x%x)\n",addr);
 }
 
-/*
- * See how a virtual address translates.
- * Must have an address.
- */
-void
-m88k_db_translate(addr, have_addr, count, modif)
-	db_expr_t addr;
-	int have_addr;
-	db_expr_t count;
-	char *modif;
-{
-	char c;
-	int verbose_flag = 0;
-	int supervisor_flag = 1;
-	int wanthelp = 0;
-
-	if (!have_addr)
-		wanthelp = 1;
-	else {
-		while (c = *modif++, c != 0) {
-			switch (c) {
-			default:
-				db_printf("bad modifier [%c]\n", c);
-				wanthelp = 1;
-				break;
-			case 'h':
-				wanthelp = 1;
-				break;
-			case 'v':
-				verbose_flag++;
-				break;
-			case 's':
-				supervisor_flag = 1;
-				break;
-			case 'u':
-				supervisor_flag = 0;
-				break;
-			}
-		}
-	}
-
-	if (wanthelp) {
-		db_printf("usage: translate[/vvsu] address\n");
-		db_printf("flags: v - be verbose (vv - be very verbose)\n");
-		db_printf("       s - use cmmu's supervisor area pointer (default)\n");
-		db_printf("       u - use cmmu's user area pointer\n");
-		return;
-	}
-	cmmu_show_translation(addr, supervisor_flag, verbose_flag, -1);
-}
-
-void
-m88k_db_cmmucfg(addr, have_addr, count, modif)
-	db_expr_t addr;
-	int have_addr;
-	db_expr_t count;
-	char *modif;
-{
-	cmmu_dump_config();
-}
-
 /************************/
 /* COMMAND TABLE / INIT */
 /************************/
@@ -667,8 +606,6 @@ struct db_command db_machine_cmds[] = {
 	{ "frame",	m88k_db_print_frame,	0,	NULL },
 	{ "regs",	m88k_db_registers,	0,	NULL },
 	{ "searchframe",m88k_db_frame_search,	0,	NULL },
-	{ "translate",	m88k_db_translate,	0,	NULL },
-	{ "cmmucfg",	m88k_db_cmmucfg,	0,	NULL },
 	{ "where",	m88k_db_where,		0,	NULL },
 #if defined(EXTRA_MACHDEP_COMMANDS)
 	EXTRA_MACHDEP_COMMANDS
diff --git a/sys/arch/m88k/m88k/m8820x_machdep.c b/sys/arch/m88k/m88k/m8820x_machdep.c
index c4089fd4696..b9ba1de34f0 100644
--- a/sys/arch/m88k/m88k/m8820x_machdep.c
+++ b/sys/arch/m88k/m88k/m8820x_machdep.c
@@ -1,4 +1,4 @@
-/*	$OpenBSD: m8820x_machdep.c,v 1.14 2005/12/03 19:06:11 miod Exp $	*/
+/*	$OpenBSD: m8820x_machdep.c,v 1.15 2005/12/04 12:20:19 miod Exp $	*/
 /*
  * Copyright (c) 2004, Miodrag Vallat.
  *
@@ -88,58 +88,42 @@
 
 #include <machine/asm_macro.h>
 #include <machine/cmmu.h>
+#include <machine/cpu.h>
 #include <machine/locore.h>
 #include <machine/lock.h>
 #include <machine/m8820x.h>
+#include <machine/psl.h>
 
-#ifdef DDB
-#include <ddb/db_output.h>		/* db_printf()		*/
-#endif
-
-void m8820x_cmmu_init(void);
+void m8820x_init(void);
 void m8820x_cpu_configuration_print(int);
-void m8820x_cmmu_shutdown_now(void);
-void m8820x_cmmu_parity_enable(void);
-void m8820x_cmmu_set_sapr(cpuid_t, apr_t);
-void m8820x_cmmu_set_uapr(apr_t);
-void m8820x_cmmu_flush_tlb(cpuid_t, unsigned, vaddr_t, u_int);
-void m8820x_cmmu_flush_cache(cpuid_t, paddr_t, psize_t);
-void m8820x_cmmu_flush_inst_cache(cpuid_t, paddr_t, psize_t);
-void m8820x_cmmu_flush_data_cache(cpuid_t, paddr_t, psize_t);
+void m8820x_shutdown(void);
+void m8820x_set_sapr(cpuid_t, apr_t);
+void m8820x_set_uapr(apr_t);
+void m8820x_flush_tlb(cpuid_t, u_int, vaddr_t, u_int);
+void m8820x_flush_cache(cpuid_t, paddr_t, psize_t);
+void m8820x_flush_inst_cache(cpuid_t, paddr_t, psize_t);
+void m8820x_flush_data_cache(cpuid_t, paddr_t, psize_t);
 int m8820x_dma_cachectl(pmap_t, vaddr_t, vsize_t, int);
 int m8820x_dma_cachectl_pa(paddr_t, psize_t, int);
-void m8820x_cmmu_dump_config(void);
-void m8820x_cmmu_show_translation(unsigned, unsigned, unsigned, int);
+void m8820x_dump_config(void);
+void m8820x_show_translation(vaddr_t, u_int, u_int, int);
 void m8820x_show_apr(apr_t);
 
 /* This is the function table for the mc8820x CMMUs */
 struct cmmu_p cmmu8820x = {
-	m8820x_cmmu_init,
+	m8820x_init,
 	m8820x_setup_board_config,
 	m8820x_cpu_configuration_print,
-	m8820x_cmmu_shutdown_now,
-	m8820x_cmmu_parity_enable,
-	m8820x_cmmu_cpu_number,
-	m8820x_cmmu_set_sapr,
-	m8820x_cmmu_set_uapr,
-	m8820x_cmmu_flush_tlb,
-	m8820x_cmmu_flush_cache,
-	m8820x_cmmu_flush_inst_cache,
-	m8820x_cmmu_flush_data_cache,
+	m8820x_shutdown,
+	m8820x_cpu_number,
+	m8820x_set_sapr,
+	m8820x_set_uapr,
+	m8820x_flush_tlb,
+	m8820x_flush_cache,
+	m8820x_flush_inst_cache,
+	m8820x_flush_data_cache,
 	m8820x_dma_cachectl,
-	m8820x_dma_cachectl_pa,
-#ifdef DDB
-	m8820x_cmmu_dump_config,
-	m8820x_cmmu_show_translation,
-#else
-	NULL,
-	NULL,
-#endif
-#ifdef DEBUG
-	m8820x_show_apr,
-#else
-	NULL,
-#endif
+	m8820x_dma_cachectl_pa
 };
 
 /*
@@ -168,11 +152,11 @@ u_int max_cmmus;
 u_int cmmu_shift;
 
 /* local prototypes */
-void m8820x_cmmu_set(int, unsigned, int, int, int, vaddr_t);
-void m8820x_cmmu_wait(int);
-int m8820x_cmmu_sync_cache(paddr_t, psize_t);
-int m8820x_cmmu_sync_inval_cache(paddr_t, psize_t);
-int m8820x_cmmu_inval_cache(paddr_t, psize_t);
+void	m8820x_cmmu_set(int, u_int, int, int, int, vaddr_t);
+void	m8820x_cmmu_wait(int);
+int	m8820x_cmmu_sync_cache(paddr_t, psize_t);
+int	m8820x_cmmu_sync_inval_cache(paddr_t, psize_t);
+int	m8820x_cmmu_inval_cache(paddr_t, psize_t);
 
 /* Flags passed to m8820x_cmmu_set() */
 #define MODE_VAL		0x01
@@ -183,8 +167,7 @@ int m8820x_cmmu_inval_cache(paddr_t, psize_t);
  * into the CMMU's registers.
  */
 void
-m8820x_cmmu_set(int reg, unsigned val, int flags, int cpu, int mode,
-    vaddr_t addr)
+m8820x_cmmu_set(int reg, u_int val, int flags, int cpu, int mode, vaddr_t addr)
 {
 	struct m8820x_cmmu *cmmu;
 	int mmu, cnt;
@@ -277,57 +260,61 @@ m8820x_cpu_configuration_print(int master)
 	__cpu_simple_lock(&print_lock);
 
 	printf("cpu%d: ", cpu);
-	if (proctype != ARN_88100) {
+	switch (proctype) {
+	default:
 		printf("unknown model arch 0x%x rev 0x%x\n",
 		    proctype, procvers);
-		__cpu_simple_unlock(&print_lock);
-		return;
-	}
-
-	printf("M88100 rev 0x%x", procvers);
-#if 0	/* not useful yet */
-	if (max_cpus > 1)
-		printf(", %s", master ? "master" : "slave");
+		break;
+	case ARN_88100:
+		printf("M88100 rev 0x%x", procvers);
+#ifdef MULTIPROCESSOR
+		if (max_cpus > 1)
+			printf(", %s", master ? "master" : "slave");
 #endif
-	printf(", %d CMMU", 1 << cmmu_shift);
+		printf(", %d CMMU", 1 << cmmu_shift);
 
-	mmu = cpu << cmmu_shift;
-	cmmu = m8820x_cmmu + mmu;
-	for (cnt = 1 << cmmu_shift; cnt != 0; cnt--, mmu++, cmmu++) {
-		int idr = cmmu->cmmu_regs[CMMU_IDR];
-		int mmuid = CMMU_TYPE(idr);
-
-		if (mmu % 2 == 0)
-			printf("\ncpu%d: ", cpu);
-		else
-			printf(", ");
-
-		if (mmutypes[mmuid][0] == 'U')
-			printf("unknown model id 0x%x", mmuid);
-		else
-			printf("%s", mmutypes[mmuid]);
-		printf(" rev 0x%x,", CMMU_VERSION(idr));
+		mmu = cpu << cmmu_shift;
+		cmmu = m8820x_cmmu + mmu;
+		for (cnt = 1 << cmmu_shift; cnt != 0; cnt--, mmu++, cmmu++) {
+			int idr = cmmu->cmmu_regs[CMMU_IDR];
+			int mmuid = CMMU_TYPE(idr);
+
+			if (mmu % 2 == 0)
+				printf("\ncpu%d: ", cpu);
+			else
+				printf(", ");
+
+			if (mmutypes[mmuid][0] == 'U')
+				printf("unknown model id 0x%x", mmuid);
+			else
+				printf("%s", mmutypes[mmuid]);
+			printf(" rev 0x%x,", CMMU_VERSION(idr));
 #ifdef M88200_HAS_SPLIT_ADDRESS
-		/*
-		 * Print address lines
-		 */
-		amask = cmmu->cmmu_addr_mask;
-		if (amask != 0) {
-			aline = 0;
-			while (amask != 0) {
-				abit = ff1(amask);
-				if ((cmmu->cmmu_addr & (1 << abit)) != 0)
-					printf("%cA%02d",
-					    aline != 0 ? '/' : ' ', abit);
-				else
-					printf("%cA%02d*",
-					    aline != 0 ? '/' : ' ', abit);
-				amask ^= 1 << abit;
-			}
-		} else
+			/*
+			 * Print address lines
+			 */
+			amask = cmmu->cmmu_addr_mask;
+			if (amask != 0) {
+				aline = 0;
+				while (amask != 0) {
+					abit = ff1(amask);
+					if ((cmmu->cmmu_addr &
+					    (1 << abit)) != 0)
+						printf("%cA%02d",
+						    aline != 0 ? '/' : ' ',
+						    abit);
+					else
+						printf("%cA%02d*",
+						    aline != 0 ? '/' : ' ',
+						    abit);
+					amask ^= 1 << abit;
+				}
+			} else
 #endif
-			printf(" full");
-		printf(" %ccache", CMMU_MODE(mmu) == INST_CMMU ? 'I' : 'D');
+				printf(" full");
+			printf(" %ccache", CMMU_MODE(mmu) == INST_CMMU ? 'I' : 'D');
+		}
+		break;
 	}
 	printf("\n");
 
@@ -351,12 +338,16 @@ m8820x_cpu_configuration_print(int master)
  * CMMU initialization routine
  */
 void
-m8820x_cmmu_init()
+m8820x_init()
 {
 	struct m8820x_cmmu *cmmu;
 	unsigned int line, cmmu_num;
-	int cssp, cpu, type;
-	u_int32_t apr;
+	int cssp, type;
+	apr_t apr;
+	cpuid_t cpu;
+
+	apr = ((0x00000 << PG_BITS) | CACHE_WT | CACHE_GLOBAL | CACHE_INH) &
+	    ~APR_V;
 
 	cmmu = m8820x_cmmu;
 	for (cmmu_num = 0; cmmu_num < max_cmmus; cmmu_num++, cmmu++) {
@@ -380,13 +371,14 @@ m8820x_cmmu_init()
 			}
 
 		/*
-		 * Set the SCTR, SAPR, and UAPR to some known state
+		 * Set the SCTR, SAPR, and UAPR to some known state.
+		 * XXX Investigate why enabling parity at this point
+		 * doesn't work.
 		 */
 		cmmu->cmmu_regs[CMMU_SCTR] &=
 		    ~(CMMU_SCTR_PE | CMMU_SCTR_SE | CMMU_SCTR_PR);
-		cmmu->cmmu_regs[CMMU_SAPR] = cmmu->cmmu_regs[CMMU_UAPR] =
-		    ((0x00000 << PG_BITS) | CACHE_WT | CACHE_GLOBAL |
-		    CACHE_INH) & ~APR_V;
+
+		cmmu->cmmu_regs[CMMU_SAPR] = cmmu->cmmu_regs[CMMU_UAPR] = apr;
 
 		cmmu->cmmu_regs[CMMU_BWP0] = cmmu->cmmu_regs[CMMU_BWP1] =
 		cmmu->cmmu_regs[CMMU_BWP2] = cmmu->cmmu_regs[CMMU_BWP3] =
@@ -424,10 +416,8 @@ m8820x_cmmu_init()
 	 * addresses can never be cached, and the no-caching zones are not
 	 * set up yet.
 	 */
+	apr &= ~CACHE_INH;
 	for (cpu = 0; cpu < max_cpus; cpu++) {
-		apr = ((0x00000 << PG_BITS) | CACHE_WT | CACHE_GLOBAL)
-		    & ~(CACHE_INH | APR_V);
-
 		m8820x_cmmu_set(CMMU_SAPR, apr, MODE_VAL, cpu, INST_CMMU, 0);
 		m8820x_cmmu_set(CMMU_SCR, CMMU_FLUSH_SUPER_ALL,
 		    0, cpu, 0, 0);
@@ -439,7 +429,7 @@ m8820x_cmmu_init()
  * Just before poweroff or reset....
  */
 void
-m8820x_cmmu_shutdown_now()
+m8820x_shutdown()
 {
 	unsigned cmmu_num;
 	struct m8820x_cmmu *cmmu;
@@ -456,24 +446,8 @@ m8820x_cmmu_shutdown_now()
 	CMMU_UNLOCK;
 }
 
-/*
- * enable parity
- */
-void
-m8820x_cmmu_parity_enable()
-{
-	unsigned cmmu_num;
-	struct m8820x_cmmu *cmmu;
-
-	cmmu = m8820x_cmmu;
-	CMMU_LOCK;
-	for (cmmu_num = 0; cmmu_num < max_cmmus; cmmu_num++, cmmu++)
-		cmmu->cmmu_regs[CMMU_SCTR] |= CMMU_SCTR_PE;
-	CMMU_UNLOCK;
-}
-
 void
-m8820x_cmmu_set_sapr(cpuid_t cpu, apr_t ap)
+m8820x_set_sapr(cpuid_t cpu, apr_t ap)
 {
 	CMMU_LOCK;
 	m8820x_cmmu_set(CMMU_SAPR, ap, 0, cpu, 0, 0);
@@ -481,7 +455,7 @@ m8820x_cmmu_set_sapr(cpuid_t cpu, apr_t ap)
 }
 
 void
-m8820x_cmmu_set_uapr(apr_t ap)
+m8820x_set_uapr(apr_t ap)
 {
 	int s = splhigh();
 	int cpu = cpu_number();
@@ -500,7 +474,7 @@ m8820x_cmmu_set_uapr(apr_t ap)
  *	flush any tlb
  */
 void
-m8820x_cmmu_flush_tlb(cpuid_t cpu, unsigned kernel, vaddr_t vaddr, u_int count)
+m8820x_flush_tlb(cpuid_t cpu, unsigned kernel, vaddr_t vaddr, u_int count)
 {
 	int s = splhigh();
 
@@ -564,7 +538,7 @@ m8820x_cmmu_flush_tlb(cpuid_t cpu, unsigned kernel, vaddr_t vaddr, u_int count)
  *	flush both Instruction and Data caches
  */
 void
-m8820x_cmmu_flush_cache(cpuid_t cpu, paddr_t physaddr, psize_t size)
+m8820x_flush_cache(cpuid_t cpu, paddr_t physaddr, psize_t size)
 {
 	int s = splhigh();
 	CMMU_LOCK;
@@ -599,7 +573,7 @@ m8820x_cmmu_flush_cache(cpuid_t cpu, paddr_t physaddr, psize_t size)
  *	flush Instruction caches
  */
 void
-m8820x_cmmu_flush_inst_cache(cpuid_t cpu, paddr_t physaddr, psize_t size)
+m8820x_flush_inst_cache(cpuid_t cpu, paddr_t physaddr, psize_t size)
 {
 	int s = splhigh();
 	CMMU_LOCK;
@@ -631,7 +605,7 @@ m8820x_cmmu_flush_inst_cache(cpuid_t cpu, paddr_t physaddr, psize_t size)
 }
 
 void
-m8820x_cmmu_flush_data_cache(cpuid_t cpu, paddr_t physaddr, psize_t size)
+m8820x_flush_data_cache(cpuid_t cpu, paddr_t physaddr, psize_t size)
 {
 	int s = splhigh();
 	CMMU_LOCK;
@@ -855,300 +829,3 @@ m8820x_dma_cachectl_pa(paddr_t pa, psize_t size, int op)
 	}
 	return (rc);
 }
-
-#ifdef DDB
-void
-m8820x_cmmu_dump_config()
-{
-	struct m8820x_cmmu *cmmu;
-	int cmmu_num;
-
-	db_printf("Current CPU/CMMU configuration:\n");
-	cmmu = m8820x_cmmu;
-	for (cmmu_num = 0; cmmu_num < max_cmmus; cmmu_num++, cmmu++) {
-#ifdef M88200_HAS_SPLIT_ADDRESS
-		db_printf("CMMU #%d: %s CMMU for CPU %d, addr 0x%08lx mask 0x%08lx\n",
-		    cmmu_num,
-		    CMMU_MODE(cmmu_num) == INST_CMMU ? "inst" : "data",
-		    cmmu_num >> cmmu_shift,
-		    cmmu->cmmu_addr, cmmu->cmmu_addr_mask);
-#else
-		db_printf("CMMU #%d: %s CMMU for CPU %d",
-		    cmmu_num,
-		    CMMU_MODE(cmmu_num) == INST_CMMU ? "inst" : "data",
-		    cmmu_num >> cmmu_shift);
-#endif
-	}
-}
-
-/*
- * Show (for debugging) how the current CPU translates the given ADDRESS
- * (as DATA).
- */
-void
-m8820x_cmmu_show_translation(unsigned address, unsigned supervisor_flag,
-    unsigned verbose_flag, int unused __attribute__ ((unused)))
-{
-	struct m8820x_cmmu *cmmu;
-	int cpu = cpu_number();
-	vaddr_t va = address;
-	int cmmu_num, cnt;
-	u_int32_t value;
-
-	/*
-	 * Find the correct data CMMU.
-	 */
-	cmmu_num = cpu << cmmu_shift;
-	cmmu = m8820x_cmmu + cmmu_num;
-	for (cnt = 1 << cmmu_shift; cnt != 0; cnt--, cmmu_num++, cmmu++) {
-		if (CMMU_MODE(cmmu_num) == INST_CMMU)
-			continue;
-#ifdef M88200_HAS_SPLIT_ADDRESS
-		if (cmmu->cmmu_addr_mask == 0 ||
-		    (va & cmmu->cmmu_addr_mask) ==
-		     cmmu->cmmu_addr)
-#endif
-			break;
-	}
-	if (cnt == 0) {
-		db_printf("No matching cmmu for VA %08x\n", address);
-		return;
-	}
-
-	if (verbose_flag != 0)
-		db_printf("VA %08x is managed by CMMU#%d.\n",
-		    address, cmmu_num);
-
-	/*
-	 * Perform some sanity checks.
-	 */
-	if (verbose_flag == 0) {
-		if ((cmmu->cmmu_regs[CMMU_SCTR] &
-		    CMMU_SCTR_SE) == 0)
-			db_printf("WARNING: snooping not enabled for CMMU#%d.\n",
-			    cmmu_num);
-	} else {
-		int i;
-
-		cmmu = m8820x_cmmu;
-		for (i = 0; i < max_cmmus; i++, cmmu++)
-			if (verbose_flag > 1 ||
-			    (cmmu->cmmu_regs[CMMU_SCTR] & CMMU_SCTR_SE) == 0) {
-				db_printf("CMMU#%d (cpu %d %s) snooping %s\n",
-				    i, i >> cmmu_shift,
-				    CMMU_MODE(i) == INST_CMMU ? "inst" : "data",
-				    (cmmu->cmmu_regs[CMMU_SCTR] &
-				     CMMU_SCTR_SE) ? "on" : "OFF");
-			}
-		cmmu = m8820x_cmmu + cmmu_num;
-	}
-
-	/*
-	 * Ask for a CMMU probe and report its result.
-	 */
-	{
-		u_int32_t ssr;
-
-		cmmu->cmmu_regs[CMMU_SAR] = address;
-		cmmu->cmmu_regs[CMMU_SCR] =
-		    supervisor_flag ? CMMU_PROBE_SUPER : CMMU_PROBE_USER;
-		ssr = cmmu->cmmu_regs[CMMU_SSR];
-
-		switch (verbose_flag) {
-		case 2:
-			db_printf("probe of 0x%08x returns ssr=0x%08x\n",
-			    address, ssr);
-			/* FALLTHROUGH */
-		case 1:
-			if (ssr & CMMU_SSR_V)
-				db_printf("PROBE of 0x%08x returns phys=0x%x",
-				    address, cmmu->cmmu_regs[CMMU_SAR]);
-			else
-				db_printf("PROBE fault at 0x%x",
-				    cmmu->cmmu_regs[CMMU_PFAR]);
-			if (ssr & CMMU_SSR_CE)
-				db_printf(", copyback err");
-			if (ssr & CMMU_SSR_BE)
-				db_printf(", bus err");
-			if (ssr & CACHE_WT)
-				db_printf(", writethrough");
-			if (ssr & CMMU_SSR_SO)
-				db_printf(", sup prot");
-			if (ssr & CACHE_GLOBAL)
-				db_printf(", global");
-			if (ssr & CACHE_INH)
-				db_printf(", cache inhibit");
-			if (ssr & CMMU_SSR_M)
-				db_printf(", modified");
-			if (ssr & CMMU_SSR_U)
-				db_printf(", used");
-			if (ssr & CMMU_SSR_PROT)
-				db_printf(", write prot");
-			if (ssr & CMMU_SSR_BH)
-				db_printf(", BATC");
-			db_printf(".\n");
-			break;
-		}
-	}
-
-	/*
-	 * Interpret area descriptor.
-	 */
-
-	if (supervisor_flag)
-		value = cmmu->cmmu_regs[CMMU_SAPR];
-	else
-		value = cmmu->cmmu_regs[CMMU_UAPR];
-
-	switch (verbose_flag) {
-	case 2:
-		db_printf("CMMU#%d", cmmu_num);
-		db_printf(" %cAPR is 0x%08x\n",
-		    supervisor_flag ? 'S' : 'U', value);
-		/* FALLTHROUGH */
-	case 1:
-		db_printf("CMMU#%d", cmmu_num);
-		db_printf(" %cAPR: SegTbl: 0x%x000p",
-		    supervisor_flag ? 'S' : 'U', PG_PFNUM(value));
-		if (value & CACHE_WT)
-			db_printf(", WTHRU");
-		if (value & CACHE_GLOBAL)
-			db_printf(", GLOBAL");
-		if (value & CACHE_INH)
-			db_printf(", INHIBIT");
-		if (value & APR_V)
-			db_printf(", VALID");
-		db_printf("\n");
-		break;
-	}
-
-	if ((value & APR_V) == 0) {
-		db_printf("VA 0x%08x -> apr 0x%08x not valid\n", va, value);
-		return;
-	}
-
-	value &= PG_FRAME;	/* now point to seg page */
-
-	/*
-	 * Walk segment and page tables to find our page.
-	 */
-	{
-		sdt_entry_t sdt;
-
-		if (verbose_flag)
-			db_printf("will follow to entry %d of page at 0x%x...\n",
-			    SDTIDX(va), value);
-		value |= SDTIDX(va) * sizeof(sdt_entry_t);
-
-		if (badwordaddr((vaddr_t)value)) {
-			db_printf("VA 0x%08x -> segment table @0x%08x not accessible\n",
-			    va, value);
-			return;
-		}
-
-		sdt = *(sdt_entry_t *)value;
-		switch (verbose_flag) {
-		case 2:
-			db_printf("SEG DESC @0x%x is 0x%08x\n", value, sdt);
-			/* FALLTHROUGH */
-		case 1:
-			db_printf("SEG DESC @0x%x: PgTbl: 0x%x000",
-			    value, PG_PFNUM(sdt));
-			if (sdt & CACHE_WT)
-				db_printf(", WTHRU");
-			if (sdt & SG_SO)
-				db_printf(", S-PROT");
-			if (sdt & CACHE_GLOBAL)
-				db_printf(", GLOBAL");
-			if (sdt & CACHE_INH)
-				db_printf(", $INHIBIT");
-			if (sdt & SG_PROT)
-				db_printf(", W-PROT");
-			if (sdt & SG_V)
-				db_printf(", VALID");
-			db_printf(".\n");
-			break;
-		}
-
-		if ((sdt & SG_V) == 0) {
-			db_printf("VA 0x%08x -> segment entry 0x%8x @0x%08x not valid\n",
-			    va, sdt, value);
-			return;
-		}
-
-		value = ptoa(PG_PFNUM(sdt));
-	}
-
-	{
-		pt_entry_t pte;
-
-		if (verbose_flag)
-			db_printf("will follow to entry %d of page at 0x%x...\n",
-			    PDTIDX(va), value);
-		value |= PDTIDX(va) * sizeof(pt_entry_t);
-
-		if (badwordaddr((vaddr_t)value)) {
-			db_printf("VA 0x%08x -> page table entry @0x%08x not accessible\n",
-			    va, value);
-			return;
-		}
-
-		pte = *(pt_entry_t *)value;
-		switch (verbose_flag) {
-		case 2:
-			db_printf("PAGE DESC @0x%x is 0x%08x.\n", value, pte);
-			/* FALLTHROUGH */
-		case 1:
-			db_printf("PAGE DESC @0x%x: page @%x000",
-			    value, PG_PFNUM(pte));
-			if (pte & PG_W)
-				db_printf(", WIRE");
-			if (pte & CACHE_WT)
-				db_printf(", WTHRU");
-			if (pte & PG_SO)
-				db_printf(", S-PROT");
-			if (pte & CACHE_GLOBAL)
-				db_printf(", GLOBAL");
-			if (pte & CACHE_INH)
-				db_printf(", $INHIBIT");
-			if (pte & PG_M)
-				db_printf(", MOD");
-			if (pte & PG_U)
-				db_printf(", USED");
-			if (pte & PG_PROT)
-				db_printf(", W-PROT");
-			if (pte & PG_V)
-				db_printf(", VALID");
-			db_printf(".\n");
-			break;
-		}
-
-		if ((pte & PG_V) == 0) {
-			db_printf("VA 0x%08x -> page table entry 0x%08x @0x%08x not valid\n",
-			    va, pte, value);
-			return;
-		}
-
-		value = ptoa(PG_PFNUM(pte)) | (va & PAGE_MASK);
-	}
-
-	db_printf("VA 0x%08x -> PA 0x%08x\n", va, value);
-}
-#endif /* DDB */
-
-#ifdef DEBUG
-void
-m8820x_show_apr(apr_t value)
-{
-	printf("table @ 0x%x000", PG_PFNUM(value));
-	if (value & CACHE_WT)
-		printf(", writethrough");
-	if (value & CACHE_GLOBAL)
-		printf(", global");
-	if (value & CACHE_INH)
-		printf(", cache inhibit");
-	if (value & APR_V)
-		printf(", valid");
-	printf("\n");
-}
-#endif