diff options
| author | Miod Vallat <miod@cvs.openbsd.org> | 2015-08-15 22:31:39 +0000 |
|---|---|---|
| committer | Miod Vallat <miod@cvs.openbsd.org> | 2015-08-15 22:31:39 +0000 |
| commit | 67e1cf4d4723e5626d6b2cee6e9d91b11ba1a4d7 (patch) | |
| tree | 86d54e47ad9e50b57a6631aff2c041ad82582da9 /sys/arch/mips64/include | |
| parent | dcb7c2022e58cc762287cfa9290f01f2232fb3d1 (diff) | |
Some bits for Loongson 3A support.
Diffstat (limited to 'sys/arch/mips64/include')
| -rw-r--r-- | sys/arch/mips64/include/cache.h | 12 |
1 files changed, 11 insertions, 1 deletions
diff --git a/sys/arch/mips64/include/cache.h b/sys/arch/mips64/include/cache.h index e28d69edc8e..2b9ece4037c 100644 --- a/sys/arch/mips64/include/cache.h +++ b/sys/arch/mips64/include/cache.h @@ -1,4 +1,4 @@ -/* $OpenBSD: cache.h,v 1.6 2014/03/31 20:21:19 miod Exp $ */ +/* $OpenBSD: cache.h,v 1.7 2015/08/15 22:31:38 miod Exp $ */ /* * Copyright (c) 2012 Miodrag Vallat. @@ -60,6 +60,11 @@ CACHE_PROTOS(Octeon) CACHE_PROTOS(Loongson2) /* + * Loongson 3A and 2Gq. + */ +CACHE_PROTOS(Loongson3) + +/* * MIPS R4000 and R4400. */ CACHE_PROTOS(Mips4k) @@ -80,6 +85,11 @@ CACHE_PROTOS(tfp) CACHE_PROTOS(Mips10k) /* + * mips64r2-compliant processors. + */ +CACHE_PROTOS(mips64r2) + +/* * Values used by the IOSyncDCache routine [which acts as the backend of * bus_dmamap_sync()]. */ |