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authorVisa Hankala <visa@cvs.openbsd.org>2017-04-07 14:17:39 +0000
committerVisa Hankala <visa@cvs.openbsd.org>2017-04-07 14:17:39 +0000
commite29615c0561f730dda60f4f81fc6f2cc6a53d341 (patch)
treee68507904143e7a4d1c11b8c22b37895ff2baece /sys/arch/mips64/include
parent2140507231053c89985b20dbaf1fbe8831effcdc (diff)
Add prid for CN72xx/CN73xx.
Diffstat (limited to 'sys/arch/mips64/include')
-rw-r--r--sys/arch/mips64/include/cpu.h3
1 files changed, 2 insertions, 1 deletions
diff --git a/sys/arch/mips64/include/cpu.h b/sys/arch/mips64/include/cpu.h
index 5206d877a5d..0f31d10fdad 100644
--- a/sys/arch/mips64/include/cpu.h
+++ b/sys/arch/mips64/include/cpu.h
@@ -1,4 +1,4 @@
-/* $OpenBSD: cpu.h,v 1.114 2017/03/02 10:38:10 natano Exp $ */
+/* $OpenBSD: cpu.h,v 1.115 2017/04/07 14:17:38 visa Exp $ */
/*-
* Copyright (c) 1992, 1993
@@ -403,6 +403,7 @@ void cp0_calibrate(struct cpu_info *);
#define MIPS_LOONGSON2 0x63 /* STC LoongSon2/3 CPU ISA III+ */
#define MIPS_CN61XX 0x93 /* Cavium OCTEON II CN6[01]xx MIPS64R2 */
#define MIPS_CN71XX 0x96 /* Cavium OCTEON III CN7[01]xx MIPS64R2 */
+#define MIPS_CN73XX 0x97 /* Cavium OCTEON III CN7[23]xx MIPS64R2 */
/*
* MIPS FPU types. Only soft, rest is the same as cpu type.