Use CCA_CACHED as the default CCA for all cached mappings and addresses.

3 files changed, 26 insertions, 27 deletions

diff --git a/sys/arch/mips64/mips64/cache_r10k.S b/sys/arch/mips64/mips64/cache_r10k.S
index 7d11975816d..0bb6285dc07 100644
--- a/sys/arch/mips64/mips64/cache_r10k.S
+++ b/sys/arch/mips64/mips64/cache_r10k.S
@@ -1,4 +1,4 @@
-/*	$OpenBSD: cache_r10k.S,v 1.6 2007/10/18 04:32:25 miod Exp $ */
+/*	$OpenBSD: cache_r10k.S,v 1.7 2008/04/07 22:30:47 miod Exp $ */
 
 /*
  * Copyright (c) 2004 Opsycon AB (www.opsycon.se)
@@ -213,7 +213,7 @@ LEAF(Mips10k_SyncCache, 0)
  * Sync the instruction cache.
  */
 
-	LOAD_XKPHYS(t0, CCA_NONCOHERENT)
+	LOAD_XKPHYS(t0, CCA_CACHED)
 	PTR_ADDU t1, t0, t1			# Compute end address
 	PTR_SUBU t1, 128
 
@@ -232,7 +232,7 @@ LEAF(Mips10k_SyncCache, 0)
  * the selected cache and differs from Hit in that sense.
  */
 
-	LOAD_XKPHYS(t0, CCA_NONCOHERENT)
+	LOAD_XKPHYS(t0, CCA_CACHED)
 	PTR_ADDU t1, t0, t2			# End address
 	PTR_SUBU t1, t1, 128
 1:
@@ -250,7 +250,7 @@ LEAF(Mips10k_SyncCache, 0)
 	PTR_ADDU t0, t0, 128
 
 /* Do L2 */
-	LOAD_XKPHYS(t3, CCA_NONCOHERENT)
+	LOAD_XKPHYS(t3, CCA_CACHED)
 	lw	ta0, CpuSecondaryCacheSize	# XXX Need set size here.
 10:
 	cache	IndexWBInvalidate_S, 0(t3)
@@ -317,7 +317,7 @@ END(Mips10k_InvalidateICachePage)
  *----------------------------------------------------------------------------
  */
 LEAF(Mips10k_InvalidateICache, 0)
-	LOAD_XKPHYS(a2, CCA_NONCOHERENT)
+	LOAD_XKPHYS(a2, CCA_CACHED)
 	and	a0, 0x00ffffff			# Reduce addr to cache index
 	PTR_ADDU a1, 63				# Round up size
 	PTR_ADDU a1, a0				# Add extra from address
@@ -358,7 +358,7 @@ END(Mips10k_InvalidateICache)
  *----------------------------------------------------------------------------
  */
 LEAF(Mips10k_SyncDCachePage, 0)
-	LOAD_XKPHYS(a2, CCA_NONCOHERENT)
+	LOAD_XKPHYS(a2, CCA_CACHED)
 	dsll	a0, 34
 	dsrl	a0, 34
 	PTR_ADDU a0, a2				# a0 now new XKPHYS address
diff --git a/sys/arch/mips64/mips64/cache_r5k.S b/sys/arch/mips64/mips64/cache_r5k.S
index 207712e6fc7..67df52de0ea 100644
--- a/sys/arch/mips64/mips64/cache_r5k.S
+++ b/sys/arch/mips64/mips64/cache_r5k.S
@@ -1,4 +1,4 @@
-/*	$OpenBSD: cache_r5k.S,v 1.21 2007/10/24 20:04:26 miod Exp $ */
+/*	$OpenBSD: cache_r5k.S,v 1.22 2008/04/07 22:30:47 miod Exp $ */
 
 /*
  * Copyright (c) 1998-2004 Opsycon AB (www.opsycon.se)
@@ -240,7 +240,7 @@ Conf5K:						# R5xxx type, check for L2 cache
 
 	mtc0	v0, COP_0_CONFIG		# Enable L2 cache
 	or	t2, CTYPE_HAS_XL2		# External L2 present.
-	LOAD_XKPHYS(t0, CCA_NONCOHERENT)
+	LOAD_XKPHYS(t0, CCA_CACHED)
 	PTR_ADDU t1, t0, ta2
 1:
 	cache	InvalidateSecondaryPage, 0(t0)
@@ -270,7 +270,7 @@ Conf52K:					# R5200 type, check for L2 cache
 
 	mtc0	v0, COP_0_CONFIG		# Enable L2 cache
 	or	t2, CTYPE_HAS_XL2		# External L2 present.
-	LOAD_XKPHYS(t0, CCA_NONCOHERENT)
+	LOAD_XKPHYS(t0, CCA_CACHED)
 	PTR_ADDU t1, t0, ta2
 1:
 	cache	InvalidateSecondaryPage, 0(t0)
@@ -311,7 +311,7 @@ Conf7K:					# RM7000, check for L2 and L3 cache
 	mtc0	v0, COP_0_CONFIG		# Enable L3 cache
 	or	t2, CTYPE_HAS_XL3
 #endif
-	LOAD_XKPHYS(t0, CCA_NONCOHERENT)
+	LOAD_XKPHYS(t0, CCA_CACHED)
 	PTR_ADDU t1, t0, ta3
 1:
 	cache	InvalidatePage_T, 0(t0)
@@ -330,7 +330,7 @@ Conf7KL2:
 	ori	v0, CF_7_SE
 
 	mtc0	v0, COP_0_CONFIG		# Enable and init L2 cache
-	LOAD_XKPHYS(t0, CCA_NONCOHERENT)
+	LOAD_XKPHYS(t0, CCA_CACHED)
 	PTR_ADDU t1, t0, ta3
 1:
 	PTR_ADDU t0, 32
@@ -338,7 +338,7 @@ Conf7KL2:
 	cache	IndexStoreTag_S, -4(t0)
 	sync
 
-	LOAD_XKPHYS(t0, CCA_NONCOHERENT)
+	LOAD_XKPHYS(t0, CCA_CACHED)
 	PTR_ADDU t1, t0, ta3
 1:
 	PTR_ADDU t0, 32
@@ -346,7 +346,7 @@ Conf7KL2:
 	lw	zero, -4(t0)
 	sync
 
-	LOAD_XKPHYS(t0, CCA_NONCOHERENT)
+	LOAD_XKPHYS(t0, CCA_CACHED)
 	PTR_ADDU t1, t0, ta3
 1:
 	PTR_ADDU t0, 32
@@ -426,7 +426,7 @@ LEAF(Mips5k_SyncCache, 0)
 	mtc0	v0, COP_0_STATUS_REG		# Disable interrupts
 #endif
 
-	LOAD_XKPHYS(t0, CCA_NONCOHERENT)
+	LOAD_XKPHYS(t0, CCA_CACHED)
 	PTR_ADDU t1, t0, t1			# Compute end address
 	PTR_SUBU t1, 128
 
@@ -444,7 +444,7 @@ LEAF(Mips5k_SyncCache, 0)
  * the selected cache and differs from Hit in that sense.
  */
 
-	LOAD_XKPHYS(t0, CCA_NONCOHERENT)
+	LOAD_XKPHYS(t0, CCA_CACHED)
 	PTR_ADDU t1, t0, t2			# End address
 	PTR_SUBU t1, t1, 128
 1:
@@ -463,7 +463,7 @@ LEAF(Mips5k_SyncCache, 0)
 	nop
 
 3:
-	LOAD_XKPHYS(t3, CCA_NONCOHERENT)
+	LOAD_XKPHYS(t3, CCA_CACHED)
 	lw	ta0, CpuSecondaryCacheSize
 10:
 	cache	IndexWBInvalidate_S, 0(t3)
@@ -479,7 +479,7 @@ LEAF(Mips5k_SyncCache, 0)
 	nop
 
 	mtc0    zero, COP_0_TAG_LO
-	LOAD_XKPHYS(t3, CCA_NONCOHERENT)
+	LOAD_XKPHYS(t3, CCA_CACHED)
 	lw	ta0, CpuSecondaryCacheSize
 21:
 	cache	InvalidateSecondaryPage, 0(t3)
@@ -495,7 +495,7 @@ LEAF(Mips5k_SyncCache, 0)
 	nop
 
 	mtc0    zero, COP_0_TAG_LO
-	LOAD_XKPHYS(t3, CCA_NONCOHERENT)
+	LOAD_XKPHYS(t3, CCA_CACHED)
 	lw	ta0, CpuTertiaryCacheSize
 31:
 	cache	InvalidatePage_T, 0(t3)
@@ -586,7 +586,7 @@ LEAF(Mips5k_InvalidateICache, 0)
 	lw	v0, CpuNWayCache		# Cache properties
 	lw	t0, CpuPrimaryInstSetSize	# Set size
 	and	a0, 0x00ffffff			# Reduce addr to cache index
-	LOAD_XKPHYS(a2, CCA_NONCOHERENT)
+	LOAD_XKPHYS(a2, CCA_CACHED)
 	PTR_ADDU a1, 31				# Round up size
 	PTR_ADDU a1, a0				# Add extra from address
 	and	a0, -32				# Align start address
@@ -648,7 +648,7 @@ LEAF(Mips5k_SyncDCachePage, 0)
 	li	v0, SR_DIAG_DE
 	mtc0	v0, COP_0_STATUS_REG		# Disable interrupts
 #endif
-	LOAD_XKPHYS(a2, CCA_NONCOHERENT)
+	LOAD_XKPHYS(a2, CCA_CACHED)
 	lw	v0, CpuNWayCache
 	dsll	a0, 34
 	dsrl	a0, 34
diff --git a/sys/arch/mips64/mips64/pmap.c b/sys/arch/mips64/mips64/pmap.c
index 7ba10cbefb4..38553ea56f6 100644
--- a/sys/arch/mips64/mips64/pmap.c
+++ b/sys/arch/mips64/mips64/pmap.c
@@ -1,4 +1,4 @@
-/*	$OpenBSD: pmap.c,v 1.32 2008/02/11 20:40:32 miod Exp $	*/
+/*	$OpenBSD: pmap.c,v 1.33 2008/04/07 22:30:48 miod Exp $	*/
 
 /*
  * Copyright (c) 2001-2004 Opsycon AB  (www.opsycon.se / www.opsycon.com)
@@ -40,7 +40,6 @@
 
 #include <machine/cpu.h>
 #include <machine/autoconf.h>
-#include <machine/memconf.h>
 #include <machine/vmparam.h>
 #include <mips64/archtype.h>
 
@@ -231,7 +230,7 @@ pmap_steal_memory(vsize_t size, vaddr_t *vstartp, vaddr_t *vendp)
 		if (pa + size < KSEG_SIZE)
 			va = PHYS_TO_KSEG0(pa);
 		else
-			va = PHYS_TO_XKPHYS(pa, CCA_NONCOHERENT);
+			va = PHYS_TO_XKPHYS(pa, CCA_CACHED);
 
 		bzero((void *)va, size);
 		return (va);
@@ -925,7 +924,7 @@ pmap_zero_page(struct vm_page *pg)
 
 	DPRINTF(PDB_FOLLOW, ("pmap_zero_page(%p)\n", phys));
 
-	va = (vaddr_t)PHYS_TO_XKPHYS(phys, CCA_NONCOHERENT);
+	va = (vaddr_t)PHYS_TO_XKPHYS(phys, CCA_CACHED);
 	pv = pg_to_pvh(pg);
 	if ((pg->pg_flags & PV_CACHED) &&
 	    ((pv->pv_va ^ va) & CpuCacheAliasMask) != 0) {
@@ -953,8 +952,8 @@ pmap_copy_page(struct vm_page *srcpg, struct vm_page *dstpg)
 
 	src = VM_PAGE_TO_PHYS(srcpg);
 	dst = VM_PAGE_TO_PHYS(dstpg);
-	s = (vaddr_t)PHYS_TO_XKPHYS(src, CCA_NONCOHERENT);
-	d = (vaddr_t)PHYS_TO_XKPHYS(dst, CCA_NONCOHERENT);
+	s = (vaddr_t)PHYS_TO_XKPHYS(src, CCA_CACHED);
+	d = (vaddr_t)PHYS_TO_XKPHYS(dst, CCA_CACHED);
 
 	DPRINTF(PDB_FOLLOW, ("pmap_copy_page(%p, %p)\n", src, dst));
 
@@ -1151,7 +1150,7 @@ pmap_page_alloc(vaddr_t *ret)
 	if (pg == NULL)
 		return ENOMEM;
 
-	*ret = PHYS_TO_XKPHYS(VM_PAGE_TO_PHYS(pg), CCA_NONCOHERENT);
+	*ret = PHYS_TO_XKPHYS(VM_PAGE_TO_PHYS(pg), CCA_CACHED);
 	return 0;
 }