Fix setting the SMP bit in the Auxiliary Control Register. The old code was

toggling the bit, clearing it when already set.  On Cortex-A7 setting the SMP
bit is essential since without it the CPU doesn't actually use its caches.

The SMP bit supposed to be set before turning on the caches and the MMU, so
move the setting of the Auxiliary Control Register before setting the
System Control Register.

ok jsg@

0 files changed, 0 insertions, 0 deletions