Support for MVME141 boards. Tested with both VME and VSB memory boards

(and MVME327 SCSI and MVME376 Ethernet, to provide a complete system).

10 files changed, 581 insertions, 109 deletions

diff --git a/sys/arch/mvme68k/dev/clock.c b/sys/arch/mvme68k/dev/clock.c
index 92bdce49437..0963ee132c8 100644
--- a/sys/arch/mvme68k/dev/clock.c
+++ b/sys/arch/mvme68k/dev/clock.c
@@ -1,4 +1,4 @@
-/*	$OpenBSD: clock.c,v 1.15 2009/03/01 21:40:49 miod Exp $ */
+/*	$OpenBSD: clock.c,v 1.16 2009/03/01 22:08:13 miod Exp $ */
 
 /*
  * Copyright (c) 1995 Theo de Raadt
@@ -74,6 +74,7 @@
 
 #include "lrc.h"
 #include "mc.h"
+#include "ofobio.h"
 #include "pcc.h"
 #include "pcctwo.h"
 
@@ -83,6 +84,9 @@
 #if NMC > 0
 #include <mvme68k/dev/mcreg.h>
 #endif
+#if NOFOBIO > 0
+#include <mvme68k/dev/ofobioreg.h>
+#endif
 #if NPCC > 0
 #include <mvme68k/dev/pccreg.h>
 #endif
@@ -175,6 +179,11 @@ clockattach(parent, self, args)
 		mcintr_establish(MCV_TIMER2, &sc->sc_statih, "stat");
 		break;
 #endif
+#if NOFOBIO > 0
+	case BUS_OFOBIO:
+		intr_establish(OFOBIOVEC_CLOCK, &sc->sc_profih, "clock");
+		break;
+#endif
 #if NPCC > 0
 	case BUS_PCC:
 		prof_reset = ca->ca_ipl | PCC_IRQ_IEN | PCC_TIMERACK;
@@ -209,6 +218,11 @@ clockintr(arg)
 		/* nothing to do */
 		break;
 #endif
+#if NOFOBIO > 0
+	case BUS_OFOBIO:
+		sys_ofobio->csr_c &= ~OFO_CSRC_TIMER_ACK;
+		break;
+#endif
 #if NMC > 0
 	case BUS_MC:
 		sys_mc->mc_t1irq = prof_reset;
@@ -231,8 +245,7 @@ clockintr(arg)
 }
 
 /*
- * Set up real-time clock; we don't have a statistics clock at
- * present.
+ * Set up real-time and, if available, statistics clock.
  */
 void
 cpu_initclocks()
@@ -259,7 +272,7 @@ cpu_initclocks()
 	switch (clockbus) {
 #if NLRC > 0
 	case BUS_LRC:
-		profhz = stathz = 0;
+		profhz = stathz = 0;	/* only one timer available for now */
 
 		sys_lrc->lrc_tcr0 = 0;
 		sys_lrc->lrc_tcr1 = 0;
@@ -269,6 +282,13 @@ cpu_initclocks()
 		sys_lrc->lrc_tcr2 = TCR_TEN2 | TCR_TCYC2 | TCR_T2IE;
 		break;
 #endif
+#if NOFOBIO > 0
+	case BUS_OFOBIO:
+		profhz = stathz = 0;	/* only one timer available */
+
+		ofobio_clocksetup();
+		break;
+#endif
 #if NMC > 0
 	case BUS_MC:
 		/* profclock */
@@ -400,7 +420,7 @@ void
 delay(us)
 	int us;
 {
-#if NPCC > 0
+#if NPCC > 0 || NOFOBIO > 0
 	volatile register int c;
 #endif
 
@@ -449,12 +469,15 @@ delay(us)
 	}
 		break;
 #endif
-#if NPCC > 0
+#if NPCC > 0 || NOFOBIO > 0
 	case BUS_PCC:
+	case BUS_OFOBIO:
 		/*
 		 * XXX MVME147 doesn't have a 3rd free-running timer,
 		 * so we use a stupid loop. Fix the code to watch t1:
 		 * the profiling timer.
+		 * MVME141 only has one timer, so there is no hope
+		 * either.
 		 */
 		c = 2 * us;
 		while (--c > 0)
diff --git a/sys/arch/mvme68k/dev/dart.c b/sys/arch/mvme68k/dev/dart.c
index c79dacceaad..c619db6353e 100644
--- a/sys/arch/mvme68k/dev/dart.c
+++ b/sys/arch/mvme68k/dev/dart.c
@@ -1,4 +1,4 @@
-/*	$OpenBSD: dart.c,v 1.1 2009/03/01 21:40:49 miod Exp $	*/
+/*	$OpenBSD: dart.c,v 1.2 2009/03/01 22:08:13 miod Exp $	*/
 
 /*
  * Mach Operating System
@@ -68,14 +68,29 @@ void	dartrint(struct dartsoftc *, int);
 void	dartxint(struct dartsoftc *, int);
 
 /*
- * DUART registers are mapped as the least-significant byte of 32-bit
- * addresses. The following macros hide this.
+ * DUART registers are sometimes mapped as the least-significant byte
+ * of 32-bit addresses. The following macros hide this.
  */
 
-#define	dart_read(sc, reg) \
-	bus_space_read_1((sc)->sc_iot, (sc)->sc_ioh, 3 + ((reg) << 2))
-#define	dart_write(sc, reg, val) \
-	bus_space_write_1((sc)->sc_iot, (sc)->sc_ioh, 3 + ((reg) << 2), (val))
+static __inline uint8_t dart_read(struct dartsoftc *, uint);
+static __inline void dart_write(struct dartsoftc *, uint, uint);
+
+static __inline uint8_t
+dart_read(struct dartsoftc *sc, uint reg)
+{
+	if (sc->sc_stride != 0)
+		return bus_space_read_1(sc->sc_iot, sc->sc_ioh, 3 + (reg << 2));
+	else
+		return bus_space_read_1(sc->sc_iot, sc->sc_ioh, reg);
+}
+static __inline void
+dart_write(struct dartsoftc *sc, uint reg, uint val)
+{
+	if (sc->sc_stride != 0)
+		bus_space_write_1(sc->sc_iot, sc->sc_ioh, 3 + (reg << 2), val);
+	else
+		bus_space_write_1(sc->sc_iot, sc->sc_ioh, reg, val);
+}
 
 #define	DART_CHIP(dev)	(minor(dev) >> 1)
 #define DART_PORT(dev)	(minor(dev) & 1)
@@ -122,16 +137,16 @@ dart_common_attach(struct dartsoftc *sc)
 	/* reset port a */
 	if (sc->sc_console == 0 || CONS_PORT != A_PORT) {
 		dart_write(sc, DART_CRA, RXRESET | TXDIS | RXDIS);
-		DELAY_CR;
+		delay(1);
 		dart_write(sc, DART_CRA, TXRESET | TXDIS | RXDIS);
-		DELAY_CR;
+		delay(1);
 		dart_write(sc, DART_CRA, ERRRESET | TXDIS | RXDIS);
-		DELAY_CR;
+		delay(1);
 		dart_write(sc, DART_CRA, BRKINTRESET | TXDIS | RXDIS);
-		DELAY_CR;
+		delay(1);
 		dart_write(sc, DART_CRA, MRRESET | TXDIS | RXDIS);
 #if 0
-		DELAY_CR;
+		delay(1);
 #endif
 
 		dart_write(sc, DART_MR1A, sc->sc_sv_reg->sv_mr1[A_PORT]);
@@ -143,16 +158,16 @@ dart_common_attach(struct dartsoftc *sc)
 	/* reset port b */
 	if (sc->sc_console == 0 || CONS_PORT != B_PORT) {
 		dart_write(sc, DART_CRB, RXRESET | TXDIS | RXDIS);
-		DELAY_CR;
+		delay(1);
 		dart_write(sc, DART_CRB, TXRESET | TXDIS | RXDIS);
-		DELAY_CR;
+		delay(1);
 		dart_write(sc, DART_CRB, ERRRESET | TXDIS | RXDIS);
-		DELAY_CR;
+		delay(1);
 		dart_write(sc, DART_CRB, BRKINTRESET | TXDIS | RXDIS);
-		DELAY_CR;
+		delay(1);
 		dart_write(sc, DART_CRB, MRRESET | TXDIS | RXDIS);
 #if 0
-		DELAY_CR;
+		delay(1);
 #endif
 
 		dart_write(sc, DART_MR1B, sc->sc_sv_reg->sv_mr1[B_PORT]);
@@ -168,6 +183,8 @@ dart_common_attach(struct dartsoftc *sc)
 	dart_write(sc, DART_CTUR, SLCTIM >> 8);
 	dart_write(sc, DART_CTLR, SLCTIM & 0xff);
 	dart_write(sc, DART_ACR, BDSET2 | CCLK16 | IPDCDIB | IPDCDIA);
+#else
+	dart_write(sc, DART_ACR, IPDCDIB | IPDCDIA);
 #endif
 	dart_write(sc, DART_IMR, sc->sc_sv_reg->sv_imr);
 	dart_write(sc, DART_OPCR, OPSET);
@@ -544,7 +561,7 @@ dartparam(struct tty *tp, struct termios *t)
 
 	/* re-enable the receiver */
 #if 0
-	DELAY_CR;
+	delay(1);
 #endif
 	sc->sc_sv_reg->sv_imr |= port == A_PORT ? IRXRDYA : IRXRDYB;
 	dart_write(sc, DART_IMR, sc->sc_sv_reg->sv_imr);
@@ -734,7 +751,7 @@ dartrint(struct dartsoftc *sc, int port)
 		if (sr & RBRK) {
 			/* clear break state */
 			dart_write(sc, ptaddr + DART_CRA, BRKINTRESET);
-			DELAY_CR;
+			delay(1);
 			dart_write(sc, ptaddr + DART_CRA, ERRRESET);
 
 #if defined(DDB)
@@ -854,18 +871,47 @@ dartintr(void *arg)
  * Console interface routines.
  */
 
-#define	dart_cnread(reg) \
-	*(volatile u_int8_t *)(IIOV(CONSOLE_DART_BASE) + 3 + ((reg) << 2))
-#define	dart_cnwrite(reg, val) \
-	*(volatile u_int8_t *)(IIOV(CONSOLE_DART_BASE) + 3 + ((reg) << 2)) = (val)
+static vaddr_t dartcnva;
+static uint dartcnstride;
+
+static __inline uint8_t dart_cnread(uint);
+static __inline void dart_cnwrite(uint, uint);
+
+static __inline uint8_t
+dart_cnread(uint reg)
+{
+	if (dartcnstride != 0)
+		return *(volatile u_int8_t *)(dartcnva + 3 + (reg << 2));
+	else
+		return *(volatile u_int8_t *)(dartcnva + reg);
+}
+static __inline void
+dart_cnwrite(uint reg, uint val)
+{
+	if (dartcnstride != 0)
+		*(volatile u_int8_t *)(dartcnva + 3 + (reg << 2)) = val;
+	else
+		*(volatile u_int8_t *)(dartcnva + reg) = val;
+}
+
 
 void
 dartcnprobe(struct consdev *cp)
 {
 	int maj;
 
-	if (cputyp != CPU_165)
+	switch (cputyp) {
+	case CPU_141:
+		dartcnva = IIOV(MVME141_DART_BASE);
+		dartcnstride = 0;
+		break;
+	case CPU_165:
+		dartcnva = IIOV(MVME165_DART_BASE);
+		dartcnstride = 2;
+		break;
+	default:
 		return;
+	}
 
 	/* locate the major number */
 	for (maj = 0; maj < nchrdev; maj++)
@@ -891,15 +937,15 @@ dartcninit(cp)
 	dartcn_sv.sv_imr = IIPCHG;
 
 	dart_cnwrite(DART_CRA, RXRESET | TXDIS | RXDIS);
-	DELAY_CR;
+	delay(1);
 	dart_cnwrite(DART_CRA, TXRESET | TXDIS | RXDIS);
-	DELAY_CR;
+	delay(1);
 	dart_cnwrite(DART_CRA, ERRRESET | TXDIS | RXDIS);
-	DELAY_CR;
+	delay(1);
 	dart_cnwrite(DART_CRA, BRKINTRESET | TXDIS | RXDIS);
-	DELAY_CR;
+	delay(1);
 	dart_cnwrite(DART_CRA, MRRESET | TXDIS | RXDIS);
-	DELAY_CR;
+	delay(1);
 
 	dart_cnwrite(DART_MR1A, dartcn_sv.sv_mr1[CONS_PORT]);
 	dart_cnwrite(DART_MR2A, dartcn_sv.sv_mr2[CONS_PORT]);
@@ -928,7 +974,7 @@ dartcnputc(dev_t dev, int c)
 	    (CONS_PORT == A_PORT ? ~ITXRDYA : ~ITXRDYB));
 	/* make sure transmitter is enabled */
 #if 0
-	DELAY_CR;
+	delay(1);
 #endif
 	dart_cnwrite(ptaddr + DART_CRA, TXEN);
 
@@ -943,7 +989,7 @@ dartcnputc(dev_t dev, int c)
 	/* restore the previous state */
 	dart_cnwrite(DART_IMR, dartcn_sv.sv_imr);
 #if 0
-	DELAY_CR;
+	delay(1);
 #endif
 	dart_cnwrite(ptaddr + DART_CRA, dartcn_sv.sv_cr[0]);
 
@@ -980,7 +1026,7 @@ dartcngetc(dev_t dev)
 			if (sr & RBRK) {
 				/* clear break state */
 				dart_cnwrite(ptaddr + DART_CRA, BRKINTRESET);
-				DELAY_CR;
+				delay(2);
 				dart_cnwrite(ptaddr + DART_CRA, ERRRESET);
 				break;
 			}
diff --git a/sys/arch/mvme68k/dev/dart_lrc.c b/sys/arch/mvme68k/dev/dart_lrc.c
index 576af188e1a..f0bc8d01b61 100644
--- a/sys/arch/mvme68k/dev/dart_lrc.c
+++ b/sys/arch/mvme68k/dev/dart_lrc.c
@@ -1,4 +1,4 @@
-/*	$OpenBSD: dart_lrc.c,v 1.1 2009/03/01 21:40:49 miod Exp $	*/
+/*	$OpenBSD: dart_lrc.c,v 1.2 2009/03/01 22:08:13 miod Exp $	*/
 /*
  * Copyright (c) 2006, 2009, Miodrag Vallat
  *
@@ -36,8 +36,8 @@
 #include <mvme68k/dev/dartreg.h>
 #include <mvme68k/dev/dartvar.h>
 
-int	dart_lrc_match(struct device *parent, void *self, void *aux);
-void	dart_lrc_attach(struct device *parent, struct device *self, void *aux);
+int	dart_lrc_match(struct device *, void *, void *);
+void	dart_lrc_attach(struct device *, struct device *, void *);
 
 struct cfattach dartlrc_ca = {
 	sizeof(struct dartsoftc), dart_lrc_match, dart_lrc_attach
@@ -52,13 +52,7 @@ dart_lrc_match(struct device *parent, void *cf, void *aux)
 	int rc;
 #endif
 
-	if (cputyp != CPU_165)
-		return (0);
-
-	/*
-	 * We do not accept empty locators here...
-	 */
-	if (ca->ca_paddr != CONSOLE_DART_BASE)
+	if (cputyp != CPU_165 || ca->ca_paddr != MVME165_DART_BASE)
 		return (0);
 
 #if 0	/* overkill, this is the console so if we've run so far, it exists */
@@ -102,5 +96,6 @@ dart_lrc_attach(struct device *parent, struct device *self, void *aux)
 	lrcintr_establish(LRCVEC_DART, &sc->sc_ih, self->dv_xname);
 
 	sc->sc_vec = LRC_VECBASE + LRCVEC_DART;
+	sc->sc_stride = 2;
 	dart_common_attach(sc);
 }
diff --git a/sys/arch/mvme68k/dev/dart_ofobio.c b/sys/arch/mvme68k/dev/dart_ofobio.c
new file mode 100644
index 00000000000..26b032ab5c8
--- /dev/null
+++ b/sys/arch/mvme68k/dev/dart_ofobio.c
@@ -0,0 +1,100 @@
+/*	$OpenBSD: dart_ofobio.c,v 1.1 2009/03/01 22:08:13 miod Exp $	*/
+/*
+ * Copyright (c) 2006, 2009, Miodrag Vallat
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <sys/param.h>
+#include <sys/systm.h>
+#include <sys/device.h>
+
+#include <machine/autoconf.h>
+#include <machine/cpu.h>
+
+#include <mvme68k/dev/ofobioreg.h>
+
+#include <mvme68k/dev/dartreg.h>
+#include <mvme68k/dev/dartvar.h>
+
+int	dart_ofobio_match(struct device *, void *, void *);
+void	dart_ofobio_attach(struct device *, struct device *, void *);
+
+struct cfattach dartofobio_ca = {
+	sizeof(struct dartsoftc), dart_ofobio_match, dart_ofobio_attach
+};
+
+int
+dart_ofobio_match(struct device *parent, void *cf, void *aux)
+{
+	struct confargs *ca = aux;
+#if 0
+	bus_space_handle_t ioh;
+	int rc;
+#endif
+
+	if (cputyp != CPU_141 || ca->ca_paddr != MVME141_DART_BASE)
+		return (0);
+
+#if 0	/* overkill, this is the console so if we've run so far, it exists */
+	if (bus_space_map(ca->ca_iot, ca->ca_paddr, DART_SIZE, 0, &ioh) != 0)
+		return (0);
+	rc = badvaddr((vaddr_t)bus_space_vaddr(ca->ca_iot, ioh) + 3, 1);
+	bus_space_unmap(ca->ca_iot, ca->ca_paddr, DART_SIZE);
+
+	return (rc == 0);
+#else
+	return (1);
+#endif
+}
+
+void
+dart_ofobio_attach(struct device *parent, struct device *self, void *aux)
+{
+	struct dartsoftc *sc = (struct dartsoftc *)self;
+	struct confargs *ca = aux;
+	bus_space_handle_t ioh;
+
+	if (ca->ca_ipl < 0)
+		ca->ca_ipl = IPL_TTY;
+
+	sc->sc_iot = ca->ca_iot;
+	if (bus_space_map(sc->sc_iot, ca->ca_paddr, DART_SIZE, 0, &ioh) != 0) {
+		printf(": can't map registers!\n");
+		return;
+	}
+	sc->sc_ioh = ioh;
+
+	sc->sc_console = 1;	/* there can't be any other */
+	printf(": console");
+
+	/* enable interrupts */
+	sc->sc_ih.ih_fn = dartintr;
+	sc->sc_ih.ih_arg = sc;
+	sc->sc_ih.ih_wantframe = 0;
+	sc->sc_ih.ih_ipl = ca->ca_ipl;
+
+	sc->sc_vec = OFOBIOVEC_DART;
+	intr_establish(sc->sc_vec, &sc->sc_ih, self->dv_xname);
+	sc->sc_stride = 0;
+	dart_common_attach(sc);
+}
diff --git a/sys/arch/mvme68k/dev/dartreg.h b/sys/arch/mvme68k/dev/dartreg.h
index bc364589ae0..35e9bebdbcb 100644
--- a/sys/arch/mvme68k/dev/dartreg.h
+++ b/sys/arch/mvme68k/dev/dartreg.h
@@ -1,17 +1,49 @@
-/*	$OpenBSD: dartreg.h,v 1.1 2009/03/01 21:40:49 miod Exp $	*/
+/*	$OpenBSD: dartreg.h,v 1.2 2009/03/01 22:08:13 miod Exp $	*/
 
-#define	CONSOLE_DART_BASE	0xfffd0000	/* on MVME165 */
+#define	MVME141_DART_BASE	0xfff70000
+#define	MVME165_DART_BASE	0xfffd0000
 
 #define MAXPORTS	2		/* max count of PORTS/DUART */
 
 #define  A_PORT   0
 #define  B_PORT   1
 
-/* the access to the same command register must be delayed,
-   because the chip has some hardware problems in this case */
-#define DELAY_CR   delay(2)
+/*
+ *	MC68681 hardware registers.
+ */
+
+#define	DART_MR1A	0x00	/* RW: mode register A */
+#define	DART_MR2A	0x00	/* RW: mode register A */
+#define	DART_SRA	0x01	/* R: status register A */
+#define	DART_CSRA	0x01	/* W: clock select register A */
+#define	DART_CRA	0x02	/* W: command register A */
+#define	DART_RBA	0x03	/* R: receiver buffer A */
+#define	DART_TBA	0x03	/* W: transmit buffer A */
+#define	DART_IPCR	0x04	/* R: input port change register */
+#define	DART_ACR	0x04	/* W: auxiliary control register */
+#define	DART_ISR	0x05	/* R: interrupt status register */
+#define	DART_IMR	0x05	/* W: interrupt mask register */
+#define	DART_CUR	0x06	/* R: count upper register */
+#define	DART_CTUR	0x06	/* W: counter/timer upper register */
+#define	DART_CLR	0x07	/* R: count lower register */
+#define	DART_CTLR	0x07	/* W: counter/timer lower register */
+#define	DART_MR1B	0x08	/* RW: mode register B */
+#define	DART_MR2B	0x08	/* RW: mode register B */
+#define	DART_SRB	0x09	/* R: status register B */
+#define	DART_CSRB	0x09	/* W: clock select register B */
+#define	DART_CRB	0x0a	/* W: command register B */
+#define	DART_RBB	0x0b	/* R: receiver buffer B */
+#define	DART_TBB	0x0b	/* W: transmit buffer B */
+#define	DART_IVR	0x0c	/* RW: interrupt vector register */
+#define	DART_IP		0x0d	/* R: input port (unlatched) */
+#define	DART_OPCR	0x0d	/* W: output port configuration register */
+#define	DART_CTSTART	0x0e	/* R: start counter command */
+#define	DART_OPRS	0x0e	/* W: output port bit set */
+#define	DART_CTSTOP	0x0f	/* R: stop counter command */
+#define	DART_OPRR	0x0f	/* W: output port bit reset */
 
-/*********************** MC68681 DEFINITIONS ************************/
+#define	DART_A_BASE	0x00
+#define	DART_B_BASE	0x08
 
 /* mode register 1: MR1x operations */
 #define RXRTS        0x80  /* enable receiver RTS */
@@ -38,7 +70,7 @@
 
 /* clock-select register: CSRx operations */
 #define NOBAUD       -1    /* 50 and 200 baud are not possible */
-/* they are not in Baud register set 2 */
+			   /* they are not in Baud register set 2 */
 #define BD75         0x00  /* 75 baud */
 #define BD110        0x11  /* 110 baud */
 #define BD134        0x22  /* 134.5 baud */
@@ -52,9 +84,6 @@
 #define BD9600       0xbb  /* 9600 baud */
 #define BD19200      0xcc  /* 19200 baud */
 
-#define DEFBAUD      BD9600   /* default value if baudrate is not possible */
-
-
 /* channel command register: CRx operations */
 #define MRRESET      0x10  /* reset mr pointer to mr1 */
 #define RXRESET      0x20  /* reset receiver */
@@ -93,15 +122,14 @@
 #define BDSET2       0x80  /* baudrate generator set 2 */
 #define CCLK1        0x60  /* timer clock: external rate.  TA */
 #define CCLK16       0x30  /* counter clock: x1 clk divided by 16 */
+#define IPDCDIB      0x08  /* IP3 change == DCD input on port B */
+#define IPDCDIA      0x04  /* IP2 change == DCD input on port A */
 
 /* input port change register: IPCR operations */
 #define IPCRDCDB     0x80  /* IP3 change == DCD change on port B */
 #define IPCRDCDA     0x40  /* IP2 change == DCD change on port A */
-
-/* Defines for mvme335 */
 #define IPDCDB       0x20  /* DCD line input b */
 #define IPDCDA       0x10  /* DCD line input a */
-
 #define IPDSRB       0x08  /* DSR line input b */
 #define IPDSRA       0x04  /* DSR line input a */
 #define IPCTSB       0x02  /* CTS line input b */
@@ -116,40 +144,3 @@
 #define IBRKA        0x04  /* delta break a */
 #define IRXRDYA      0x02  /* receiver ready a */
 #define ITXRDYA      0x01  /* transmitter ready a */
-
-/*
- *	MC68681 hardware registers.
- */
-
-#define	DART_MR1A	0x00	/* RW: mode register A */
-#define	DART_MR2A	0x00	/* RW: mode register A */
-#define	DART_SRA	0x01	/* R: status register A */
-#define	DART_CSRA	0x01	/* W: clock select register A */
-#define	DART_CRA	0x02	/* W: command register A */
-#define	DART_RBA	0x03	/* R: receiver buffer A */
-#define	DART_TBA	0x03	/* W: transmit buffer A */
-#define	DART_IPCR	0x04	/* R: input port change register */
-#define	DART_ACR	0x04	/* W: auxiliary control register */
-#define	DART_ISR	0x05	/* R: interrupt status register */
-#define	DART_IMR	0x05	/* W: interrupt mask register */
-#define	DART_CUR	0x06	/* R: count upper register */
-#define	DART_CTUR	0x06	/* W: counter/timer upper register */
-#define	DART_CLR	0x07	/* R: count lower register */
-#define	DART_CTLR	0x07	/* W: counter/timer lower register */
-#define	DART_MR1B	0x08	/* RW: mode register B */
-#define	DART_MR2B	0x08	/* RW: mode register B */
-#define	DART_SRB	0x09	/* R: status register B */
-#define	DART_CSRB	0x09	/* W: clock select register B */
-#define	DART_CRB	0x0a	/* W: command register B */
-#define	DART_RBB	0x0b	/* R: receiver buffer B */
-#define	DART_TBB	0x0b	/* W: transmit buffer B */
-#define	DART_IVR	0x0c	/* RW: interrupt vector register */
-#define	DART_IP		0x0d	/* R: input port (unlatched) */
-#define	DART_OPCR	0x0d	/* W: output port configuration register */
-#define	DART_CTSTART	0x0e	/* R: start counter command */
-#define	DART_OPRS	0x0e	/* W: output port bit set */
-#define	DART_CTSTOP	0x0f	/* R: stop counter command */
-#define	DART_OPRR	0x0f	/* W: output port bit reset */
-
-#define	DART_A_BASE	0x00
-#define	DART_B_BASE	0x08
diff --git a/sys/arch/mvme68k/dev/dartvar.h b/sys/arch/mvme68k/dev/dartvar.h
index 78a28fac00b..3258e85911e 100644
--- a/sys/arch/mvme68k/dev/dartvar.h
+++ b/sys/arch/mvme68k/dev/dartvar.h
@@ -1,4 +1,4 @@
-/*	$OpenBSD: dartvar.h,v 1.1 2009/03/01 21:40:49 miod Exp $	*/
+/*	$OpenBSD: dartvar.h,v 1.2 2009/03/01 22:08:13 miod Exp $	*/
 
 /*
  * Mach Operating System
@@ -51,6 +51,7 @@ struct dartsoftc {
 
 	int			sc_console;
 	int			sc_vec;
+	uint			sc_stride;
 
 	struct dart_sv_reg	*sc_sv_reg;
 	struct dart_sv_reg	sc_sv_reg_storage;
diff --git a/sys/arch/mvme68k/dev/nvram.c b/sys/arch/mvme68k/dev/nvram.c
index 2b843833641..00bebf8208b 100644
--- a/sys/arch/mvme68k/dev/nvram.c
+++ b/sys/arch/mvme68k/dev/nvram.c
@@ -1,4 +1,4 @@
-/*	$OpenBSD: nvram.c,v 1.19 2009/03/01 21:40:49 miod Exp $ */
+/*	$OpenBSD: nvram.c,v 1.20 2009/03/01 22:08:13 miod Exp $ */
 
 /*
  * Copyright (c) 1995 Theo de Raadt
@@ -94,11 +94,21 @@ nvramattach(parent, self, args)
 	sc->sc_paddr = ca->ca_paddr;
 	sc->sc_vaddr = (vaddr_t)ca->ca_vaddr;
 
-	sc->sc_len = MK48T08_SIZE;
+	switch (cputyp) {
+	default:
+		sc->sc_len = MK48T08_SIZE;
+		break;
+#ifdef MVME141
+	case CPU_141:
+		sc->sc_len = MK48T02_SIZE;
+		break;
+#endif
 #ifdef MVME147
-	if (cputyp == CPU_147)
+	case CPU_147:
 		sc->sc_len = MK48T02_SIZE;
+		break;
 #endif
+	}
 
 	/*
 	 * On the MVME165, the MK48T08 is mapped as one byte per longword,
diff --git a/sys/arch/mvme68k/dev/ofobio.c b/sys/arch/mvme68k/dev/ofobio.c
new file mode 100644
index 00000000000..35d469e609e
--- /dev/null
+++ b/sys/arch/mvme68k/dev/ofobio.c
@@ -0,0 +1,214 @@
+/*	$OpenBSD: ofobio.c,v 1.1 2009/03/01 22:08:13 miod Exp $	*/
+
+/*
+ * Copyright (c) 2009 Miodrag Vallat.
+ *
+ * Permission to use, copy, modify, and distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+/*
+ * MVME141 On-board resources (One-Four-One OBIO)
+ *
+ * Unlike other MVME boards supported under OpenBSD/mvme68k, there is no
+ * specific ASIC (lrc, mc2, pcc, pcc2...) providing a solid base to which
+ * all other devices are related.
+ *
+ * Instead, we have four registers, and no timers. The onboard devices
+ * (MC6861 providing serial ports and the clock, VMEchip, VSBchip and
+ * NVRAM) may as well attach to mainbus. We nevertheless attach them at
+ * ofobio to make things simpler in the kernel.
+ */
+
+#include <sys/param.h>
+#include <sys/systm.h>
+#include <sys/device.h>
+#include <sys/kernel.h>
+
+#include <uvm/uvm_extern.h>
+
+#include <machine/autoconf.h>
+#include <machine/cpu.h>
+
+#include <mvme68k/dev/ofobioreg.h>
+#include <mvme68k/dev/dartreg.h>
+
+struct ofobioreg *sys_ofobio;
+
+struct ofobiosoftc {
+	struct device	  sc_dev;
+	struct ofobioreg *sc_regs;
+	struct intrhand	  sc_abortih;
+};
+
+int	ofobioabort(void *);
+void	ofobioattach(struct device *, struct device *, void *);
+int	ofobiomatch(struct device *, void *, void *);
+int	ofobioprint(void *, const char *);
+int	ofobioscan(struct device *, void *, void *);
+
+struct cfattach ofobio_ca = {
+	sizeof(struct ofobiosoftc), ofobiomatch, ofobioattach
+};
+
+struct cfdriver ofobio_cd = {
+	NULL, "ofobio", DV_DULL
+};
+
+int
+ofobiomatch(struct device *parent, void *cf, void *aux)
+{
+	if (cputyp != CPU_141 || sys_ofobio != NULL)
+		return (0);
+
+	return (1);
+}
+
+void
+ofobioattach(struct device *parent, struct device *self, void *aux)
+{
+#if 0
+	struct confargs *ca = aux;
+#endif
+	struct ofobiosoftc *sc = (struct ofobiosoftc *)self;
+
+	sys_ofobio = sc->sc_regs = (struct ofobioreg *)IIOV(OFOBIO_CSR_ADDR);
+
+	/* disable VSB and timer interrupts */
+	sc->sc_regs->csr_b |= OFO_CSRB_VSB_INTDIS | OFO_CSRB_TIMER_INTDIS;
+	/* enable A32 addressing and device interrupts */
+	sc->sc_regs->csr_b &= ~(OFO_CSRB_GLOBAL_INTDIS | OFO_CSRB_DISABLE_A24);
+
+	/*
+	 * A note regarding the board cache: the on-board 32KB are used
+	 * during early BUG bootstrap, until off-board memory is found,
+	 * and is intended to be used by the operating system as cache
+	 * memory (in addition to the small instruction cache internal to
+	 * the 68030).
+	 *
+	 * The cache flush and cache invalidation routines in locore
+	 * are not modified to invalidate the board cache as well,
+	 * since its snooping appears to be good enough to make it
+	 * completely transparent (the fact that vsbic(4) works, relying
+	 * to proper invalidate behaviour, is a good omen).
+	 */
+
+	/* clear board cache, then enable it */
+	sc->sc_regs->csr_a |= OFO_CSRA_CACHE_WDIS | OFO_CSRA_CACHE_RDIS;
+	sc->sc_regs->csr_a |= OFO_CSRA_CACHE_CLEAR;
+	sc->sc_regs->csr_a = OFO_CSRA_CACHE_MONITOR;
+
+	printf(": board cache enabled\n");
+
+	sc->sc_abortih.ih_fn = ofobioabort;
+	sc->sc_abortih.ih_ipl = IPL_HIGH;
+	sc->sc_abortih.ih_wantframe = 1;
+	intr_establish(OFOBIOVEC_ABORT, &sc->sc_abortih, self->dv_xname);
+
+	config_search(ofobioscan, self, aux);
+}
+
+int
+ofobioprint(void *aux, const char *pnp)
+{
+	struct confargs *ca = aux;
+
+	if (ca->ca_offset != -1)
+		printf(" offset 0x%x", ca->ca_offset);
+	if (ca->ca_ipl > 0)
+		printf(" ipl %d", ca->ca_ipl);
+	return (UNCONF);
+}
+
+int
+ofobioscan(struct device *parent, void *self, void *aux)
+{
+	struct cfdata *cf = self;
+#if 0
+	struct ofobiosoftc *sc = (struct ofobiosoftc *)parent;
+#endif
+	struct confargs *ca = aux;
+	struct confargs oca;
+
+	bzero(&oca, sizeof oca);
+	oca.ca_iot = ca->ca_iot;
+	oca.ca_dmat = ca->ca_dmat;
+	oca.ca_offset = cf->cf_loc[0];
+	oca.ca_ipl = cf->cf_loc[1];
+	if (oca.ca_offset != -1) {
+		oca.ca_paddr = ca->ca_paddr + oca.ca_offset;
+		oca.ca_vaddr = IIOV(oca.ca_paddr);
+	} else {
+		oca.ca_vaddr = (vaddr_t)-1;
+		oca.ca_paddr = (paddr_t)-1;
+	}
+	oca.ca_bustype = BUS_OFOBIO;
+	oca.ca_name = cf->cf_driver->cd_name;
+
+	if ((*cf->cf_attach->ca_match)(parent, cf, &oca) == 0)
+		return (0);
+
+	config_attach(parent, cf, &oca, ofobioprint);
+
+	return (1);
+}
+
+int
+ofobioabort(void *frame)
+{
+	/*
+	 * Latch the condition; this will debounce the interrupt,
+	 * acknowledge it, and both the CSRD_ABORT and CRSD_ABORT_LATCH
+	 * bits will clear.
+	 */
+	sys_ofobio->csr_d |= OFO_CSRD_ABORT_LATCH;
+
+	nmihand(frame);
+
+	return (1);
+}
+
+void
+ofobio_clocksetup()
+{
+	volatile uint8_t *dartregs =
+	    (volatile uint8_t *)IIOV(MVME141_DART_BASE);
+	uint limit;
+	uint8_t dummy;
+
+	/*
+	 * Note that the dart(4) driver already may have programmed the
+	 * OPCR register during attachment.
+	 * It is very unfortunate that we have to override this. However
+	 * since dart(4) never needs to change the setting of this register,
+	 * ve'll simply keep the serial-related bits and add our own.
+	 */
+
+	/* disable timer output during programming */
+	dartregs[DART_OPCR] = OPSET;
+
+	/*
+	 * The DUART runs at 3.6864 MHz; by using the second waveform
+	 * generator we'll get a CLK/32 master rate.
+	 */
+	limit = (3686400 / 32) / hz;
+
+	dartregs[DART_CTUR] = limit >> 8;
+	dartregs[DART_CTLR] = limit & 0xff;
+	dartregs[DART_ACR] = BDSET2 | CCLK1 | IPDCDB | IPDCDA;
+	dartregs[DART_OPCR] = OPSETTO;
+	/* start counter */
+	dummy = dartregs[DART_CTSTART];
+
+	/* enable timer interrupts */
+	sys_ofobio->csr_b &= ~OFO_CSRB_TIMER_INTDIS;
+}
diff --git a/sys/arch/mvme68k/dev/ofobioreg.h b/sys/arch/mvme68k/dev/ofobioreg.h
new file mode 100644
index 00000000000..4da18cae65f
--- /dev/null
+++ b/sys/arch/mvme68k/dev/ofobioreg.h
@@ -0,0 +1,88 @@
+/*	$OpenBSD: ofobioreg.h,v 1.1 2009/03/01 22:08:13 miod Exp $	*/
+
+/*
+ * Copyright (c) 2009 Miodrag Vallat.
+ *
+ * Permission to use, copy, modify, and distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+/*
+ * MVME141 On-board resources (One-Four-One OBIO)
+ */
+
+/*
+ * Register layout.
+ */
+struct ofobioreg {
+	volatile uint8_t	reg00;	/* 0x32: cpu speed in MHz? */
+	volatile uint8_t	reg01;	/* 0x18 */
+	volatile uint8_t	reg02;	/* 0xfc */
+	volatile uint8_t	reg03;	/* 0xfc */
+	volatile uint8_t	reg04;	/* 0xa8 */
+	volatile uint8_t	reg05;	/* 0x40 */
+	volatile uint8_t	reg06;	/* 0x82 */
+	volatile uint8_t	reg07;	/* 0x82 */
+	volatile uint8_t	csr_a;
+	volatile uint8_t	csr_b;
+	volatile uint8_t	reg0a;	/* copy of csr_a */
+	volatile uint8_t	reg0b;	/* copy of csr_b */
+	volatile uint8_t	csr_c;
+	volatile uint8_t	csr_d;
+	volatile uint8_t	reg0e;
+	volatile uint8_t	reg0f;
+	volatile uint8_t	reg10;
+	volatile uint8_t	reg11;	/* 0x45 */
+	volatile uint8_t	reg12;
+	volatile uint8_t	reg13;
+	volatile uint8_t	reg14;
+	volatile uint8_t	reg15;
+	volatile uint8_t	reg16;
+	volatile uint8_t	reg17;
+	volatile uint8_t	reg18;
+	volatile uint8_t	reg19;
+	volatile uint8_t	reg1a;
+	volatile uint8_t	reg1b;
+	volatile uint8_t	reg1c;
+	volatile uint8_t	reg1d;
+	volatile uint8_t	reg1e;
+	volatile uint8_t	reg1f;
+};
+
+/* CSR A */
+#define	OFO_CSRA_CACHE_MONITOR	0xe0	/* cache monitor control mask */
+#define	OFO_CSRA_CACHE_CLEAR	0x10	/* clear board cache */
+#define	OFO_CSRA_CACHE_WDIS	0x08	/* cache write disable */
+#define	OFO_CSRA_CACHE_RDIS	0x04	/* cache read disable */
+
+/* CSR B */
+#define	OFO_CSRB_GLOBAL_INTDIS	0x80	/* global interrupt disable */
+#define	OFO_CSRB_VSB_INTDIS	0x40	/* VSB interrupt disable */
+#define	OFO_CSRB_TIMER_INTDIS	0x20	/* OP3 timer interrupt disable */
+#define	OFO_CSRB_DISABLE_A24	0x08	/* disable A24 mode */
+
+/* CSR C */
+#define	OFO_CSRC_TIMER_ACK	0x80	/* OP3 timer acknowledge */
+
+/* CSR D */
+#define	OFO_CSRD_ABORT		0x40	/* abort switch pressed */
+#define	OFO_CSRD_ABORT_LATCH	0x04	/* abort switch condition, latched */
+
+extern struct ofobioreg *sys_ofobio;
+
+#define	OFOBIO_CSR_ADDR	0xfff60000
+
+#define	OFOBIOVEC_CLOCK	0x1e
+#define	OFOBIOVEC_ABORT	0x42
+#define	OFOBIOVEC_DART	0x44
+
+void	ofobio_clocksetup(void);
diff --git a/sys/arch/mvme68k/dev/vme.c b/sys/arch/mvme68k/dev/vme.c
index 0274b47bf9a..92c6a3f175e 100644
--- a/sys/arch/mvme68k/dev/vme.c
+++ b/sys/arch/mvme68k/dev/vme.c
@@ -1,4 +1,4 @@
-/*	$OpenBSD: vme.c,v 1.26 2009/03/01 21:40:49 miod Exp $ */
+/*	$OpenBSD: vme.c,v 1.27 2009/03/01 22:08:13 miod Exp $ */
 
 /*
  * Copyright (c) 1995 Theo de Raadt
@@ -44,6 +44,7 @@
 
 #include "lrc.h"
 #include "mc.h"
+#include "ofobio.h"
 #include "pcc.h"
 #include "pcctwo.h"
 
@@ -236,8 +237,9 @@ vmepmap(sc, vmeaddr, len, bustype)
 
 	len = roundup(len, NBPG);
 	switch (vmebustype) {
-#if NLRC > 0 || NPCC > 0
+#if NLRC > 0 || NOFOBIO > 0 || NPCC > 0
 	case BUS_LRC:
+	case BUS_OFOBIO:
 	case BUS_PCC:
 		switch (bustype) {
 		case BUS_VMES:
@@ -435,7 +437,7 @@ vmeattach(parent, self, args)
 {
 	struct vmesoftc *sc = (struct vmesoftc *)self;
 	struct confargs *ca = args;
-#if NLRC > 0 || NPCC > 0
+#if NLRC > 0 || NOFOBIO > 0 || NPCC > 0
 	struct vme1reg *vme1;
 #endif
 #if NMC > 0 || NPCCTWO > 0
@@ -446,8 +448,9 @@ vmeattach(parent, self, args)
 
 	vmebustype = ca->ca_bustype;
 	switch (ca->ca_bustype) {
-#if NLRC > 0 || NPCC > 0
+#if NLRC > 0 || NOFOBIO > 0 || NPCC > 0
 	case BUS_LRC:
+	case BUS_OFOBIO:
 	case BUS_PCC:
 		vme1 = (struct vme1reg *)sc->sc_vaddr;
 		if (vme1->vme1_scon & VME1_SCON_SWITCH)
@@ -491,7 +494,7 @@ vmeintr_establish(vec, ih, name)
 	const char *name;
 {
 	struct vmesoftc *sc = (struct vmesoftc *) vme_cd.cd_devs[0];
-#if NLRC > 0 || NPCC > 0
+#if NLRC > 0 || NOFOBIO > 0 || NPCC > 0
 	struct vme1reg *vme1;
 #endif
 #if NMC > 0 || NPCCTWO > 0
@@ -502,8 +505,9 @@ vmeintr_establish(vec, ih, name)
 	x = intr_establish(vec, ih, name);
 
 	switch (vmebustype) {
-#if NLRC > 0 || NPCC > 0
+#if NLRC > 0 || NOFOBIO > 0 || NPCC > 0
 	case BUS_LRC:
+	case BUS_OFOBIO:
 	case BUS_PCC:
 		vme1 = (struct vme1reg *)sc->sc_vaddr;
 		vme1->vme1_irqen = vme1->vme1_irqen |
@@ -522,7 +526,7 @@ vmeintr_establish(vec, ih, name)
 	return (x);
 }
 
-#if defined(MVME147) || defined(MVME165)
+#if defined(MVME141) || defined(MVME147) || defined(MVME165)
 void
 vme1chip_init(sc)
 	struct vmesoftc *sc;