diff options
| author | Miod Vallat <miod@cvs.openbsd.org> | 2007-05-19 17:03:50 +0000 |
|---|---|---|
| committer | Miod Vallat <miod@cvs.openbsd.org> | 2007-05-19 17:03:50 +0000 |
| commit | 7c88c4fd9575a3eeb25a91df0d756bce2ff1f25b (patch) | |
| tree | 7a700be0ab095fc4c06ee76b86ba7f3844bc675f /sys/arch/mvme88k/include | |
| parent | febaa4d37ef3c1d1d10c265af334c7d26b0b8bd1 (diff) | |
Try reducing the number of IPIs, by only reinflicting them to us if we are
lowering the spl.
Also, warn and halt in tracks if the interrupt pin of a secondary cpu never
clears (found the hard way in one of the 2P256 modules here), since there is
nothing better we can do.
Last, do not attempt to handle VME interrupts on secondary processors yes
(this confuses the bus, since both processors will perform a VME interrupt
acknowledge sequence, but only one will succeed).
This lets processes correctly run on all the available processors in
single-user mode, but there are still issues to sort out.
Diffstat (limited to 'sys/arch/mvme88k/include')
| -rw-r--r-- | sys/arch/mvme88k/include/mvme188.h | 10 |
1 files changed, 6 insertions, 4 deletions
diff --git a/sys/arch/mvme88k/include/mvme188.h b/sys/arch/mvme88k/include/mvme188.h index aa13449cf5f..a46a345fbfb 100644 --- a/sys/arch/mvme88k/include/mvme188.h +++ b/sys/arch/mvme88k/include/mvme188.h @@ -1,4 +1,4 @@ -/* $OpenBSD: mvme188.h,v 1.29 2007/05/14 17:00:40 miod Exp $ */ +/* $OpenBSD: mvme188.h,v 1.30 2007/05/19 17:03:47 miod Exp $ */ /* * Copyright (c) 1999 Steve Murphree, Jr. * All rights reserved. @@ -58,11 +58,13 @@ */ /* per-processor interrupt enable registers */ +#define MVME188_IENBASE 0xfff84000 #define MVME188_IEN0 0xfff84004 /* interrupt enable CPU 0 */ #define MVME188_IEN1 0xfff84008 /* interrupt enable CPU 1 */ #define MVME188_IEN2 0xfff84010 /* interrupt enable CPU 2 */ #define MVME188_IEN3 0xfff84020 /* interrupt enable CPU 3 */ #define MVME188_IENALL 0xfff8403c /* simultaneous write */ +#define MVME188_IEN(cpu) (MVME188_IENBASE + (4 << (cpu))) #define MVME188_IST 0xfff84040 /* interrupt status register */ @@ -161,7 +163,7 @@ /* groups by interrupt levels */ -#define LVL7 (IRQ_ABORT | IRQ_ACF | IRQ_VME7 | IRQ_SF) +#define LVL7 (IRQ_ABORT | IRQ_ACF /* | IRQ_VME7 */ | IRQ_SF) #define LVL6 (IRQ_VME6) #define LVL5 (IRQ_VME5 | IRQ_DTI | IRQ_CIOI) #define LVL4 (IRQ_VME4) @@ -171,7 +173,7 @@ #define LVL0 (0x0) /* interrupts we want to process on the master CPU only */ -#define SLAVE_MASK (HW_FAILURE_MASK | OBIO_INTERRUPT_MASK) +#define SLAVE_MASK (HW_FAILURE_MASK | OBIO_INTERRUPT_MASK | VME_INTERRUPT_MASK) #define MASK_LVL_0 (LVL7 | LVL6 | LVL5 | LVL4 | LVL3 | LVL2 | LVL1) #define MASK_LVL_1 (LVL7 | LVL6 | LVL5 | LVL4 | LVL3 | LVL2) @@ -184,7 +186,7 @@ #define INT_LEVEL 8 /* # of interrupt level + 1 */ #define ISR_GET_CURRENT_MASK(cpu) \ - (*(volatile u_int *)MVME188_IST & *int_mask_reg[cpu]) + (*(volatile u_int *)MVME188_IST & int_mask_reg[cpu]) /* * Software interrupts 0 to 3 are used to deliver IPIs to cpu0-3. |