Split the cmmu code routines into single 88110 (MVME197LE) and 88110+88410

combos (MVME197SP/DP), and implement supposedly smarter cache routines.

There is still room for improvement, however, cache flush operation errata
permissing.

Tested on 197LE and 197DP.

1 files changed, 42 insertions, 86 deletions

diff --git a/sys/arch/mvme88k/include/m88110.h b/sys/arch/mvme88k/include/m88110.h
index b727a6447d4..7b7b9f3f452 100644
--- a/sys/arch/mvme88k/include/m88110.h
+++ b/sys/arch/mvme88k/include/m88110.h
@@ -1,4 +1,4 @@
-/*	$OpenBSD: m88110.h,v 1.20 2007/11/22 23:31:55 miod Exp $ */
+/*	$OpenBSD: m88110.h,v 1.21 2007/11/22 23:33:41 miod Exp $ */
 
 #ifndef	__MACHINE_M88110_H__
 #define	__MACHINE_M88110_H__
@@ -6,31 +6,6 @@
 /*
  *	88110 CMMU definitions
  */
-#define CMMU_ICMD 0
-#define CMMU_ICTL 1
-#define CMMU_ISAR 2
-#define CMMU_ISAP 3
-#define CMMU_IUAP 4
-#define CMMU_IIR  5
-#define CMMU_IBP  6
-#define CMMU_IPPU 7
-#define CMMU_IPPL 8
-#define CMMU_ISR  9
-#define CMMU_ILAR 10
-#define CMMU_IPAR 11
-
-#define CMMU_DCMD 12
-#define CMMU_DCTL 13
-#define CMMU_DSAR 14
-#define CMMU_DSAP 15
-#define CMMU_DUAP 16
-#define CMMU_DIR  17
-#define CMMU_DBP  18
-#define CMMU_DPPU 19
-#define CMMU_DPPL 20
-#define CMMU_DSR  21
-#define CMMU_DLAR 22
-#define CMMU_DPAR 23
 
 #define CMMU_ICMD_INV_ITIC       0x001    /* Invalidate Inst Cache & TIC */
 #define CMMU_ICMD_INV_TIC        0x002    /* Invalidate TIC */
@@ -105,11 +80,6 @@
 #define CMMU_DSR_WA              0x000002 /* Write-Allocate Bus Error */
 #define CMMU_DSR_BE              0x000001 /* Bus Error */
 
-#define CMMU_READ 0
-#define CMMU_WRITE 1
-#define CMMU_DATA 1
-#define CMMU_INST 0
-
 /* definitions for use of the BATC */
 #define BATC_512K	(0x00 << BATC_BLKSHIFT)
 #define BATC_1M		(0x01 << BATC_BLKSHIFT)
@@ -120,8 +90,11 @@
 #define BATC_32M	(0x3f << BATC_BLKSHIFT)
 #define BATC_64M	(0x7f << BATC_BLKSHIFT)
 
-#define CLINE_MASK	0x1f
-#define CLINE_SIZE	(8 * 32)
+/*
+ * Cache line information
+ */
+#define	MC88110_CACHE_SHIFT	5
+#define	MC88110_CACHE_LINE	(1 << MC88110_CACHE_SHIFT)
 
 #ifndef	_LOCORE
 
@@ -168,92 +141,75 @@ u_int get_dppu(void);
 u_int get_dppl(void);
 u_int get_dsr(void);
 
-/* Cache inlines */
-
-#define line_addr(x)	(paddr_t)((x) & ~CLINE_MASK)
-#define page_addr(x)	(paddr_t)((x) & ~PAGE_MASK)
-
 /*
- * 88110 general information #22:
- * ``Issuing a command to flush and invalidate the data cache while the
- *   dcache is disabled (CEN = 0 in dctl) will cause problems.  Do not
- *   flush a disabled data cache.  In general, there is no reason to
- *   perform this operation with the cache disabled, since it may be
- *   incoherent with the proper state of memory.  Before 5.0 the flush
- *   command was treated like a nop when the cache was disabled.  This
- *   is no longer the case.''
+ * The following inlines expect their address to be line-aligned for line
+ * operations, and page aligned for page operations.
  */
 
-static __inline__ void mc88110_flush_data_line(paddr_t x)
+/*
+static __inline__ void
+mc88110_flush_data_line(paddr_t x)
 {
-	u_int dctl = get_dctl();
-	if (dctl & CMMU_DCTL_CEN) {
-		set_dsar(line_addr(x));
-		set_dcmd(CMMU_DCMD_FLUSH_LINE);
-	}
+	set_dsar(x);
+	set_dcmd(CMMU_DCMD_FLUSH_LINE);
 }
 
-static __inline__ void mc88110_flush_data_page(paddr_t x)
+static __inline__ void
+mc88110_flush_data_page(paddr_t x)
 {
-	u_int dctl = get_dctl();
-	if (dctl & CMMU_DCTL_CEN) {
-		set_dsar(page_addr(x));
-		set_dcmd(CMMU_DCMD_FLUSH_PG);
-	}
+	set_dsar(x);
+	set_dcmd(CMMU_DCMD_FLUSH_PG);
 }
+*/
 
-static __inline__ void mc88110_flush_data(void)
+static __inline__ void
+mc88110_flush_data(void)
 {
-	u_int dctl = get_dctl();
-	if (dctl & CMMU_DCTL_CEN) {
-		set_dcmd(CMMU_DCMD_FLUSH_ALL);
-	}
+	set_dcmd(CMMU_DCMD_FLUSH_ALL);
 }
 
-static __inline__ void mc88110_inval_data_line(paddr_t x)
+static __inline__ void
+mc88110_inval_data_line(paddr_t x)
 {
-	set_dsar(line_addr(x));
+	set_dsar(x);
 	set_dcmd(CMMU_DCMD_INV_LINE);
 }
 
-static __inline__ void mc88110_inval_data(void)
+static __inline__ void
+mc88110_inval_data(void)
 {
 	set_dcmd(CMMU_DCMD_INV_ALL);
 }
 
-static __inline__ void mc88110_sync_data_line(paddr_t x)
+static __inline__ void
+mc88110_sync_data_line(paddr_t x)
 {
-	u_int dctl = get_dctl();
-	if (dctl & CMMU_DCTL_CEN) {
-		set_dsar(line_addr(x));
-		set_dcmd(CMMU_DCMD_FLUSH_LINE_INV);
-	}
+	set_dsar(x);
+	set_dcmd(CMMU_DCMD_FLUSH_LINE_INV);
 }
 
-static __inline__ void mc88110_sync_data_page(paddr_t x)
+static __inline__ void
+mc88110_sync_data_page(paddr_t x)
 {
-	u_int dctl = get_dctl();
-	if (dctl & CMMU_DCTL_CEN) {
-		set_dsar(page_addr(x));
-		set_dcmd(CMMU_DCMD_FLUSH_PG_INV);
-	}
+	set_dsar(x);
+	set_dcmd(CMMU_DCMD_FLUSH_PG_INV);
 }
 
-static __inline__ void mc88110_sync_data(void)
+static __inline__ void
+mc88110_sync_data(void)
 {
-	u_int dctl = get_dctl();
-	if (dctl & CMMU_DCTL_CEN) {
-		set_dcmd(CMMU_DCMD_FLUSH_ALL_INV);
-	}
+	set_dcmd(CMMU_DCMD_FLUSH_ALL_INV);
 }
 
-static __inline__ void mc88110_inval_inst_line(paddr_t x)
+static __inline__ void
+mc88110_inval_inst_line(paddr_t x)
 {
-	set_isar(line_addr(x));
+	set_isar(x);
 	set_icmd(CMMU_ICMD_INV_LINE);
 }
 
-static __inline__ void mc88110_inval_inst(void)
+static __inline__ void
+mc88110_inval_inst(void)
 {
 	set_icmd(CMMU_ICMD_INV_ITIC);
 }