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author	Steve Murphree <smurph@cvs.openbsd.org>	2001-12-22 17:57:12 +0000
committer	Steve Murphree <smurph@cvs.openbsd.org>	2001-12-22 17:57:12 +0000
commit	48748b359aa1579870715d7a1d9148166956853a (patch)
tree	b93e81f626ab95e384807e8b752c8f16aaa873c4 /sys/arch/mvme88k
parent	bab32196144d0fbc20ee2e2b705c702514b7f673 (diff)

change function names to reflect cpu type instead of board type.

Diffstat (limited to 'sys/arch/mvme88k')

-rw-r--r--

sys/arch/mvme88k/include/exception_vectors2.h

276

-rw-r--r--

sys/arch/mvme88k/include/locore.h

-rw-r--r--

sys/arch/mvme88k/include/trap.h

-rw-r--r--

sys/arch/mvme88k/mvme88k/eh.S

2677

-rw-r--r--

sys/arch/mvme88k/mvme88k/locore_c_routines.c

-rw-r--r--

sys/arch/mvme88k/mvme88k/m88100_fp.S

-rw-r--r--

sys/arch/mvme88k/mvme88k/m88110_fp.S

-rw-r--r--

sys/arch/mvme88k/mvme88k/machdep.c

-rw-r--r--

sys/arch/mvme88k/mvme88k/trap.c

9 files changed, 1578 insertions, 1513 deletions

diff --git a/sys/arch/mvme88k/include/exception_vectors2.h b/sys/arch/mvme88k/include/exception_vectors2.h
index 1e5ee0b11db..87e31088d70 100644
--- a/sys/arch/mvme88k/include/exception_vectors2.h
+++ b/sys/arch/mvme88k/include/exception_vectors2.h

@@ -1,4 +1,4 @@

-/* $OpenBSD: exception_vectors2.h,v 1.5 2001/12/16 23:49:46 miod Exp $ */

+/* $OpenBSD: exception_vectors2.h,v 1.6 2001/12/22 17:57:11 smurph Exp $ */

* Mach Operating System

@@ -25,143 +25,145 @@

* any improvements or extensions that they make and grant Carnegie the

* rights to redistribute these changes.

-/*#define M197_UNDEFINED PREDEFINED_BY_ROM*/

+/*#define M88110_UNDEFINED PREDEFINED_BY_ROM*/

#ifndef __MACHINE_EXECPTION_VECTORS2_H__

#define __MACHINE_EXECPTION_VECTORS2_H__

-#ifndef M197_M197_UNDEFINED

-#define M197_UNDEFINED _m197_unknown_handler

+#ifndef M88110_UNDEFINED

+#define M88110_UNDEFINED _m88110_unknown_handler

#endif

-/* vector 0x00 (#0) */ word _m197_reset_handler

-/* vector 0x01 (#1) */ word _m197_interrupt_handler

-/* vector 0x02 (#2) */ word _m197_instruction_access_handler

-/* vector 0x03 (#3) */ word _m197_data_exception_handler

-/* vector 0x04 (#4) */ word _m197_misaligned_handler

-/* vector 0x05 (#5) */ word _m197_unimplemented_handler

-/* vector 0x06 (#6) */ word _m197_privilege_handler

-/* vector 0x07 (#7) */ word _m197_bounds_handler

-/* vector 0x08 (#8) */ word _m197_divide_handler

-/* vector 0x09 (#9) */ word _m197_overflow_handler

-/* vector 0x0a (#10) */ word _m197_error_handler

-/* vector 0x0b (#11) */ word _m197_nonmaskable

-/* vector 0x0c (#12) */ word _m197_data_read_miss

-/* vector 0x0d (#13) */ word _m197_data_write_miss

-/* vector 0x0e (#14) */ word _m197_inst_atc_miss

-/* vector 0x0f (#15) */ word _m197_trace

-/* vector 0x10 (#16) */ word M197_UNDEFINED

-/* vector 0x11 (#17) */ word M197_UNDEFINED

-/* vector 0x12 (#18) */ word M197_UNDEFINED

-/* vector 0x13 (#19) */ word M197_UNDEFINED

-/* vector 0x14 (#20) */ word M197_UNDEFINED

-/* vector 0x15 (#21) */ word M197_UNDEFINED

-/* vector 0x16 (#22) */ word M197_UNDEFINED

-/* vector 0x17 (#23) */ word M197_UNDEFINED

-/* vector 0x18 (#24) */ word M197_UNDEFINED

-/* vector 0x19 (#25) */ word M197_UNDEFINED

-/* vector 0x1a (#26) */ word M197_UNDEFINED

-/* vector 0x1b (#27) */ word M197_UNDEFINED

-/* vector 0x1c (#28) */ word M197_UNDEFINED

-/* vector 0x1d (#29) */ word M197_UNDEFINED

-/* vector 0x1e (#30) */ word M197_UNDEFINED

-/* vector 0x1f (#31) */ word M197_UNDEFINED

-/* vector 0x20 (#32) */ word M197_UNDEFINED

-/* vector 0x21 (#33) */ word M197_UNDEFINED

-/* vector 0x22 (#34) */ word M197_UNDEFINED

-/* vector 0x23 (#35) */ word M197_UNDEFINED

-/* vector 0x24 (#36) */ word M197_UNDEFINED

-/* vector 0x25 (#37) */ word M197_UNDEFINED

-/* vector 0x26 (#38) */ word M197_UNDEFINED

-/* vector 0x27 (#39) */ word M197_UNDEFINED

-/* vector 0x28 (#40) */ word M197_UNDEFINED

-/* vector 0x29 (#41) */ word M197_UNDEFINED

-/* vector 0x2a (#42) */ word M197_UNDEFINED

-/* vector 0x2b (#43) */ word M197_UNDEFINED

-/* vector 0x2c (#44) */ word M197_UNDEFINED

-/* vector 0x2d (#45) */ word M197_UNDEFINED

-/* vector 0x2e (#46) */ word M197_UNDEFINED

-/* vector 0x2f (#47) */ word M197_UNDEFINED

-/* vector 0x30 (#48) */ word M197_UNDEFINED

-/* vector 0x31 (#49) */ word M197_UNDEFINED

-/* vector 0x32 (#50) */ word M197_UNDEFINED

-/* vector 0x33 (#51) */ word M197_UNDEFINED

-/* vector 0x34 (#52) */ word M197_UNDEFINED

-/* vector 0x35 (#53) */ word M197_UNDEFINED

-/* vector 0x36 (#54) */ word M197_UNDEFINED

-/* vector 0x37 (#55) */ word M197_UNDEFINED

-/* vector 0x38 (#56) */ word M197_UNDEFINED

-/* vector 0x39 (#57) */ word M197_UNDEFINED

-/* vector 0x3a (#58) */ word M197_UNDEFINED

-/* vector 0x3b (#59) */ word M197_UNDEFINED

-/* vector 0x3c (#60) */ word M197_UNDEFINED

-/* vector 0x3d (#61) */ word M197_UNDEFINED

-/* vector 0x3e (#62) */ word M197_UNDEFINED

-/* vector 0x3f (#63) */ word M197_UNDEFINED

-/* vector 0x40 (#64) */ word M197_UNDEFINED

-/* vector 0x41 (#65) */ word M197_UNDEFINED

-/* vector 0x42 (#66) */ word M197_UNDEFINED

-/* vector 0x43 (#67) */ word M197_UNDEFINED

-/* vector 0x44 (#68) */ word M197_UNDEFINED

-/* vector 0x45 (#69) */ word M197_UNDEFINED

-/* vector 0x46 (#70) */ word M197_UNDEFINED

-/* vector 0x47 (#71) */ word M197_UNDEFINED

-/* vector 0x48 (#72) */ word M197_UNDEFINED

-/* vector 0x49 (#73) */ word M197_UNDEFINED

-/* vector 0x4a (#74) */ word M197_UNDEFINED

-/* vector 0x4b (#75) */ word M197_UNDEFINED

-/* vector 0x4c (#76) */ word M197_UNDEFINED

-/* vector 0x4d (#77) */ word M197_UNDEFINED

-/* vector 0x4e (#78) */ word M197_UNDEFINED

-/* vector 0x4f (#79) */ word M197_UNDEFINED

-/* vector 0x50 (#80) */ word M197_UNDEFINED

-/* vector 0x51 (#81) */ word M197_UNDEFINED

-/* vector 0x52 (#82) */ word M197_UNDEFINED

-/* vector 0x53 (#83) */ word M197_UNDEFINED

-/* vector 0x54 (#84) */ word M197_UNDEFINED

-/* vector 0x55 (#85) */ word M197_UNDEFINED

-/* vector 0x56 (#86) */ word M197_UNDEFINED

-/* vector 0x57 (#87) */ word M197_UNDEFINED

-/* vector 0x58 (#88) */ word M197_UNDEFINED

-/* vector 0x59 (#89) */ word M197_UNDEFINED

-/* vector 0x5a (#90) */ word M197_UNDEFINED

-/* vector 0x5b (#91) */ word M197_UNDEFINED

-/* vector 0x5c (#92) */ word M197_UNDEFINED

-/* vector 0x5d (#93) */ word M197_UNDEFINED

-/* vector 0x5e (#94) */ word M197_UNDEFINED

-/* vector 0x5f (#95) */ word M197_UNDEFINED

-/* vector 0x60 (#96) */ word M197_UNDEFINED

-/* vector 0x61 (#97) */ word M197_UNDEFINED

-/* vector 0x62 (#98) */ word M197_UNDEFINED

-/* vector 0x63 (#99) */ word M197_UNDEFINED

-/* vector 0x64 (#100) */ word M197_UNDEFINED

-/* vector 0x65 (#101) */ word M197_UNDEFINED

-/* vector 0x66 (#102) */ word M197_UNDEFINED

-/* vector 0x67 (#103) */ word M197_UNDEFINED

-/* vector 0x68 (#104) */ word M197_UNDEFINED

-/* vector 0x69 (#105) */ word M197_UNDEFINED

-/* vector 0x6a (#106) */ word M197_UNDEFINED

-/* vector 0x6b (#107) */ word M197_UNDEFINED

-/* vector 0x6c (#108) */ word M197_UNDEFINED

-/* vector 0x6d (#109) */ word M197_UNDEFINED

-/* vector 0x6e (#110) */ word M197_UNDEFINED

-/* vector 0x6f (#111) */ word M197_UNDEFINED

-/* vector 0x70 (#112) */ word M197_UNDEFINED

-/* vector 0x71 (#113) */ word M197_UNDEFINED

-/* vector 0x72 (#114) */ word _m197_fp_precise_handler

-/* vector 0x73 (#115) */ word M197_UNDEFINED

-/* vector 0x74 (#116) */ word _m197_unimplemented_handler

-/* vector 0x75 (#117) */ word M197_UNDEFINED

-/* vector 0x76 (#118) */ word _m197_unimplemented_handler

-/* vector 0x77 (#119) */ word M197_UNDEFINED

-/* vector 0x78 (#120) */ word _m197_unimplemented_handler

-/* vector 0x79 (#121) */ word M197_UNDEFINED

-/* vector 0x7a (#122) */ word _m197_unimplemented_handler

-/* vector 0x7b (#123) */ word M197_UNDEFINED

-/* vector 0x7c (#124) */ word _m197_unimplemented_handler

-/* vector 0x7d (#125) */ word M197_UNDEFINED

-/* vector 0x7e (#126) */ word _m197_unimplemented_handler

-/* vector 0x7f (#127) */ word M197_UNDEFINED

-/* vector 0x80 (#128) */ word _m197_syscall_handler

-/* vector 0x81 (#129) */ word _m197_syscall_handler

-/* vector 0x82 (#130) */ word _m197_break

-/* vector 0x83 (#131) */ word _m197_trace

-/* vector 0x84 (#132) */ word _m197_entry

+/* vector 0x00 (#0) */ word _m88110_reset_handler

+/* vector 0x01 (#1) */ word _m88110_interrupt_handler

+/* vector 0x02 (#2) */ word _m88110_instruction_access_handler

+/* vector 0x03 (#3) */ word _m88110_data_exception_handler

+/* vector 0x04 (#4) */ word _m88110_misaligned_handler

+/* vector 0x05 (#5) */ word _m88110_unimplemented_handler

+/* vector 0x06 (#6) */ word _m88110_privilege_handler

+/* vector 0x07 (#7) */ word _m88110_bounds_handler

+/* vector 0x08 (#8) */ word _m88110_divide_handler

+/* vector 0x09 (#9) */ word _m88110_overflow_handler

+/* vector 0x0a (#10) */ word _m88110_error_handler

+/* vector 0x0b (#11) */ word _m88110_nonmaskable

+/* vector 0x0c (#12) */ word _m88110_data_read_miss

+/* vector 0x0d (#13) */ word _m88110_data_write_miss

+/* vector 0x0e (#14) */ word _m88110_inst_atc_miss

+/* vector 0x0f (#15) */ word _m88110_trace

+/* vector 0x10 (#16) */ word M88110_UNDEFINED

+/* vector 0x11 (#17) */ word M88110_UNDEFINED

+/* vector 0x12 (#18) */ word M88110_UNDEFINED

+/* vector 0x13 (#19) */ word M88110_UNDEFINED

+/* vector 0x14 (#20) */ word M88110_UNDEFINED

+/* vector 0x15 (#21) */ word M88110_UNDEFINED

+/* vector 0x16 (#22) */ word M88110_UNDEFINED

+/* vector 0x17 (#23) */ word M88110_UNDEFINED

+/* vector 0x18 (#24) */ word M88110_UNDEFINED

+/* vector 0x19 (#25) */ word M88110_UNDEFINED

+/* vector 0x1a (#26) */ word M88110_UNDEFINED

+/* vector 0x1b (#27) */ word M88110_UNDEFINED

+/* vector 0x1c (#28) */ word M88110_UNDEFINED

+/* vector 0x1d (#29) */ word M88110_UNDEFINED

+/* vector 0x1e (#30) */ word M88110_UNDEFINED

+/* vector 0x1f (#31) */ word M88110_UNDEFINED

+/* vector 0x20 (#32) */ word M88110_UNDEFINED

+/* vector 0x21 (#33) */ word M88110_UNDEFINED

+/* vector 0x22 (#34) */ word M88110_UNDEFINED

+/* vector 0x23 (#35) */ word M88110_UNDEFINED

+/* vector 0x24 (#36) */ word M88110_UNDEFINED

+/* vector 0x25 (#37) */ word M88110_UNDEFINED

+/* vector 0x26 (#38) */ word M88110_UNDEFINED

+/* vector 0x27 (#39) */ word M88110_UNDEFINED

+/* vector 0x28 (#40) */ word M88110_UNDEFINED

+/* vector 0x29 (#41) */ word M88110_UNDEFINED

+/* vector 0x2a (#42) */ word M88110_UNDEFINED

+/* vector 0x2b (#43) */ word M88110_UNDEFINED

+/* vector 0x2c (#44) */ word M88110_UNDEFINED

+/* vector 0x2d (#45) */ word M88110_UNDEFINED

+/* vector 0x2e (#46) */ word M88110_UNDEFINED

+/* vector 0x2f (#47) */ word M88110_UNDEFINED

+/* vector 0x30 (#48) */ word M88110_UNDEFINED

+/* vector 0x31 (#49) */ word M88110_UNDEFINED

+/* vector 0x32 (#50) */ word M88110_UNDEFINED

+/* vector 0x33 (#51) */ word M88110_UNDEFINED

+/* vector 0x34 (#52) */ word M88110_UNDEFINED

+/* vector 0x35 (#53) */ word M88110_UNDEFINED

+/* vector 0x36 (#54) */ word M88110_UNDEFINED

+/* vector 0x37 (#55) */ word M88110_UNDEFINED

+/* vector 0x38 (#56) */ word M88110_UNDEFINED

+/* vector 0x39 (#57) */ word M88110_UNDEFINED

+/* vector 0x3a (#58) */ word M88110_UNDEFINED

+/* vector 0x3b (#59) */ word M88110_UNDEFINED

+/* vector 0x3c (#60) */ word M88110_UNDEFINED

+/* vector 0x3d (#61) */ word M88110_UNDEFINED

+/* vector 0x3e (#62) */ word M88110_UNDEFINED

+/* vector 0x3f (#63) */ word M88110_UNDEFINED

+/* vector 0x40 (#64) */ word M88110_UNDEFINED

+/* vector 0x41 (#65) */ word M88110_UNDEFINED

+/* vector 0x42 (#66) */ word M88110_UNDEFINED

+/* vector 0x43 (#67) */ word M88110_UNDEFINED

+/* vector 0x44 (#68) */ word M88110_UNDEFINED

+/* vector 0x45 (#69) */ word M88110_UNDEFINED

+/* vector 0x46 (#70) */ word M88110_UNDEFINED

+/* vector 0x47 (#71) */ word M88110_UNDEFINED

+/* vector 0x48 (#72) */ word M88110_UNDEFINED

+/* vector 0x49 (#73) */ word M88110_UNDEFINED

+/* vector 0x4a (#74) */ word M88110_UNDEFINED

+/* vector 0x4b (#75) */ word M88110_UNDEFINED

+/* vector 0x4c (#76) */ word M88110_UNDEFINED

+/* vector 0x4d (#77) */ word M88110_UNDEFINED

+/* vector 0x4e (#78) */ word M88110_UNDEFINED

+/* vector 0x4f (#79) */ word M88110_UNDEFINED

+/* vector 0x50 (#80) */ word M88110_UNDEFINED

+/* vector 0x51 (#81) */ word M88110_UNDEFINED

+/* vector 0x52 (#82) */ word M88110_UNDEFINED

+/* vector 0x53 (#83) */ word M88110_UNDEFINED

+/* vector 0x54 (#84) */ word M88110_UNDEFINED

+/* vector 0x55 (#85) */ word M88110_UNDEFINED

+/* vector 0x56 (#86) */ word M88110_UNDEFINED

+/* vector 0x57 (#87) */ word M88110_UNDEFINED

+/* vector 0x58 (#88) */ word M88110_UNDEFINED

+/* vector 0x59 (#89) */ word M88110_UNDEFINED

+/* vector 0x5a (#90) */ word M88110_UNDEFINED

+/* vector 0x5b (#91) */ word M88110_UNDEFINED

+/* vector 0x5c (#92) */ word M88110_UNDEFINED

+/* vector 0x5d (#93) */ word M88110_UNDEFINED

+/* vector 0x5e (#94) */ word M88110_UNDEFINED

+/* vector 0x5f (#95) */ word M88110_UNDEFINED

+/* vector 0x60 (#96) */ word M88110_UNDEFINED

+/* vector 0x61 (#97) */ word M88110_UNDEFINED

+/* vector 0x62 (#98) */ word M88110_UNDEFINED

+/* vector 0x63 (#99) */ word M88110_UNDEFINED

+/* vector 0x64 (#100) */ word M88110_UNDEFINED

+/* vector 0x65 (#101) */ word M88110_UNDEFINED

+/* vector 0x66 (#102) */ word M88110_UNDEFINED

+/* vector 0x67 (#103) */ word M88110_UNDEFINED

+/* vector 0x68 (#104) */ word M88110_UNDEFINED

+/* vector 0x69 (#105) */ word M88110_UNDEFINED

+/* vector 0x6a (#106) */ word M88110_UNDEFINED

+/* vector 0x6b (#107) */ word M88110_UNDEFINED

+/* vector 0x6c (#108) */ word M88110_UNDEFINED

+/* vector 0x6d (#109) */ word M88110_UNDEFINED

+/* vector 0x6e (#110) */ word M88110_UNDEFINED

+/* vector 0x6f (#111) */ word M88110_UNDEFINED

+/* vector 0x70 (#112) */ word M88110_UNDEFINED

+/* vector 0x71 (#113) */ word M88110_UNDEFINED

+/* vector 0x72 (#114) */ word _m88110_fp_precise_handler

+/* vector 0x73 (#115) */ word M88110_UNDEFINED

+/* vector 0x74 (#116) */ word _m88110_unimplemented_handler

+/* vector 0x75 (#117) */ word M88110_UNDEFINED

+/* vector 0x76 (#118) */ word _m88110_unimplemented_handler

+/* vector 0x77 (#119) */ word M88110_UNDEFINED

+/* vector 0x78 (#120) */ word _m88110_unimplemented_handler

+/* vector 0x79 (#121) */ word M88110_UNDEFINED

+/* vector 0x7a (#122) */ word _m88110_unimplemented_handler

+/* vector 0x7b (#123) */ word M88110_UNDEFINED

+/* vector 0x7c (#124) */ word _m88110_unimplemented_handler

+/* vector 0x7d (#125) */ word M88110_UNDEFINED

+/* vector 0x7e (#126) */ word _m88110_unimplemented_handler

+/* vector 0x7f (#127) */ word M88110_UNDEFINED

+/* vector 0x80 (#128) */ word _m88110_syscall_handler

+/* vector 0x81 (#129) */ word _m88110_syscall_handler

+/* vector 0x82 (#130) */ word _m88110_break

+/* vector 0x83 (#131) */ word _m88110_trace

+/* vector 0x84 (#132) */ word _m88110_entry

#endif /* __MACHINE_EXECPTION_VECTORS2_H__ */

diff --git a/sys/arch/mvme88k/include/locore.h b/sys/arch/mvme88k/include/locore.h
index 317348f906e..644e9d14e8e 100644
--- a/sys/arch/mvme88k/include/locore.h
+++ b/sys/arch/mvme88k/include/locore.h

@@ -1,4 +1,4 @@

-/* $OpenBSD: locore.h,v 1.13 2001/12/16 23:49:46 miod Exp $ */

+/* $OpenBSD: locore.h,v 1.14 2001/12/22 17:57:11 smurph Exp $ */

#ifndef _MACHINE_LOCORE_H_

#define _MACHINE_LOCORE_H_

@@ -40,25 +40,16 @@ int db_are_interrupts_disabled __P((void));

void fubail __P((void));

void subail __P((void));

-#if defined(MVME187) || defined(MVME188)

int guarded_access __P((volatile unsigned char *address,

unsigned len, u_char *vec));

-#endif

/* locore_c_routines.c */

-#if defined(MVME187) || defined(MVME188)

+#ifdef M88100

void dae_print __P((unsigned *eframe));

void data_access_emulation __P((unsigned *eframe));

#endif

-#ifdef MVME188

-unsigned int safe_level __P((unsigned mask, unsigned curlevel));

-#if 0

-void block_obio_interrupt __P((unsigned mask));

-void unblock_obio_interrupt __P((unsigned mask));

-#endif

unsigned spl __P((void));

unsigned getipl __P((void));

#ifdef DDB

@@ -80,32 +71,35 @@ void dosoftint __P((void));

void MY_info __P((struct trapframe *f, caddr_t p, int flags, char *s));

void MY_info_done __P((struct trapframe *f, int flags));

void mvme_bootstrap __P((void));

+#ifdef MVME187

+void m187_ext_int __P((u_int v, struct m88100_saved_state *eframe));

+#endif

#ifdef MVME188

void m188_reset __P((void));

void m188_ext_int __P((u_int v, struct m88100_saved_state *eframe));

+unsigned int safe_level __P((unsigned mask, unsigned curlevel));

#endif

-#if defined(MVME187) || defined(MVME197)

-void sbc_ext_int __P((u_int v, struct m88100_saved_state *eframe));

+#ifdef MVME197

+void m197_ext_int __P((u_int v, struct m88100_saved_state *eframe));

#endif

/* eh.S */

struct proc;

void proc_do_uret __P((struct proc *));

-#if defined(MVME187) || defined(MVME188)

+#ifdef M88100

void sigsys __P((void));

void sigtrap __P((void));

void stepbpt __P((void));

void userbpt __P((void));

void syscall_handler __P((void));

#endif

-#if defined(MVME197)

-void m197_sigsys __P((void));

-void m197_sigtrap __P((void));

-void m197_stepbpt __P((void));

-void m197_userbpt __P((void));

-void m197_syscall_handler __P((void));

+#ifdef M88110

+void m88110_sigsys __P((void));

+void m88110_sigtrap __P((void));

+void m88110_stepbpt __P((void));

+void m88110_userbpt __P((void));

+void m88110_syscall_handler __P((void));

#endif

/* process.S */

diff --git a/sys/arch/mvme88k/include/trap.h b/sys/arch/mvme88k/include/trap.h
index 379760b4ae0..a03a119eaf3 100644
--- a/sys/arch/mvme88k/include/trap.h
+++ b/sys/arch/mvme88k/include/trap.h

@@ -1,4 +1,4 @@

-/* $OpenBSD: trap.h,v 1.14 2001/12/16 23:49:46 miod Exp $ */

+/* $OpenBSD: trap.h,v 1.15 2001/12/22 17:57:11 smurph Exp $ */

* Mach Operating System

@@ -73,29 +73,30 @@

#define T_USER 29 /* user mode fault */

#ifndef _LOCORE

-void panictrap(int type, struct m88100_saved_state *frame);

-void test_trap(struct m88100_saved_state *frame);

-void error_fault(struct m88100_saved_state *frame);

-void error_reset(struct m88100_saved_state *frame);

-unsigned ss_get_value(struct proc *p, unsigned addr, int size);

-int ss_put_value(struct proc *p, unsigned addr, unsigned value, int size);

-unsigned ss_branch_taken(unsigned inst, unsigned pc,

- unsigned (*func)(unsigned int, struct trapframe *),

- struct trapframe *func_data); /* 'opaque' */

-unsigned ss_getreg_val(unsigned regno, struct trapframe *tf);

-int ss_inst_branch(unsigned ins);

-int ss_inst_delayed(unsigned ins);

-unsigned ss_next_instr_address(struct proc *p, unsigned pc, unsigned delay_slot);

-int cpu_singlestep(register struct proc *p);

+void panictrap __P((int, struct m88100_saved_state *));

+void test_trap __P((struct m88100_saved_state *));

+void error_fault __P((struct m88100_saved_state *));

+void error_reset __P((struct m88100_saved_state *));

+unsigned ss_get_value __P((struct proc *, unsigned, int));

+int ss_put_value __P((struct proc *, unsigned, unsigned, int));

+unsigned ss_branch_taken __P((unsigned, unsigned,

+ unsigned (*func) __P((unsigned int, struct trapframe *)),

+ struct trapframe *)); /* 'opaque' */

+unsigned ss_getreg_val __P((unsigned, struct trapframe *));

+int ss_inst_branch __P((unsigned));

+int ss_inst_delayed __P((unsigned));

+unsigned ss_next_instr_address __P((struct proc *, unsigned, unsigned));

+int cpu_singlestep __P((register struct proc *));

-#if defined(MVME187) || defined(MVME188)

-void syscall(register_t code, struct m88100_saved_state *tf);

-void trap18x(unsigned type, struct m88100_saved_state *frame);

-#endif /* defined(MVME187) || defined(MVME188) */

-#ifdef MVME197

-void m197_syscall(register_t code, struct m88100_saved_state *tf);

-void trap197(unsigned type, struct m88100_saved_state *frame);

-#endif /* MVME197 */

+#ifdef M88100

+void m88100_trap __P((unsigned, struct m88100_saved_state *));

+void m88100_syscall __P((register_t, struct m88100_saved_state *));

+#endif /* M88100 */

+#ifdef M88110

+void m88110_trap __P((unsigned, struct m88100_saved_state *));

+void m88110_syscall __P((register_t, struct m88100_saved_state *));

+#endif /* M88110 */

#endif /* _LOCORE */

diff --git a/sys/arch/mvme88k/mvme88k/eh.S b/sys/arch/mvme88k/mvme88k/eh.S
index f04e61297d6..43b28988b76 100644
--- a/sys/arch/mvme88k/mvme88k/eh.S
+++ b/sys/arch/mvme88k/mvme88k/eh.S

@@ -1,4 +1,4 @@

-/* $OpenBSD: eh.S,v 1.25 2001/12/19 07:04:41 smurph Exp $ */

+/* $OpenBSD: eh.S,v 1.26 2001/12/22 17:57:10 smurph Exp $ */

* Mach Operating System

@@ -236,8 +236,7 @@

#define EF_SR3 (EF_R0 + 5)

#define EF_FLAGS EF_MODE

-#define INTSTACK 0 /* To make interupts use their own stack */

+#define INTSTACK 0 /* To make interupts use their own stack */

data

align 4

sbadcpupanic:

@@ -249,10 +248,77 @@ sbadcpupanic:

Lbadcpupanic:

or.u r2, r0, hi16(sbadcpupanic)

or r2, r2, lo16(sbadcpupanic)

- bsr _panic

+ bsr _C_LABEL(panic)

align 8

+#define OFF_VEC 0

+#define OFF_EPSR 4

+#define OFF_EXIP 8

+#define OFF_ENIP 12

+#define OFF_DSR 16

+#define OFF_DLAR 20

+#define OFF_DPAR 24

+#define OFF_ISR 28

+#define OFF_ILAR 32

+#define OFF_IPAR 36

+#define OFF_TMP 40

+#define SAVE_CTX ; \

+ stcr r31, SRX ; \

+ or.u r31, r0, hi16(_save_frame) ; \

+ or r31, r31, lo16(_save_frame) ; \

+ /* save old R31 and other R registers */; \

+ st.d r0 , r31, GENREG_OFF(0) ; \

+ st.d r2 , r31, GENREG_OFF(2) ; \

+ st.d r4 , r31, GENREG_OFF(4) ; \

+ st.d r6 , r31, GENREG_OFF(6) ; \

+ st.d r8 , r31, GENREG_OFF(8) ; \

+ st.d r10, r31, GENREG_OFF(10) ; \

+ st.d r12, r31, GENREG_OFF(12) ; \

+ st.d r14, r31, GENREG_OFF(14) ; \

+ st.d r16, r31, GENREG_OFF(16) ; \

+ st.d r18, r31, GENREG_OFF(18) ; \

+ st.d r20, r31, GENREG_OFF(20) ; \

+ st.d r22, r31, GENREG_OFF(22) ; \

+ st.d r24, r31, GENREG_OFF(24) ; \

+ st.d r26, r31, GENREG_OFF(26) ; \

+ st.d r28, r31, GENREG_OFF(28) ; \

+ st r30, r31, GENREG_OFF(30) ; \

+ ldcr r1, SRX ; \

+ st r1, r31, GENREG_OFF(31) ; \

+ ldcr r1, EPSR ; \

+ ldcr r2, EXIP ; \

+ ldcr r3, ENIP ; \

+ st r1, r31, REG_OFF(EF_EPSR) ; \

+ st r2, r31, REG_OFF(EF_EXIP) ; \

+ st r3, r31, REG_OFF(EF_ENIP) ; \

+ ldcr r1, DSR ; \

+ ldcr r2, DLAR ; \

+ ldcr r3, DPAR ; \

+ st r1, r31, REG_OFF(EF_DSR) ; \

+ st r2, r31, REG_OFF(EF_DLAR) ; \

+ st r3, r31, REG_OFF(EF_DPAR) ; \

+ ldcr r1, ISR ; \

+ ldcr r2, ILAR ; \

+ ldcr r3, IPAR ; \

+ st r1, r31, REG_OFF(EF_ISR) ; \

+ st r2, r31, REG_OFF(EF_ILAR) ; \

+ st r3, r31, REG_OFF(EF_IPAR) ; \

+ ldcr r1, DSAP ; \

+ ldcr r2, DUAP ; \

+ st r1, r31, REG_OFF(EF_DSAP) ; \

+ st r2, r31, REG_OFF(EF_DUAP) ; \

+ ldcr r1, ISAP ; \

+ ldcr r2, IUAP ; \

+ st r1, r31, REG_OFF(EF_ISAP) ; \

+ st r2, r31, REG_OFF(EF_IUAP) ; \

+ /* Restore r1, r2, r3, and r31 */ ; \

+ ld r1 , r31, GENREG_OFF(1) ; \

+ ld.d r2 , r31, GENREG_OFF(2) ; \

+ ld r31, r31, GENREG_OFF(31)

/***************************************************************************

***************************************************************************

@@ -322,19 +388,19 @@ Lbadcpupanic:

#ifdef M88110

#define PREP2(NAME, NUM, BIT, SSBR_STUFF, FLAG_PRECHECK); \

+ SAVE_CTX ; \

xcr FLAGS, FLAGS, SR1 ; \

FLAG_PRECHECK ; \

- ; \

/* the bsr later clobbers r1, so save now */ ; \

- stcr r1, SR2 /* r1 now free */ ; \

+ stcr r1, SR2 /* r1 now free */ ; \

/* set or clear the FLAG_FROM_KERNEL bit */ ; \

- ldcr r1, EPSR ; \

- bb0.n PSR_SUPERVISOR_MODE_BIT, r1, 1f ; \

- clr FLAGS, FLAGS, 1<FLAG_FROM_KERNEL> ; \

- set FLAGS, FLAGS, 1<FLAG_FROM_KERNEL> ; \

+1: ldcr r1, EPSR ; \

+ bb0.n PSR_SUPERVISOR_MODE_BIT, r1, 1f ; \

+ clr FLAGS, FLAGS, 1<FLAG_FROM_KERNEL> ; \

+ set FLAGS, FLAGS, 1<FLAG_FROM_KERNEL> ; \

; \

/* get a stack (exception frame) */ ; \

- 1: bsr m197_setup_phase_one ; \

+ 1: bsr m88110_setup_phase_one ; \

; \

/* TMP2 now free -- use to set EF_VECTOR */ ; \

or TMP2, r0, NUM ; \

@@ -342,7 +408,7 @@ Lbadcpupanic:

; \

/* call setup_phase_two to restart the FPU */ ; \

/* and to save all general registers. */ ; \

- bsr m197_setup_phase_two ; \

+ bsr m88110_setup_phase_two ; \

; \

/* All general regs free -- do any debugging */ ; \

PREP_DEBUG(BIT, NAME)

@@ -354,8 +420,8 @@ Lbadcpupanic:

#define No_Precheck /* empty */

#define Data_Precheck \

bb1.n FLAG_IGNORE_DATA_EXCEPTION, FLAGS, ignore_data_exception

-#define M197_Data_Precheck \

- bb1.n FLAG_IGNORE_DATA_EXCEPTION, FLAGS, m197_ignore_data_exception

+#define M88110_Data_Precheck \

+ bb1.n FLAG_IGNORE_DATA_EXCEPTION, FLAGS, m88110_ignore_data_exception

#ifdef EH_DEBUG

@@ -366,8 +432,9 @@ Lbadcpupanic:

* The bits are defined in "asm.h"

-GLOBAL(eh_debug) word 0x00000000

+GLOBAL(eh_debug) word 0x00000000

* additional pre-servicing preparation to be done when

* debugging... check eh_debug and make the call if

@@ -425,43 +492,43 @@ GLOBAL(eh_debug) word 0x00000000

/* unknown exception handler */

GLOBAL(unknown_handler)

- PREP("unknown", 0, DEBUG_UNKNOWN_BIT, No_SSBR_Stuff, No_Precheck)

- CALL(_C_LABEL(trap18x), T_UNKNOWNFLT, r30)

- DONE(DEBUG_UNKNOWN_BIT)

+ PREP("unknown", 0, DEBUG_UNKNOWN_BIT, No_SSBR_Stuff, No_Precheck)

+ CALL(_C_LABEL(m88100_trap), T_UNKNOWNFLT, r30)

+ DONE(DEBUG_UNKNOWN_BIT)

/* interrupt exception handler */

GLOBAL(interrupt_handler)

- PREP("interrupt", 1, DEBUG_INTERRUPT_BIT, No_SSBR_Stuff, No_Precheck)

- /* interrupt_func is set in mvme_bootstrap() */

- CALL(_C_LABEL(trap18x), T_INT, r30)

- /*CALLP(_interrupt_func, 1, r30) */

- DONE(DEBUG_INTERRUPT_BIT)

+ PREP("interrupt", 1, DEBUG_INTERRUPT_BIT, No_SSBR_Stuff, No_Precheck)

+ /* interrupt_func is set in mvme_bootstrap() */

+ CALL(_C_LABEL(m88100_trap), T_INT, r30)

+ /*CALLP(_interrupt_func, 1, r30) */

+ DONE(DEBUG_INTERRUPT_BIT)

/* instruction access exception handler */

GLOBAL(instruction_access_handler)

- PREP("inst", 2, DEBUG_INSTRUCTION_BIT, No_SSBR_Stuff, No_Precheck)

- CALL(_C_LABEL(trap18x), T_INSTFLT, r30)

- DONE(DEBUG_INSTRUCTION_BIT)

+ PREP("inst", 2, DEBUG_INSTRUCTION_BIT, No_SSBR_Stuff, No_Precheck)

+ CALL(_C_LABEL(m88100_trap), T_INSTFLT, r30)

+ DONE(DEBUG_INSTRUCTION_BIT)

* data access exception handler --

* See badaddr() below for info about Data_Precheck.

GLOBAL(data_exception_handler)

- PREP("data", 3, DEBUG_DATA_BIT, No_SSBR_Stuff, Data_Precheck)

- DONE(DEBUG_DATA_BIT)

+ PREP("data", 3, DEBUG_DATA_BIT, No_SSBR_Stuff, Data_Precheck)

+ DONE(DEBUG_DATA_BIT)

/* misaligned access exception handler */

GLOBAL(misaligned_handler)

- PREP("misalign", 4, DEBUG_MISALIGN_BIT, Clear_SSBR_Dest, No_Precheck)

- CALL(_C_LABEL(trap18x), T_MISALGNFLT, r30)

- DONE(DEBUG_MISALIGN_BIT)

+ PREP("misalign", 4, DEBUG_MISALIGN_BIT, Clear_SSBR_Dest, No_Precheck)

+ CALL(_C_LABEL(m88100_trap), T_MISALGNFLT, r30)

+ DONE(DEBUG_MISALIGN_BIT)

/* unimplemented opcode exception handler */

GLOBAL(unimplemented_handler)

- PREP("unimp", 5, DEBUG_UNIMPLEMENTED_BIT, No_SSBR_Stuff, No_Precheck)

- CALL(_C_LABEL(trap18x), T_ILLFLT, r30)

- DONE(DEBUG_UNIMPLEMENTED_BIT)

+ PREP("unimp", 5, DEBUG_UNIMPLEMENTED_BIT, No_SSBR_Stuff, No_Precheck)

+ CALL(_C_LABEL(m88100_trap), T_ILLFLT, r30)

+ DONE(DEBUG_UNIMPLEMENTED_BIT)

* Some versions of the chip have a bug whereby false privilege

@@ -469,112 +536,115 @@ GLOBAL(unimplemented_handler)

* it is false. If so, just return. The code before PREP handles this....

GLOBAL(privilege_handler)

- stcr r1, SR2 /* hold r1 for a moment */

- ldcr r1, SXIP /* look at the sxip... valid bit set? */

- bb1.n RTE_VALID_BIT, r1, 1f /*skip over return if a valid exception*/

- ldcr r1, SR2 /* restore r1 */

- RTE

-1: PREP("privilege", 6, DEBUG_PRIVILEGE_BIT, Clear_SSBR_Dest, No_Precheck)

- CALL(_C_LABEL(trap18x), T_PRIVINFLT, r30)

- DONE(DEBUG_PRIVILEGE_BIT)

+ stcr r1, SR2 /* hold r1 for a moment */

+ ldcr r1, SXIP /* look at the sxip... valid bit set? */

+ bb1.n RTE_VALID_BIT, r1, 1f /*skip over return if a valid exception*/

+ ldcr r1, SR2 /* restore r1 */

+ RTE

+1: PREP("privilege", 6, DEBUG_PRIVILEGE_BIT, Clear_SSBR_Dest, No_Precheck)

+ CALL(_C_LABEL(m88100_trap), T_PRIVINFLT, r30)

+ DONE(DEBUG_PRIVILEGE_BIT)

* I'm not sure what the trap(T_BNDFLT,...) does, but it doesn't send

* a signal to the process...

GLOBAL(bounds_handler)

- PREP("bounds", 7, DEBUG_BOUNDS_BIT, Clear_SSBR_Dest, No_Precheck)

- CALL(_C_LABEL(trap18x), T_BNDFLT, r30)

- DONE(DEBUG_BOUNDS_BIT)

+ PREP("bounds", 7, DEBUG_BOUNDS_BIT, Clear_SSBR_Dest, No_Precheck)

+ CALL(_C_LABEL(m88100_trap), T_BNDFLT, r30)

+ DONE(DEBUG_BOUNDS_BIT)

/* integer divide-by-zero exception handler */

GLOBAL(divide_handler)

- PREP("divide", 8, DEBUG_DIVIDE_BIT, Clear_SSBR_Dest, No_Precheck)

- CALL(_C_LABEL(trap18x), T_ZERODIV, r30)

- DONE(DEBUG_DIVIDE_BIT)

+ PREP("divide", 8, DEBUG_DIVIDE_BIT, Clear_SSBR_Dest, No_Precheck)

+ CALL(_C_LABEL(m88100_trap), T_ZERODIV, r30)

+ DONE(DEBUG_DIVIDE_BIT)

/* integer overflow exception handelr */

GLOBAL(overflow_handler)

- PREP("overflow", 9, DEBUG_OVERFLOW_BIT, No_SSBR_Stuff, No_Precheck)

- CALL(_C_LABEL(trap18x), T_OVFFLT, r30)

- DONE(DEBUG_OVERFLOW_BIT)

+ PREP("overflow", 9, DEBUG_OVERFLOW_BIT, No_SSBR_Stuff, No_Precheck)

+ CALL(_C_LABEL(m88100_trap), T_OVFFLT, r30)

+ DONE(DEBUG_OVERFLOW_BIT)

/* Floating-point precise handler */

#define FPp_SSBR_STUFF bsr clear_FPp_ssbr_bit

ASGLOBAL(fp_precise_handler)

- PREP("FPU precise", 114, DEBUG_FPp_BIT, FPp_SSBR_STUFF, No_Precheck)

- CALL(_m88100_Xfp_precise, r0, r30) /* call fp_precise(??, exception_frame)*/

- DONE(DEBUG_FPp_BIT)

+ PREP("FPU precise", 114, DEBUG_FPp_BIT, FPp_SSBR_STUFF, No_Precheck)

+ CALL(_m88100_Xfp_precise, r0, r30) /* call fp_precise(??, exception_frame)*/

+ DONE(DEBUG_FPp_BIT)

/* Floating-point imprecise handler */

#define FPi_SSBR_STUFF bsr clear_FPi_ssbr_bit

ASGLOBAL(fp_imprecise_handler)

- PREP("FPU imprecise", 115, DEBUG_FPi_BIT, FPi_SSBR_STUFF, No_Precheck)

- CALL(_Xfp_imprecise, r0, r30) /*call fp_imprecise(??,exception_frame)*/

- DONE(DEBUG_FPi_BIT)

+ PREP("FPU imprecise", 115, DEBUG_FPi_BIT, FPi_SSBR_STUFF, No_Precheck)

+ CALL(_Xfp_imprecise, r0, r30) /*call fp_imprecise(??,exception_frame)*/

+ DONE(DEBUG_FPi_BIT)

/* All standard system calls. */

GLOBAL(syscall_handler)

- PREP("syscall", 128, DEBUG_SYSCALL_BIT, No_SSBR_Stuff, No_Precheck)

- ld r13, r30, GENREG_OFF(13)

- CALL(_syscall, r13, r30) /* system call no. is in r13 */

- DONE(DEBUG_SYSCALL_BIT)

+ PREP("syscall", 128, DEBUG_SYSCALL_BIT, No_SSBR_Stuff, No_Precheck)

+ ld r13, r30, GENREG_OFF(13)

+ CALL(_m88100_syscall, r13, r30) /* system call no. is in r13 */

+ DONE(DEBUG_SYSCALL_BIT)

/* trap 496 comes here */

GLOBAL(bugtrap)

- PREP("bugsyscall", 496, DEBUG_BUGCALL_BIT, No_SSBR_Stuff, No_Precheck)

- ld r9, r30, GENREG_OFF(9)

- CALL(_bugsyscall, r9, r30) /* system call no. is in r9 */

- DONE(DEBUG_SYSCALL_BIT)

+ PREP("bugsyscall", 496, DEBUG_BUGCALL_BIT, No_SSBR_Stuff, No_Precheck)

+ ld r9, r30, GENREG_OFF(9)

+ CALL(_bugsyscall, r9, r30) /* system call no. is in r9 */

+ DONE(DEBUG_BUGCALL_BIT)

GLOBAL(sigsys)

- PREP("sigsys", 0, DEBUG_SIGSYS_BIT, No_SSBR_Stuff, No_Precheck)

- CALL(_C_LABEL(trap18x), T_SIGSYS, r30)

- DONE(DEBUG_SIGSYS_BIT)

+ PREP("sigsys", 0, DEBUG_SIGSYS_BIT, No_SSBR_Stuff, No_Precheck)

+ CALL(_C_LABEL(m88100_trap), T_SIGSYS, r30)

+ DONE(DEBUG_SIGSYS_BIT)

GLOBAL(sigtrap)

- PREP("sigtrap", 0, DEBUG_SIGTRAP_BIT, No_SSBR_Stuff, No_Precheck)

- CALL(_C_LABEL(trap18x), T_SIGTRAP, r30)

- DONE(DEBUG_SIGTRAP_BIT)

+ PREP("sigtrap", 0, DEBUG_SIGTRAP_BIT, No_SSBR_Stuff, No_Precheck)

+ CALL(_C_LABEL(m88100_trap), T_SIGTRAP, r30)

+ DONE(DEBUG_SIGTRAP_BIT)

GLOBAL(stepbpt)

- PREP("stepbpt", 0, DEBUG_SIGTRAP_BIT, No_SSBR_Stuff, No_Precheck)

- CALL(_C_LABEL(trap18x), T_STEPBPT, r30)

- DONE(DEBUG_SIGTRAP_BIT)

+ PREP("stepbpt", 0, DEBUG_SIGTRAP_BIT, No_SSBR_Stuff, No_Precheck)

+ CALL(_C_LABEL(m88100_trap), T_STEPBPT, r30)

+ DONE(DEBUG_SIGTRAP_BIT)

GLOBAL(userbpt)

- PREP("userbpt", 0, DEBUG_SIGTRAP_BIT, No_SSBR_Stuff, No_Precheck)

- CALL(_C_LABEL(trap18x), T_USERBPT, r30)

- DONE(DEBUG_SIGTRAP_BIT)

+ PREP("userbpt", 0, DEBUG_SIGTRAP_BIT, No_SSBR_Stuff, No_Precheck)

+ CALL(_C_LABEL(m88100_trap), T_USERBPT, r30)

+ DONE(DEBUG_SIGTRAP_BIT)

#if DDB

- ASGLOBAL(break)

- PREP("break", 130, DEBUG_BREAK_BIT, No_SSBR_Stuff, No_Precheck)

- CALL(_C_LABEL(trap18x), T_KDB_BREAK, r30)

- DONE(DEBUG_BREAK_BIT)

- ASGLOBAL(trace)

- PREP("trace", 131, DEBUG_TRACE_BIT, No_SSBR_Stuff, No_Precheck)

- CALL(_C_LABEL(trap18x), T_KDB_TRACE, r30)

- DONE(DEBUG_TRACE_BIT)

- GLOBAL(entry)

- PREP("kdb", 132, DEBUG_KDB_BIT, No_SSBR_Stuff, No_Precheck)

- CALL(_C_LABEL(trap18x), T_KDB_ENTRY, r30)

- DONE(DEBUG_KDB_BIT)

+ASGLOBAL(break)

+ PREP("break", 130, DEBUG_BREAK_BIT, No_SSBR_Stuff, No_Precheck)

+ CALL(_C_LABEL(m88100_trap), T_KDB_BREAK, r30)

+ DONE(DEBUG_BREAK_BIT)

+ASGLOBAL(trace)

+ PREP("trace", 131, DEBUG_TRACE_BIT, No_SSBR_Stuff, No_Precheck)

+ CALL(_C_LABEL(m88100_trap), T_KDB_TRACE, r30)

+ DONE(DEBUG_TRACE_BIT)

+GLOBAL(entry)

+ PREP("kdb", 132, DEBUG_KDB_BIT, No_SSBR_Stuff, No_Precheck)

+ CALL(_C_LABEL(m88100_trap), T_KDB_ENTRY, r30)

+ DONE(DEBUG_KDB_BIT)

#else /* else not DDB */

- ASGLOBAL(break)

- PREP("break", 130, DEBUG_BREAK_BIT, No_SSBR_Stuff, No_Precheck)

- CALL(_C_LABEL(trap18x), T_UNKNOWNFLT, r30)

- DONE(DEBUG_BREAK_BIT)

- ASGLOBAL(trace)

- PREP("trace", 131, DEBUG_TRACE_BIT, No_SSBR_Stuff, No_Precheck)

- CALL(_C_LABEL(trap18x), T_UNKNOWNFLT, r30)

- DONE(DEBUG_TRACE_BIT)

- GLOBAL(entry)

- PREP("unknown", 132, DEBUG_UNKNOWN_BIT, No_SSBR_Stuff, No_Precheck)

- CALL(_C_LABEL(trap18x), T_UNKNOWNFLT, r30)

- DONE(DEBUG_KDB_BIT)

+ASGLOBAL(break)

+ PREP("break", 130, DEBUG_BREAK_BIT, No_SSBR_Stuff, No_Precheck)

+ CALL(_C_LABEL(m88100_trap), T_UNKNOWNFLT, r30)

+ DONE(DEBUG_BREAK_BIT)

+ASGLOBAL(trace)

+ PREP("trace", 131, DEBUG_TRACE_BIT, No_SSBR_Stuff, No_Precheck)

+ CALL(_C_LABEL(m88100_trap), T_UNKNOWNFLT, r30)

+ DONE(DEBUG_TRACE_BIT)

+GLOBAL(entry)

+ PREP("unknown", 132, DEBUG_UNKNOWN_BIT, No_SSBR_Stuff, No_Precheck)

+ CALL(_C_LABEL(m88100_trap), T_UNKNOWNFLT, r30)

+ DONE(DEBUG_KDB_BIT)

#endif /* DDB */

/*--------------------------------------------------------------------------*/

@@ -685,7 +755,7 @@ GLOBAL(error_handler)

bb1 ne, r10, 3f

or.u r10, r0, hi16(IST_REG) /* interrupt status register */

ld r11, r10, lo16(IST_REG)

- st r11, r31, REG_OFF(EF_MASK) /* put in EF_MASK for regdump */

+ st r11, r31, REG_OFF(EF_MASK) /* put in EF_MASK for regdump */

#endif /* MVME188 */

* Cheap way to enable FPU and start shadowing again.

@@ -707,7 +777,7 @@ GLOBAL(error_handler)

st r20, r31, 0x04

st r20, r31, 0x00

- CALL(_error_fault, r30, r30)

+ CALL(_C_LABEL(error_fault), r30, r30)

/* TURN INTERUPTS back on */

ldcr r1, PSR

@@ -845,7 +915,7 @@ GLOBAL(reset_handler)

st r20, r31, 0x04

st r20, r31, 0x00

- CALL(_error_reset, r30, r30)

+ CALL(_C_LABEL(error_reset), r30, r30)

/* TURN INTERUPTS back on */

ldcr r1, PSR

@@ -897,12 +967,12 @@ ASGLOBAL(ignore_data_exception)

* This is part of baddadr (below).

-ASGLOBAL(m197_ignore_data_exception)

+ASGLOBAL(m88110_ignore_data_exception)

/******************************************************\

* SR0: pointer to the current thread structure *

- * SR1: previous FLAGS reg *

+ * SR1: previous FLAGS reg *

* SR2: free *

- * SR3: must presere *

+ * SR3: must preserve *

* FLAGS: CPU status flags *

\******************************************************/

xcr FLAGS, FLAGS, SR1 /* replace SR1, FLAGS */

@@ -910,18 +980,18 @@ ASGLOBAL(m197_ignore_data_exception)

* For more info, see badaddr() below.

- * We just want to jump to "badaddr__return_nonzero" below.

+ * We just want to jump to "m88110_badaddr__return_nonzero" below.

* We don't worry about trashing R2 here because we're

* jumping back to the function badaddr() where we're allowd

* to blast r2..r9 as we see fit.

- or.u r2, r0, hi16(badaddr__return_nonzero)

- or r2, r2, lo16(badaddr__return_nonzero)

- stcr r2, SXIP /* Make it the next instruction to execute */

+ or.u r2, r0, hi16(m88110_badaddr__return_nonzero)

+ or r2, r2, lo16(m88110_badaddr__return_nonzero)

+ stcr r2, EXIP /* Make it the next instruction to execute */

- /* the following jumps to "badaddr__return_nonzero" in below */

+ /* the following jumps to "m88110_badaddr__return_nonzero" below */

NOP

RTE

#endif /* M88110 */

@@ -949,10 +1019,10 @@ ASGLOBAL(m197_ignore_data_exception)

GLOBAL(badaddr)

- /*

- * Disable interrupts ... don't want a context switch while we're

- * doing this! Also, save the old PSR in R8 to restore later.

- */

+ /*

+ * Disable interrupts ... don't want a context switch while we're

+ * doing this! Also, save the old PSR in R8 to restore later.

+ */

ldcr r8, PSR

set r4, r8, 1<PSR_INTERRUPT_DISABLE_BIT>

FLUSH_PIPELINE

@@ -1021,10 +1091,10 @@ badaddr__unknown_size:

or.u r2, r0, hi16(1b)

or r2, r2, lo16(1b)

or r4, r0, r1

- bsr _printf

+ bsr _C_LABEL(printf)

or.u r2, r0, hi16(1b)

or r2, r2, lo16(1b)

- bsr _panic

+ bsr _C_LABEL(panic)

/*NOTREACHED*/

#endif

@@ -1048,6 +1118,18 @@ ASGLOBAL(badaddr__return)

stcr r8, PSR

jmp r1

+ASGLOBAL(m88110_badaddr__return_nonzero)

+ /*

+ * On mc88110, we possibly took an exception

+ * and we have to clear DSR after the rte

+ * instruction clears the EFRZ bit in

+ * the PSR.

+ */

+ stcr r0, DSR /* Clear DSR reg on mc88110 */

+ stcr r0, DLAR /* Clear DLAR reg on mc88110 */

+ br.n badaddr__return_nonzero

+ stcr r0, DPAR /* Clear DPAR reg on mc88110 */

******************************************************************************

@@ -1057,22 +1139,22 @@ ASGLOBAL(badaddr__return)

#ifdef M88100

ASGLOBAL(setup_phase_one)

- /***************** REGISTER STATUS BLOCK ***********************\

- * SR0: current thread (if any, null if not) *

- * SR1: saved copy of exception-time register now holding FLAGS *

- * SR2: saved copy of exception-time r1 *

- * SR3: must be preserved .. may be the exception-time stack *

- * r1: return address to calling exception handler *

- * FLAGS: CPU status flags *

- *************************************************** *

- * immediate goal: *

- * Decide where we're going to put the exception frame. *

- * Might be at the end of R31, SR3, or the thread's *

- * pcb. *

- \***************************************************************/

- /* Check if we are coming in from a FPU restart exception.

- If so, the pcb will be in SR3 */

+ /***************** REGISTER STATUS BLOCK ***********************\

+ * SR0: current thread (if any, null if not) *

+ * SR1: saved copy of exception-time register now holding FLAGS *

+ * SR2: saved copy of exception-time r1 *

+ * SR3: must be preserved .. may be the exception-time stack *

+ * r1: return address to calling exception handler *

+ * FLAGS: CPU status flags *

+ *************************************************** *

+ * immediate goal: *

+ * Decide where we're going to put the exception frame. *

+ * Might be at the end of R31, SR3, or the thread's *

+ * pcb. *

+ \***************************************************************/

+ /* Check if we are coming in from a FPU restart exception.

+ If so, the pcb will be in SR3 */

NOP

xcr r1, r1, SR2

NOP

@@ -1080,23 +1162,23 @@ ASGLOBAL(setup_phase_one)

NOP

bb1 FLAG_ENABLING_FPU, FLAGS, use_SR3_pcb

- /* are we coming in from user mode? If so, pick up thread pcb */

+ /* are we coming in from user mode? If so, pick up thread pcb */

bb0 FLAG_FROM_KERNEL, FLAGS, pickup_stack

- /* Interrupt in kernel mode, not FPU restart */

+ /* Interrupt in kernel mode, not FPU restart */

ASGLOBAL(already_on_kernel_stack)

- /***************** REGISTER STATUS BLOCK ***********************\

- * SR0: current thread (if any, null if not) *

- * SR1: saved copy of exception-time register now holding FLAGS *

- * SR2: return address to the calling exception handler *

- * SR3: must be preserved; may be important for other exceptions *

- * FLAGS: CPU status flags *

- *************************************************** *

- * immediate goal: *

- * We're already on the kernel stack, but not having *

- * needed to use SR3. We can just make room on the *

- * stack (r31) for our exception frame. *

- \***************************************************************/

+ /***************** REGISTER STATUS BLOCK ***********************\

+ * SR0: current thread (if any, null if not) *

+ * SR1: saved copy of exception-time register now holding FLAGS *

+ * SR2: return address to the calling exception handler *

+ * SR3: must be preserved; may be important for other exceptions *

+ * FLAGS: CPU status flags *

+ *************************************************** *

+ * immediate goal: *

+ * We're already on the kernel stack, but not having *

+ * needed to use SR3. We can just make room on the *

+ * stack (r31) for our exception frame. *

+ \***************************************************************/

subu r31, r31, SIZEOF_EF /* r31 now our E.F. */

st FLAGS,r31, REG_OFF(EF_FLAGS) /* save flags */

st r1, r31, GENREG_OFF(1) /* save prev. r1 (now r1 free)*/

@@ -1110,35 +1192,35 @@ ASGLOBAL(already_on_kernel_stack)

ASGLOBAL(use_SR3_pcb)

- /***************** REGISTER STATUS BLOCK ***********************\

- * SR0: current thread (if any, null if not) *

- * SR1: saved copy of exception-time register now holding FLAGS *

- * SR2: return address to the calling exception handler *

- * SR3: must be preserved; exception-time stack pointer *

- * FLAGS: CPU status flags *

- *************************************************** *

- * immediate goal: *

- * An exception occurred while enabling the FPU. Since r31 *

- * is the user's r31 while enabling the FPU, we had put *

- * our pcb pointer into SR3, so make room from *

- * there for our stack pointer. *

- * We need to check if SR3 is the old stack pointer or the *

- * pointer off to the user pcb. If it pointing to the user *

- * pcb, we need to pick up the kernel stack. Otherwise *

- * we need to allocate a frame upon it. *

- * We look at the EPSR to see if it was from user mode *

- * Unfortunately, we have no registers free at the moment *

- * But we know register 0 in the pcb frame will always be *

- * zero, so we can use it as scratch storage. *

- * *

- \***************************************************************/

+ /***************** REGISTER STATUS BLOCK ***********************\

+ * SR0: current thread (if any, null if not) *

+ * SR1: saved copy of exception-time register now holding FLAGS *

+ * SR2: return address to the calling exception handler *

+ * SR3: must be preserved; exception-time stack pointer *

+ * FLAGS: CPU status flags *

+ *************************************************** *

+ * immediate goal: *

+ * An exception occured while enabling the FPU. Since r31 *

+ * is the user's r31 while enabling the FPU, we had put *

+ * our pcb pointer into SR3, so make room from *

+ * there for our stack pointer. *

+ * We need to check if SR3 is the old stack pointer or the *

+ * pointer off to the user pcb. If it pointing to the user *

+ * pcb, we need to pick up the kernel stack. Otherwise *

+ * we need to allocate a frame upon it. *

+ * We look at the EPSR to see if it was from user mode *

+ * Unfortunately, we have no registers free at the moment *

+ * But we know register 0 in the pcb frame will always be *

+ * zero, so we can use it as scratch storage. *

+ * *

+ \***************************************************************/

xcr r30, r30, SR3 /* r30 = old exception frame */

st r1, r30, GENREG_OFF(0) /* free up r1 */

ld r1, r30, REG_OFF(EF_EPSR) /* get back the epsr */

bb0.n PSR_SUPERVISOR_MODE_BIT, r1, 1f /* if user mode */

ld r1, r30, GENREG_OFF(0) /* restore r1 */

- /* we were in kernel mode - dump frame upon the stack */

+ /* we were in kernel mode - dump frame upon the stack */

st r0, r30, GENREG_OFF(0) /* repair old frame */

subu r30, r30, SIZEOF_EF /* r30 now our E.F. */

st FLAGS,r30, REG_OFF(EF_FLAGS) /* save flags */

@@ -1151,10 +1233,10 @@ ASGLOBAL(use_SR3_pcb)

br.n have_pcb

xcr r30, r30, SR3 /* restore r30 */

- /* we took an exception while restarting the FPU from user space.

- * Consequently, we never picked up a stack. Do so now.

- * R1 is currently free (saved in the exception frame pointed at by

- * r30) */

+ /* we took an exception while restarting the FPU from user space.

+ * Consequently, we never picked up a stack. Do so now.

+ * R1 is currently free (saved in the exception frame pointed at by

+ * r30) */

or.u r1, r0, hi16(_kstack)

ld r1, r1, lo16(_kstack)

addu r1, r1, USIZE-SIZEOF_EF

@@ -1169,21 +1251,21 @@ ASGLOBAL(use_SR3_pcb)

xcr r30, r30, SR3 /* restore r30 */

ASGLOBAL(pickup_stack)

- /***************** REGISTER STATUS BLOCK ***********************\

- * SR0: current thread *

- * SR1: saved copy of exception-time register now holding FLAGS *

- * SR2: return address to the calling exception handler *

- * SR3: free *

- * FLAGS: CPU status flags *

- *************************************************** *

- * immediate goal: *

- * Since we're servicing an exception from user mode, we *

- * know that SR3 is free. We use it to free up a temp. *

- * register to be used in getting the thread's pcb *

- \***************************************************************/

+ /***************** REGISTER STATUS BLOCK ***********************\

+ * SR0: current thread *

+ * SR1: saved copy of exception-time register now holding FLAGS *

+ * SR2: return address to the calling exception handler *

+ * SR3: free *

+ * FLAGS: CPU status flags *

+ *************************************************** *

+ * immediate goal: *

+ * Since we're servicing an exception from user mode, we *

+ * know that SR3 is free. We use it to free up a temp. *

+ * register to be used in getting the thread's pcb *

+ \***************************************************************/

stcr r31, SR3 /* save previous r31 */

- /* switch to the thread's kernel stack. */

+ /* switch to the thread's kernel stack. */

or.u r31, r0, hi16(_curpcb)

ld r31, r31, lo16(_curpcb)

addu r31, r31, PCB_USER_STATE /* point to user save area */

@@ -1191,7 +1273,7 @@ ASGLOBAL(pickup_stack)

st r1, r31, GENREG_OFF(1) /* save prev. r1 (now r1 free)*/

ldcr r1, SR3 /* save previous r31 */

st r1, r31, GENREG_OFF(31)

- /*FALLTHROUGH */

+ /*FALLTHROUGH */

ASGLOBAL(have_pcb)

/***************** REGISTER STATUS BLOCK ***********************\

@@ -1392,25 +1474,25 @@ ASGLOBAL(do_DMT2_double)

1: clr TMP, TMP, TMP2

ASGLOBAL(DMT_check_finished)

- /***************** REGISTER STATUS BLOCK ***********************\

- * SR0: current thread *

- * SR1: saved copy of exception-time register now holding FLAGS *

- * SR2: return address to the calling exception handler *

- * SR3: saved TMP *

- * r1: free *

- * TMP: possibly revised SSBR *

- * TMP2: free *

- * TMP3: free *

- * FLAGS: CPU status flags *

- * r31: exception frame *

- * Valid in the exception frame: *

- * Exception-time r1, r31, FLAGS. *

- * Exception-time TMP2, TMP3. *

- * Exception-time espr, sfip, snip, sxip. *

- * Dmt0. *

- * Other data pipeline control registers, if appropriate. *

- * Exception SR3, if appropriate. *

- \***************************************************************/

+ /***************** REGISTER STATUS BLOCK ***********************\

+ * SR0: current thread *

+ * SR1: saved copy of exception-time register now holding FLAGS *

+ * SR2: return address to the calling exception handler *

+ * SR3: saved TMP *

+ * r1: free *

+ * TMP: possibly revised SSBR *

+ * TMP2: free *

+ * TMP3: free *

+ * FLAGS: CPU status flags *

+ * r31: exception frame *

+ * Valid in the exception frame: *

+ * Exception-time r1, r31, FLAGS. *

+ * Exception-time TMP2, TMP3. *

+ * Exception-time espr, sfip, snip, sxip. *

+ * Dmt0. *

+ * Other data pipeline control registers, if appropriate. *

+ * Exception SR3, if appropriate. *

+ \***************************************************************/

ldcr r1, SR2

jmp r1 /* return to allow the handler to clear more SSBR bits */

@@ -1420,15 +1502,15 @@ ASGLOBAL(DMT_check_finished)

/************************************************************************/

ASGLOBAL(clear_FPi_ssbr_bit)

- /*

- * Clear floatingpont-imprecise ssbr bits.

- * Also, save appropriate FPU control registers to the E.F.

- *

- * r1: return address to calling exception handler

- * TMP : (possibly) revised ssbr

- * TMP2 : free

- * TMP3 : free

- */

+ /*

+ * Clear floatingpont-imprecise ssbr bits.

+ * Also, save appropriate FPU control registers to the E.F.

+ *

+ * r1: return address to calling exception handler

+ * TMP : (possibly) revised ssbr

+ * TMP2 : free

+ * TMP3 : free

+ */

fldcr TMP2, FPSR

fldcr TMP3, FPCR

st TMP2, r31, REG_OFF(EF_FPSR)

@@ -1444,10 +1526,10 @@ ASGLOBAL(clear_FPi_ssbr_bit)

st TMP2, r31, REG_OFF(EF_FPIT)

st TMP3, r31, REG_OFF(EF_FPRL)

- /*

- * We only need clear the bit in the SSBR for the

- * 2nd reg of a double result [see section 6.8.5]

- */

+ /*

+ * We only need clear the bit in the SSBR for the

+ * 2nd reg of a double result [see section 6.8.5]

+ */

#define FPIT_SIZE_BIT 10

bb0 FPIT_SIZE_BIT, TMP2, not_double_fpi

extu TMP2, TMP2, 5<0> /* get the reg. */

@@ -1463,42 +1545,42 @@ ASGLOBAL(not_double_fpi)

ASGLOBAL(clear_FPp_ssbr_bit)

- /*

- * Clear floating pont precise ssbr bits.

- * Also, save appropriate FPU control registers to the E.F.

- *

- * r1: return address to calling exception handler

- * TMP : (possibly) revised ssbr

- * TMP2 : free

- * TMP3 : free

- */

- fldcr TMP2, FPSR

- fldcr TMP3, FPCR

- st TMP2, r31, REG_OFF(EF_FPSR)

- st TMP3, r31, REG_OFF(EF_FPCR)

- fldcr TMP3, FPECR

- st TMP3, r31, REG_OFF(EF_FPECR)

- fldcr TMP2, FPHS1

- fldcr TMP3, FPHS2

- st TMP2, r31, REG_OFF(EF_FPHS1)

- st TMP3, r31, REG_OFF(EF_FPHS2)

- fldcr TMP2, FPLS1

- fldcr TMP3, FPLS2

- st TMP2, r31, REG_OFF(EF_FPLS1)

- st TMP3, r31, REG_OFF(EF_FPLS2)

- fldcr TMP2, FPPT

- st TMP2, r31, REG_OFF(EF_FPPT)

+ /*

+ * Clear floating pont precise ssbr bits.

+ * Also, save appropriate FPU control registers to the E.F.

+ *

+ * r1: return address to calling exception handler

+ * TMP : (possibly) revised ssbr

+ * TMP2 : free

+ * TMP3 : free

+ */

+ fldcr TMP2, FPSR

+ fldcr TMP3, FPCR

+ st TMP2, r31, REG_OFF(EF_FPSR)

+ st TMP3, r31, REG_OFF(EF_FPCR)

+ fldcr TMP3, FPECR

+ st TMP3, r31, REG_OFF(EF_FPECR)

+ fldcr TMP2, FPHS1

+ fldcr TMP3, FPHS2

+ st TMP2, r31, REG_OFF(EF_FPHS1)

+ st TMP3, r31, REG_OFF(EF_FPHS2)

+ fldcr TMP2, FPLS1

+ fldcr TMP3, FPLS2

+ st TMP2, r31, REG_OFF(EF_FPLS1)

+ st TMP3, r31, REG_OFF(EF_FPLS2)

+ fldcr TMP2, FPPT

+ st TMP2, r31, REG_OFF(EF_FPPT)

#define FPPT_SIZE_BIT 5

- bb1.n FPPT_SIZE_BIT, TMP2, 2f

- extu TMP3, TMP2, 5<0> /* get FP operation dest reg */

- br.n 3f

- set TMP3, TMP3, 1<5> /* set size=1 -- clear one bit for "float" */

-2: set TMP3, TMP3, 1<6> /* set size=2 -- clear two bit for "double" */

+ bb1.n FPPT_SIZE_BIT, TMP2, 2f

+ extu TMP3, TMP2, 5<0> /* get FP operation dest reg */

+ br.n 3f

+ set TMP3, TMP3, 1<5> /* set size=1 -- clear one bit for "float" */

+2: set TMP3, TMP3, 1<6> /* set size=2 -- clear two bit for "double" */

3: clr TMP, TMP, TMP3 /* clear bit(s) in ssbr. */

4: jmp r1

@@ -1507,102 +1589,102 @@ ASGLOBAL(clear_FPp_ssbr_bit)

/************************************************************************/

ASGLOBAL(clear_dest_ssbr_bit)

- /*

- * There are various cases where an exception can leave the

- * destination register's bit in the SB set.

- * Examples:

- * misaligned or privilege exception on a LD or XMEM

- * DIV or DIVU by zero.

- *

- * I think that if the instruction is LD.D, then two bits must

- * be cleared.

- *

- * Even though there are a number of instructions/exception

- * combinations that could fire this code up, it's only required

- * to be run for the above cases. However, I don't think it'll

- * ever be a problem to run this in other cases (ST instructions,

- * for example), so I don't bother checking. If we had to check

- * for every possible instruction, this code would be much larger.

- *

- * The only checking, then, is to see if it's a LD.D or not.

- *

- * At the moment....

- * r1: return address to calling exception handler

- * TMP : (possibly) revised ssbr

- * TMP2 : free

- * TMP3 : free

- */

- ldcr TMP3, EPSR /* going to check: user or system memory? */

- ldcr TMP2, SXIP /* get the instruction's address */

- bb1.n PSR_SUPERVISOR_MODE_BIT, TMP3, 2f

- clr TMP2, TMP2, 2<0> /* get rid of valid and error bits. */

-1: /* user space load here */

+ /*

+ * There are various cases where an exception can leave the

+ * destination register's bit in the SB set.

+ * Examples:

+ * misaligned or privilege exception on a LD or XMEM

+ * DIV or DIVU by zero.

+ *

+ * I think that if the instruction is LD.D, then two bits must

+ * be cleared.

+ *

+ * Even though there are a number of instructions/exception

+ * combinations that could fire this code up, it's only required

+ * to be run for the above cases. However, I don't think it'll

+ * ever be a problem to run this in other cases (ST instructions,

+ * for example), so I don't bother checking. If we had to check

+ * for every possible instruction, this code would be much larger.

+ *

+ * The only checking, then, is to see if it's a LD.D or not.

+ *

+ * At the moment....

+ * r1: return address to calling exception handler

+ * TMP : (possibly) revised ssbr

+ * TMP2 : free

+ * TMP3 : free

+ */

+ ldcr TMP3, EPSR /* going to check: user or system memory? */

+ ldcr TMP2, SXIP /* get the instruction's address */

+ bb1.n PSR_SUPERVISOR_MODE_BIT, TMP3, 2f

+ clr TMP2, TMP2, 2<0> /* get rid of valid and error bits. */

+1: /* user space load here */

#if ERRATA__XXX_USR

- NOP

- ld.usr TMP2,TMP2, r0 /* get the instruction itself */

- NOP

- br 3f

+ NOP

+ ld.usr TMP2,TMP2, r0 /* get the instruction itself */

+ NOP

+ br 3f

#else

- br.n 3f

- ld.usr TMP2,TMP2, r0 /* get the instruction itself */

+ br.n 3f

+ ld.usr TMP2,TMP2, r0 /* get the instruction itself */

#endif

-2: /* system space load here */

- ld TMP2, TMP2, r0 /* get the instruction itself */

-3: /* now have the instruction..... */

- /*

- * Now see if it's a double load

- * There are three forms of double load [IMM16, scaled, unscaled],

- * which can be checked by matching against two templates:

- * -- 77776666555544443333222211110000 --

- * if (((instruction & 11111100000000000000000000000000) ==

- * 00010000000000000000000000000000) ;;

- * ((instruction & 11111100000000001111110011100000) ==

- * 11110100000000000001000000000000))

- * {

- * It's a load double, so

- * clear two SSBR bits.

- * } else {

- * It's not a load double.

- * Must be a load single, xmem, or st

- * Thus, clear one SSBR bit.

- * }

- */

- /* check the first pattern for ld.d */

- extu TMP3, TMP2, 16<16> /* get the upper 16 bits */

- mask TMP3, TMP3, 0xFC00 /* apply the mask */

- cmp TMP3, TMP3, 0x1000 /* if this is equal, it's a load double */

- bb1 eq, TMP3, misaligned_double

- /* still could be -- check the second pattern for ld.d */

- /* look at the upper 16 bits first */

- extu TMP3, TMP2, 16<16> /* get the upper 16 bits */

- mask TMP3, TMP3, 0xFC00 /* apply the mask */

- cmp TMP3, TMP3, 0xF400 /* if equal, it might be a load double */

- bb1 ne, TMP3, misaligned_single /* not equal, so must be single */

- /* now look at the lower 16 bits */

- extu TMP3, TMP2, 16<0> /* get the lower 16 bits */

- mask TMP3, TMP3, 0xFCE0 /* apply the mask */

- cmp TMP3, TMP3, 0x1000 /* if this is equal, it's a load double */

- bb1 eq, TMP3, misaligned_double

+2: /* system space load here */

+ ld TMP2, TMP2, r0 /* get the instruction itself */

+3: /* now have the instruction..... */

+ /*

+ * Now see if it's a double load

+ * There are three forms of double load [IMM16, scaled, unscaled],

+ * which can be checked by matching against two templates:

+ * -- 77776666555544443333222211110000 --

+ * if (((instruction & 11111100000000000000000000000000) ==

+ * 00010000000000000000000000000000) ;;

+ * ((instruction & 11111100000000001111110011100000) ==

+ * 11110100000000000001000000000000))

+ * {

+ * It's a load double, so

+ * clear two SSBR bits.

+ * } else {

+ * It's not a load double.

+ * Must be a load single, xmem, or st

+ * Thus, clear one SSBR bit.

+ * }

+ */

+ /* check the first pattern for ld.d */

+ extu TMP3, TMP2, 16<16> /* get the upper 16 bits */

+ mask TMP3, TMP3, 0xFC00 /* apply the mask */

+ cmp TMP3, TMP3, 0x1000 /* if this is equal, it's a load double */

+ bb1 eq, TMP3, misaligned_double

+ /* still could be -- check the second pattern for ld.d */

+ /* look at the upper 16 bits first */

+ extu TMP3, TMP2, 16<16> /* get the upper 16 bits */

+ mask TMP3, TMP3, 0xFC00 /* apply the mask */

+ cmp TMP3, TMP3, 0xF400 /* if equal, it might be a load double */

+ bb1 ne, TMP3, misaligned_single /* not equal, so must be single */

+ /* now look at the lower 16 bits */

+ extu TMP3, TMP2, 16<0> /* get the lower 16 bits */

+ mask TMP3, TMP3, 0xFCE0 /* apply the mask */

+ cmp TMP3, TMP3, 0x1000 /* if this is equal, it's a load double */

+ bb1 eq, TMP3, misaligned_double

ASGLOBAL(misaligned_single)

- extu TMP2, TMP2, 5<21> /* get the destination register */

- br.n 1f

- set TMP2, TMP2, 1<5> /* set size=1 */

+ extu TMP2, TMP2, 5<21> /* get the destination register */

+ br.n 1f

+ set TMP2, TMP2, 1<5> /* set size=1 */

ASGLOBAL(misaligned_double)

- extu TMP2, TMP2, 5<21> /* get the destination register */

- set TMP2, TMP2, 1<6> /* set size=2 -- clear two bit for "ld.d" */

+ extu TMP2, TMP2, 5<21> /* get the destination register */

+ set TMP2, TMP2, 1<6> /* set size=2 -- clear two bit for "ld.d" */

-1: jmp.n r1

- clr TMP, TMP, TMP2 /* clear bit(s) in ssbr. */

+1: jmp.n r1

+ clr TMP, TMP, TMP2 /* clear bit(s) in ssbr. */

/************************************************************************/

@@ -1610,256 +1692,256 @@ ASGLOBAL(misaligned_double)

#ifdef M88100

ASGLOBAL(setup_phase_two)

- /***************** REGISTER STATUS BLOCK ***********************\

- * SR0: saved return address to calling exception handler *

- * SR1: saved copy of exception-time register now holding FLAGS *

- * SR2: free *

- * SR3: saved TMP *

- * r1: return address to calling exception handler *

- * TMP: possibly revised SSBR *

- * TMP2: free *

- * TMP3: free *

- * FLAGS: CPU status flags *

- * r31: our exception frame *

- * Valid in the exception frame: *

- * Exception-time r1, r31, FLAGS. *

- * Exception-time TMP2, TMP3. *

- * Exception-time espr, sfip, snip, sxip. *

- * Exception number (EF_VECTOR). *

- * Dmt0 *

- * Other data pipeline control registers, if appropriate. *

- * FPU control registers, if appropriate. *

- * Exception SR3, if appropriate. *

- *************************************************** *

- * immediate goal: *

- * restore the system to the exception-time state (except *

- * SR3 will be OUR stack pointer) so that we may resart the FPU. *

- \***************************************************************/

- /*stcr r1, SR0*/ /* save return address */

- stcr TMP, SSBR /* done with SSBR, TMP now free */

- RESTORE_TMP2 /* done with extra temp regs */

- RESTORE_TMP3 /* done with extra temp regs */

- /* Get the current PSR and modify for the rte to enable the FPU */

+ /***************** REGISTER STATUS BLOCK ***********************\

+ * SR0: saved return address to calling exception handler *

+ * SR1: saved copy of exception-time register now holding FLAGS *

+ * SR2: free *

+ * SR3: saved TMP *

+ * r1: return address to calling exception handler *

+ * TMP: possibly revised SSBR *

+ * TMP2: free *

+ * TMP3: free *

+ * FLAGS: CPU status flags *

+ * r31: our exception frame *

+ * Valid in the exception frame: *

+ * Exception-time r1, r31, FLAGS. *

+ * Exception-time TMP2, TMP3. *

+ * Exception-time espr, sfip, snip, sxip. *

+ * Exception number (EF_VECTOR). *

+ * Dmt0 *

+ * Other data pipeline control registers, if appropriate. *

+ * FPU control registers, if appropriate. *

+ * Exception SR3, if appropriate. *

+ *************************************************** *

+ * immediate goal: *

+ * restore the system to the exception-time state (except *

+ * SR3 will be OUR stack pointer) so that we may resart the FPU. *

+ \***************************************************************/

+ /*stcr r1, SR0*/ /* save return address */

+ stcr TMP, SSBR /* done with SSBR, TMP now free */

+ RESTORE_TMP2 /* done with extra temp regs */

+ RESTORE_TMP3 /* done with extra temp regs */

+ /* Get the current PSR and modify for the rte to enable the FPU */

#if 1

- ldcr TMP, PSR

- clr TMP, TMP, 1<PSR_FPU_DISABLE_BIT> /* enable the FPU */

- clr TMP, TMP, 1<PSR_SHADOW_FREEZE_BIT> /* also enable shadowing */

- stcr TMP, EPSR

- /* the "+2" below is to set the VALID_BIT */

- or.u TMP, r0, hi16(fpu_enable +2)

- or TMP, TMP, lo16(fpu_enable +2)

- stcr TMP, SNIP /* jump to here fpu_enable */

- addu TMP, TMP, 4

- stcr TMP, SFIP /* and then continue after that */

+ ldcr TMP, PSR

+ clr TMP, TMP, 1<PSR_FPU_DISABLE_BIT> /* enable the FPU */

+ clr TMP, TMP, 1<PSR_SHADOW_FREEZE_BIT> /* also enable shadowing */

+ stcr TMP, EPSR

+ /* the "+2" below is to set the VALID_BIT */

+ or.u TMP, r0, hi16(fpu_enable +2)

+ or TMP, TMP, lo16(fpu_enable +2)

+ stcr TMP, SNIP /* jump to here fpu_enable */

+ addu TMP, TMP, 4

+ stcr TMP, SFIP /* and then continue after that */

#else

- ldcr TMP, PSR

- or.u TMP, TMP, 0x8000 /* set supervisor mode */

- and TMP, TMP, 0xfff7 /* also enable shadowing */

- stcr TMP, EPSR

- stcr r0, SXIP /* clear valid bit */

- stcr r0, SNIP /* clear valid bit */

- or.u TMP, r0, hi16(fpu_enable)

- or TMP, TMP, lo16(fpu_enable)

- or TMP, TMP, 0x2 /* set the VALID_BIT and clear Exception bit */

- stcr TMP, SFIP /* jump to here fpu_enable */

+ ldcr TMP, PSR

+ or.u TMP, TMP, 0x8000 /* set supervisor mode */

+ and TMP, TMP, 0xfff7 /* also enable shadowing */

+ stcr TMP, EPSR

+ stcr r0, SXIP /* clear valid bit */

+ stcr r0, SNIP /* clear valid bit */

+ or.u TMP, r0, hi16(fpu_enable)

+ or TMP, TMP, lo16(fpu_enable)

+ or TMP, TMP, 0x2 /* set the VALID_BIT and clear Exception bit */

+ stcr TMP, SFIP /* jump to here fpu_enable */

#endif

setup_phase_two_cont:

- set FLAGS, FLAGS, 1<FLAG_ENABLING_FPU> /* note what we're doing.*/

- xcr FLAGS, FLAGS, SR1

- st r1, r31, REG_OFF(EF_RET) /* save the return address */

- ld r1, r31, GENREG_OFF(1) /* get original r1 */

- xcr TMP, r31, SR3 /* TMP now restored. R31 now saved in SR3 */

- ld r31, r31, GENREG_OFF(31) /* get original r31 */

- /***************** REGISTER STATUS BLOCK ***********************\

- * SR0: current thread *

- * SR1: CPU flags *

- * SR2: free *

- * SR3: pointer to our exception frame (our stack pointer) *

- * r1 through r31: original exception-time values *

- * *

- * Valid in the exception frame: *

- * Exception-time FLAGS. *

- * Exception-time espr, sfip, snip, sxip. *

- * Exception number (EF_VECTOR). *

- * Dmt0 *

- * Other data pipeline control registers, if appropriate. *

- * FPU control registers, if appropriate. *

- * Exception SR3, if appropriate. *

- * Held temporarly in the exception frame: *

- * Return address to the calling excption handler. *

- *************************************************** *

- * immediate goal: *

- * Do an RTE to restart the fpu and jump to "fpu_enable" *

- * Another exception (or exceptions) may be raised in *

- * this, which is why FLAG_ENABLING_FPU is set in SR1. *

- \***************************************************************/

- RTE /* jumps to "fpu_enable" on the next line to enable the FPU. */

+ set FLAGS, FLAGS, 1<FLAG_ENABLING_FPU> /* note what we're doing.*/

+ xcr FLAGS, FLAGS, SR1

+ st r1, r31, REG_OFF(EF_RET) /* save the return address */

+ ld r1, r31, GENREG_OFF(1) /* get original r1 */

+ xcr TMP, r31, SR3 /* TMP now restored. R31 now saved in SR3 */

+ ld r31, r31, GENREG_OFF(31) /* get original r31 */

+ /***************** REGISTER STATUS BLOCK ***********************\

+ * SR0: current thread *

+ * SR1: CPU flags *

+ * SR2: free *

+ * SR3: pointer to our exception frame (our stack pointer) *

+ * r1 through r31: original exception-time values *

+ * *

+ * Valid in the exception frame: *

+ * Exception-time FLAGS. *

+ * Exception-time espr, sfip, snip, sxip. *

+ * Exception number (EF_VECTOR). *

+ * Dmt0 *

+ * Other data pipeline control registers, if appropriate. *

+ * FPU control registers, if appropriate. *

+ * Exception SR3, if appropriate. *

+ * Held temporarly in the exception frame: *

+ * Return address to the calling excption handler. *

+ *************************************************** *

+ * immediate goal: *

+ * Do an RTE to restart the fpu and jump to "fpu_enable" *

+ * Another exception (or exceptions) may be raised in *

+ * this, which is why FLAG_ENABLING_FPU is set in SR1. *

+ \***************************************************************/

+ RTE /* jumps to "fpu_enable" on the next line to enable the FPU. */

ASGLOBAL(fpu_enable)

- FLUSH_PIPELINE

- xcr TMP, TMP, SR3 /* get E.F. pointer */

- st.d r30, TMP, GENREG_OFF(30) /* save previous r30, r31 */

- or r31, TMP, r0 /* transfer E.F. pointer to r31 */

- ld TMP, r31, REG_OFF(EF_SR3) /* get previous SR3; maybe important*/

- /* make sure that the FLAG_ENABLING_FPU bit is off */

- xcr FLAGS,FLAGS,SR1

- clr FLAGS,FLAGS,1<FLAG_ENABLING_FPU>

- xcr FLAGS,FLAGS,SR1

- xcr TMP, TMP, SR3 /* replace TMP, SR3 */

- /* now save all regs to the exception frame. */

- st.d r0 , r31, GENREG_OFF(0)

- st.d r2 , r31, GENREG_OFF(2)

- st.d r4 , r31, GENREG_OFF(4)

- st.d r6 , r31, GENREG_OFF(6)

- st.d r8 , r31, GENREG_OFF(8)

- st.d r10, r31, GENREG_OFF(10)

- st.d r12, r31, GENREG_OFF(12)

- st.d r14, r31, GENREG_OFF(14)

- st.d r16, r31, GENREG_OFF(16)

- st.d r18, r31, GENREG_OFF(18)

- st.d r20, r31, GENREG_OFF(20)

- st.d r22, r31, GENREG_OFF(22)

- st.d r24, r31, GENREG_OFF(24)

- st.d r26, r31, GENREG_OFF(26)

- st.d r28, r31, GENREG_OFF(28)

+ FLUSH_PIPELINE

+ xcr TMP, TMP, SR3 /* get E.F. pointer */

+ st.d r30, TMP, GENREG_OFF(30) /* save previous r30, r31 */

+ or r31, TMP, r0 /* transfer E.F. pointer to r31 */

+ ld TMP, r31, REG_OFF(EF_SR3) /* get previous SR3; maybe important*/

+ /* make sure that the FLAG_ENABLING_FPU bit is off */

+ xcr FLAGS,FLAGS,SR1

+ clr FLAGS,FLAGS,1<FLAG_ENABLING_FPU>

+ xcr FLAGS,FLAGS,SR1

+ xcr TMP, TMP, SR3 /* replace TMP, SR3 */

+ /* now save all regs to the exception frame. */

+ st.d r0 , r31, GENREG_OFF(0)

+ st.d r2 , r31, GENREG_OFF(2)

+ st.d r4 , r31, GENREG_OFF(4)

+ st.d r6 , r31, GENREG_OFF(6)

+ st.d r8 , r31, GENREG_OFF(8)

+ st.d r10, r31, GENREG_OFF(10)

+ st.d r12, r31, GENREG_OFF(12)

+ st.d r14, r31, GENREG_OFF(14)

+ st.d r16, r31, GENREG_OFF(16)

+ st.d r18, r31, GENREG_OFF(18)

+ st.d r20, r31, GENREG_OFF(20)

+ st.d r22, r31, GENREG_OFF(22)

+ st.d r24, r31, GENREG_OFF(24)

+ st.d r26, r31, GENREG_OFF(26)

+ st.d r28, r31, GENREG_OFF(28)

#ifdef JEFF_DEBUG

- /* mark beginning of frame with notable value */

- or.u r20, r0, hi16(0x12345678)

- or r20, r20, lo16(0x12345678)

- st r20, r31, GENREG_OFF(0)

+ /* mark beginning of frame with notable value */

+ or.u r20, r0, hi16(0x12345678)

+ or r20, r20, lo16(0x12345678)

+ st r20, r31, GENREG_OFF(0)

#endif

- /***************** REGISTER STATUS BLOCK ***********************\

- * SR0: current thread *

- * SR1: free *

- * SR2: free *

- * SR3: previous exception-time SR3 *

- * r1: return address to the calling exception handler *

- * r2 through r30: free *

- * r31: our exception frame *

- * *

- * Valid in the exception frame: *

- * Exception-time r0 through r31. *

- * Exception-time FLAGS. *

- * Exception-time espr, sfip, snip, sxip. *

- * Exception number (EF_VECTOR). *

- * Dmt0 *

- * Other data pipeline control registers, if appropriate. *

- * FPU control registers, if appropriate. *

- * Exception SR3, if appropriate. *

- *************************************************** *

- * immediate goal: *

- * Pick up a stack if we came in from user mode. Put *

- * A copy of the exception frame pointer into r30 *

- * bump the stack a doubleword and write the exception *

- * frame pointer. *

- * if not an interrupt exception, *

- * Turn on interrupts and service any outstanding *

- * data access exceptions. *

- * Return to calling exception handler to *

- * service the exception. *

- \***************************************************************/

- /*

- * If it's not the interrupt exception, enable interrupts and

- * take care of any data access exceptions......

- *

+ /***************** REGISTER STATUS BLOCK ***********************\

+ * SR0: current thread *

+ * SR1: free *

+ * SR2: free *

+ * SR3: previous exception-time SR3 *

+ * r1: return address to the calling exception handler *

+ * r2 through r30: free *

+ * r31: our exception frame *

+ * *

+ * Valid in the exception frame: *

+ * Exception-time r0 through r31. *

+ * Exception-time FLAGS. *

+ * Exception-time espr, sfip, snip, sxip. *

+ * Exception number (EF_VECTOR). *

+ * Dmt0 *

+ * Other data pipeline control registers, if appropriate. *

+ * FPU control registers, if appropriate. *

+ * Exception SR3, if appropriate. *

+ *************************************************** *

+ * immediate goal: *

+ * Pick up a stack if we came in from user mode. Put *

+ * A copy of the exception frame pointer into r30 *

+ * bump the stack a doubleword and write the exception *

+ * frame pointer. *

+ * if not an interrupt exception, *

+ * Turn on interrupts and service any outstanding *

+ * data access exceptions. *

+ * Return to calling exception handler to *

+ * service the exception. *

+ \***************************************************************/

+ /*

+ * If it's not the interrupt exception, enable interrupts and

+ * take care of any data access exceptions......

+ */

#if INTSTACK

- * If interrupt exception, switch to interrupt stack if not

- * already there. Else, switch to kernel stack.

+ /*

+ * If interrupt exception, switch to interrupt stack if not

+ * already there. Else, switch to kernel stack.

+ */

#endif

- */

- or r30, r0, r31 /* get a copy of the e.f. pointer */

- ld r2, r31, REG_OFF(EF_EPSR)

- bb1 PSR_SUPERVISOR_MODE_BIT, r2, 1f /* If in kernel mode */

+ or r30, r0, r31 /* get a copy of the e.f. pointer */

+ ld r2, r31, REG_OFF(EF_EPSR)

+ bb1 PSR_SUPERVISOR_MODE_BIT, r2, 1f /* If in kernel mode */

#if INTSTACK

- ld r3, r31, REG_OFF(EF_VECTOR)

- cmp r3, r3, 1 /* is interrupt ? */

- bb0 eq, r3, 2f

- or.u r31, r0, hi16(_intstack_end) /* swith to int stack */

- or r31, r31, lo16(_intstack_end)

- br 3f

+ ld r3, r31, REG_OFF(EF_VECTOR)

+ cmp r3, r3, 1 /* is interrupt ? */

+ bb0 eq, r3, 2f

+ or.u r31, r0, hi16(_intstack_end) /* swith to int stack */

+ or r31, r31, lo16(_intstack_end)

+ br 3f

#endif

- or.u r31, r0, hi16(_kstack)

- ld r31, r31, lo16(_kstack)

- addu r31, r31, USIZE /* point at proper end */

- br 3f

+ or.u r31, r0, hi16(_kstack)

+ ld r31, r31, lo16(_kstack)

+ addu r31, r31, USIZE /* point at proper end */

+ br 3f

#if INTSTACK

- ld r3, r31, REG_OFF(EF_VECTOR)

- cmp r3, r3, 1 /* is interrupt ? */

- bb0 eq, r3, 3f /* no, we will stay on kern stack */

- or.u r31, r0, hi16(_intstack_end) /* swith to int stack */

- or r31, r31, lo16(_intstack_end)

+ ld r3, r31, REG_OFF(EF_VECTOR)

+ cmp r3, r3, 1 /* is interrupt ? */

+ bb0 eq, r3, 3f /* no, we will stay on kern stack */

+ or.u r31, r0, hi16(_intstack_end) /* swith to int stack */

+ or r31, r31, lo16(_intstack_end)

#endif /* INTSTACK */

- /* This label is here for debugging */

+ /* This label is here for debugging */

exception_handler_has_ksp: global exception_handler_has_ksp

-3: /*

- here - r30 holds a pointer to the exception frame.

- r31 is a pointer to the kernel stack/interrupt stack.

- */

- subu r31, r31, 8 /* make some breathing space */

- st r30, r31, 0 /* store frame pointer on the stack */

+3: /*

+ * here - r30 holds a pointer to the exception frame.

+ * r31 is a pointer to the kernel stack/interrupt stack.

+ */

+ subu r31, r31, 8 /* make some breathing space */

+ st r30, r31, 0 /* store frame pointer on the stack */

#if DDB

- st r30, r31, 4 /* store it again for the debugger to recognize */

+ st r30, r31, 4 /* store it again for the debugger to recognize */

#endif /* DDB */

- ld r2, r30, REG_OFF(EF_VECTOR)

- bcnd.n eq0, r2, return_to_calling_exception_handler /* is error */

- ld r14, r30, REG_OFF(EF_RET)

- cmp r3, r2, 1 /* interrupt is exception #1 ;Is an interrupt? */

- bb1.n eq, r3, return_to_calling_exception_handler /* skip if so */

+ ld r2, r30, REG_OFF(EF_VECTOR)

+ bcnd.n eq0, r2, return_to_calling_exception_handler /* is error */

+ ld r14, r30, REG_OFF(EF_RET)

+ cmp r3, r2, 1 /* interrupt is exception #1 ;Is an interrupt? */

+ bb1.n eq, r3, return_to_calling_exception_handler /* skip if so */

#if DDB

- cmp r3, r2, 130 /* DDB break exception */

- bb1.n eq, r3, return_to_calling_exception_handler

- cmp r3, r2, 132 /* DDB entry exception */

- bb1.n eq, r3, return_to_calling_exception_handler

+ cmp r3, r2, 130 /* DDB break exception */

+ bb1.n eq, r3, return_to_calling_exception_handler

+ cmp r3, r2, 132 /* DDB entry exception */

+ bb1.n eq, r3, return_to_calling_exception_handler

#endif

- ldcr r2, PSR

- clr r2, r2, 1<PSR_INTERRUPT_DISABLE_BIT> /* enable interrupts */

- stcr r2, PSR

+ ldcr r2, PSR

+ clr r2, r2, 1<PSR_INTERRUPT_DISABLE_BIT> /* enable interrupts */

+ stcr r2, PSR

#if DDB

- FLUSH_PIPELINE

+ FLUSH_PIPELINE

#endif

- /* service any outstanding data pipeline stuff

- - check dmt0 anything outstanding?*/

+ /* service any outstanding data pipeline stuff

+ - check dmt0 anything outstanding?*/

- ld r3, r30, REG_OFF(EF_DMT0)

- bb0 DMT_VALID_BIT, r3, return_to_calling_exception_handler

+ ld r3, r30, REG_OFF(EF_DMT0)

+ bb0 DMT_VALID_BIT, r3, return_to_calling_exception_handler

-/*

- r30 can be clobbered by calls. So stuff its value into a

- preserved register, say r15. R14 is in use (see return_to_... below).

- */

- or r15, r0, r30

+ /*

+ r30 can be clobbered by calls. So stuff its value into a

+ preserved register, say r15. R14 is in use (see return_to_... below).

+ */

+ or r15, r0, r30

- CALL(_C_LABEL(trap18x), T_DATAFLT, r15)

- CALL(_data_access_emulation, r15, r0)

+ CALL(_C_LABEL(m88100_trap), T_DATAFLT, r15)

+ CALL(_data_access_emulation, r15, r0)

-/* restore it... */

- or r30, r0, r15

+ /* restore it... */

+ or r30, r0, r15

- /* clear the dmt0 word in the E.F */

- st r0, r30, REG_OFF(EF_DMT0)

+ /* clear the dmt0 word in the E.F */

+ st r0, r30, REG_OFF(EF_DMT0)

ASGLOBAL(return_to_calling_exception_handler)

- jmp r14 /* loaded above */

+ jmp r14 /* loaded above */

#endif /* m88100 */

@@ -1873,16 +1955,16 @@ ASGLOBAL(return_to_calling_exception_handler)

ENTRY(proc_trampoline)

- ld r1,r31,0 /* load func */

- ld r2,r31,4 /* load proc pointer */

- jsr.n r1

- subu r31,r31,40 /* create stack space for function */

- addu r31,r31,48 /* stack space above + ksigframe */

- ld r1, r31,0 /* load pc */

- ld r2, r31,4 /* & proc pointer from switch frame */

- jsr.n r1

- addu r31,r31,8

- bsr _panic

+ ld r1,r31,0 /* load func */

+ ld r2,r31,4 /* load proc pointer */

+ jsr.n r1

+ subu r31,r31,40 /* create stack space for function */

+ addu r31,r31,48 /* stack space above + ksigframe */

+ ld r1, r31,0 /* load pc */

+ ld r2, r31,4 /* & proc pointer from switch frame */

+ jsr.n r1

+ addu r31,r31,8

+ bsr _C_LABEL(panic)

* proc_do_uret

@@ -1893,10 +1975,10 @@ ENTRY(proc_trampoline)

ENTRY(proc_do_uret)

- ld r3,r2,P_ADDR /* p->p_addr */

- addu r3,r3,PCB_USER_STATE /* p->p_addr.u_pcb.user_state */

- st r3,r31,0 /* put it on the stack */

- br return_from_exception_handler

+ ld r3,r2,P_ADDR /* p->p_addr */

+ addu r3,r3,PCB_USER_STATE /* p->p_addr.u_pcb.user_state */

+ st r3,r31,0 /* put it on the stack */

+ br return_from_exception_handler

ASGLOBAL(return_from_exception_handler)

GLOBAL(return_from_main)

@@ -1917,30 +1999,29 @@ GLOBAL(return_from_main)

#ifdef M88110

- or.u r2, r0, hi16(_cputyp)

- ld r3, r2, lo16(_cputyp)

+ or.u r2, r0, hi16(_C_LABEL(cputyp))

+ ld r3, r2, lo16(_C_LABEL(cputyp))

cmp r2, r3, CPU_88110

- bb1 eq, r2, m197_return_code

+ bb1 eq, r2, m88110_return_code

#endif

#ifdef M88100

- /* 18x part for return_from_exception_handler() follows... */

#define FPTR r14

ld FPTR, r31, 0 /* grab exception frame pointer */

ld r3, FPTR, REG_OFF(EF_DMT0)

bb0 DMT_VALID_BIT, r3, _check_ast /*[Oh well, nothing to do here] */

#if 1

- /*

- * This might happen for non-interrupts If the user sets DMT0

- * in an exception handler.........

- */

+ /*

+ * This might happen for non-interrupts If the user sets DMT0

+ * in an exception handler.........

+ */

ld r2, FPTR, REG_OFF(EF_VECTOR)

cmp r2, r2, 1 /* interrupt is exception #1 ; Is an interrupt? */

bb1 eq, r2, 1f

or.u r4, r0, hi16(2f)

or r4, r4, lo16(2f)

#if DDB

- CALL(_db_printf, r4, r0)

+ CALL(_C_LABEL(db_printf), r4, r0)

tb0 0, r0, 132

#endif

br 1f

@@ -1950,86 +2031,63 @@ GLOBAL(return_from_main)

text

#endif

- /*

- * If it's the interrupt exception, enable interrupt.

- * Take care of any data access exception...... 90/8/15 add by yama

- */

- /*

- * Is it ever possible to have interrupt exception while EPSR has

- * it disabled? I don't think so.. XXX nivas

- */

+ /*

+ * If it's the interrupt exception, enable interrupt.

+ * Take care of any data access exception...... 90/8/15 add by yama

+ */

+ /*

+ * Is it ever possible to have interrupt exception while EPSR has

+ * it disabled? I don't think so.. XXX nivas

+ */

ld r2, FPTR, REG_OFF(EF_VECTOR)

cmp r2, r2, 1 /* interrupt is exception #1 ; Is an interrupt? */

bb1 ne, r2, 1f /* If not so, skip */

- /* if EPSR has interrupts disabled, skip also */

+ /* if EPSR has interrupts disabled, skip also */

ld r2, FPTR, REG_OFF(EF_EPSR)

- bb1 PSR_INTERRUPT_DISABLE_BIT, r2, 1f /* skip if disabled */

+ bb1 PSR_INTERRUPT_DISABLE_BIT, r2, 1f /* skip if disabled */

ldcr r2, PSR

- clr r2, r2, 1<PSR_INTERRUPT_DISABLE_BIT> /* enable interrupts */

- FLUSH_PIPELINE

+ clr r2, r2, 1<PSR_INTERRUPT_DISABLE_BIT> /* enable interrupts */

+ FLUSH_PIPELINE

stcr r2, PSR

- 1:

+1:

ld r2, FPTR, REG_OFF(EF_DMT0)

bb0 DMT_VALID_BIT, r2, 2f

- /*

- * if there happens to be a data fault that hasn't been serviced yet,

- * go off and service that...

- */

- CALL(_C_LABEL(trap18x), T_DATAFLT, r30)

- CALL(_data_access_emulation, r30, r0) /* really only 2 args */

- /* clear the dmt0 word in the E.F. */

+ /*

+ * if there happens to be a data fault that hasn't been serviced yet,

+ * go off and service that...

+ */

+ CALL(_C_LABEL(m88100_trap), T_DATAFLT, r30)

+ CALL(_C_LABEL(data_access_emulation), r30, r0) /* really only 2 args */

+ /* clear the dmt0 word in the E.F. */

st r0 , FPTR, REG_OFF(EF_DMT0)

- 2:

+2:

br _check_ast

-#endif /* M88100 */

- /* 197 part for return_from_exception_handler() follows... */

+#endif /* m88100 */

#ifdef M88110

-ASLOCAL(m197_return_code)

+ASLOCAL(m88110_return_code)

#define FPTR r14

ld FPTR, r31, 0 /* grab exception frame pointer */

- ld r3, FPTR, REG_OFF(EF_DSR)

- cmp r2, r3, 0x0

- bb1 eq, r2, _check_ast /*[Oh well, nothing to do here] */

-#if 1

- * This might happen for non-interrupts If the user sets DMT0

- * in an exception handler.........

+ * If it's the interrupt exception, enable interrupt.

+ * If it's the data access exception, take care of it.

- ld r2, FPTR, REG_OFF(EF_VECTOR)

- cmp r2, r2, 1 /* interrupt is exception #1 ; Is an interrupt? */

- bb1 eq, r2, 1f

- or.u r4, r0, hi16(2f)

- or r4, r4, lo16(2f)

-#if DDB

- CALL(_db_printf, r4, r0)

- tb0 0, r0, 132

-#endif

- br 1f

- data

-2: string "OOPS: DSR not zero and not interrupt.\n\000"

- align 8

- text

-1:

-#endif

- /*

- * If it's the interrupt exception, enable interrupt.

- * Take care of any data access exception...... 90/8/15 add by yama

- */

- /*

- * Is it ever possible to have interrupt exception while EPSR has

- * it disabled? I don't think so.. XXX nivas

- */

+ /*

+ * Is it ever possible to have interrupt exception while EPSR has

+ * it disabled? I don't think so.. XXX nivas

+ *

+ * On mc88110, you can. The NMI interrupt. aka ABORT. XXX smurph

+ */

ld r2, FPTR, REG_OFF(EF_VECTOR)

- cmp r2, r2, 1 /* interrupt is exception #1 ; Is an interrupt? */

- bb1 ne, r2, 1f /* If not so, skip */

+ cmp r2, r2, 1 /* Is it an interrupt? */

+ bb1 ne, r2, 1f /* If not, skip */

- /* if EPSR has interrupts disabled, skip also */

+ /* if EPSR has interrupts disabled, skip also */

ld r2, FPTR, REG_OFF(EF_EPSR)

bb1 PSR_INTERRUPT_DISABLE_BIT, r2, 1f /* skip if disabled */

ldcr r2, PSR

@@ -2037,18 +2095,21 @@ ASLOCAL(m197_return_code)

FLUSH_PIPELINE

stcr r2, PSR

- ld r2, FPTR, REG_OFF(EF_DSR)

- cmp r3, r2, 0x0

- bb1 eq, r3, 2f

+ br 2f /* temp XXX smurph */

+ ld r2, FPTR, REG_OFF(EF_VECTOR)

+ cmp r2, r2, 3 /* Is it a data access exception? */

+ bb1 ne, r2, 2f /* If not, skip */

- /*

- * if there happens to be a data fault that hasn't been serviced yet,

- * go off and service that...

- */

- CALL(_C_LABEL(trap197), T_DATAFLT, r30)

+ /*

+ * if there happens to be a data fault that hasn't been serviced yet,

+ * go off and service that...

+ */

+ CALL(_C_LABEL(m88110_trap), T_DATAFLT, r30)

- /* clear the dmt0 word in the E.F. */

+ /* clear the dsr word in the E.F. */

st r0, FPTR, REG_OFF(EF_DSR)

+ st r0, FPTR, REG_OFF(EF_DLAR)

+ st r0, FPTR, REG_OFF(EF_DPAR)

#endif /* M88110 */

@@ -2062,18 +2123,18 @@ GLOBAL(check_ast)

ld r2, FPTR, REG_OFF(EF_EPSR) /* get pre-exception PSR */

bb1 PSR_INTERRUPT_DISABLE_BIT, r2, 1f /* skip if ints off */

ld r2, FPTR, REG_OFF(EF_MASK) /* get pre-exception ipl */

- bcnd ne0, r2, 1f /* can't do softint's */

+ bcnd ne0, r2, 1f /* can't do softint's */

subu r31, r31, 32

- bsr.n _setipl

+ bsr.n _C_LABEL(setipl)

or r2,r0,1

/* at ipl 1 now */

addu r31, r31, 32

- bsr _dosoftint

+ bsr _C_LABEL(dosoftint)

/* is this needed? we are going to restore the ipl below XXX nivas */

subu r31, r31, 32

- bsr.n _setipl

- or r2,r0,0 /* ints are enabled */

+ bsr.n _C_LABEL(setipl)

+ or r2,r0,0 /* ints are enabled */

addu r31, r31, 32

/* at ipl 0 now */

@@ -2082,32 +2143,32 @@ GLOBAL(check_ast)

/* should assert here - not in user mode with ints off XXX nivas */

/* get and check want_ast */

- or.u r2, r0, hi16(_want_ast)

- ld r3, r2, lo16(_want_ast)

+ or.u r2, r0, hi16(_C_LABEL(want_ast))

+ ld r3, r2, lo16(_C_LABEL(want_ast))

bcnd eq0, r3, no_ast

* trap(AST,...) will service ast's.

#ifdef M88110

- or.u r2, r0, hi16(_cputyp)

- ld r3, r2, lo16(_cputyp)

+ or.u r2, r0, hi16(_C_LABEL(cputyp))

+ ld r3, r2, lo16(_C_LABEL(cputyp))

cmp r2, r3, CPU_88110

bb0 eq, r2, 2f

- CALL(_C_LABEL(trap197), T_ASTFLT, FPTR)

+ CALL(_C_LABEL(m88110_trap), T_ASTFLT, FPTR)

br no_ast

#endif

#ifdef M88100

- CALL(_C_LABEL(trap18x), T_ASTFLT, FPTR)

+ CALL(_C_LABEL(m88100_trap), T_ASTFLT, FPTR)

#endif

#if 0

/* assert that ipl is 0; if going back to user, it should be 0 */

- bsr _getipl

+ bsr _C_LABEL(getipl)

bcnd eq0, r2, 3f

- bsr _panic

+ bsr _C_LABEL(panic)

#endif

@@ -2121,7 +2182,7 @@ ASGLOBAL(no_ast)

/* now ready to return....*/

ld r2, FPTR, REG_OFF(EF_MASK) /* get pre-exception ipl */

- bsr.n _setipl

+ bsr.n _C_LABEL(setipl)

subu r31, r31, 40

addu r31, r31, 40

@@ -2155,17 +2216,17 @@ ASGLOBAL(no_ast)

/* reload the control regs*/

#ifdef M88110

- or.u r1, r0, hi16(_cputyp)

- ld r1, r1, lo16(_cputyp)

+ or.u r1, r0, hi16(_C_LABEL(cputyp))

+ ld r30, r1, lo16(_C_LABEL(cputyp))

cmp r1, r30, CPU_88110

bb1 ne, r1, 1f

/* mc88110 needs the EXIP */

- ld r30, r31, REG_OFF(EF_SNIP)

- ld r1, r31, REG_OFF(EF_SXIP)

- stcr r30, SNIP

- stcr r1, SXIP

+ ld r30, r31, REG_OFF(EF_ENIP)

+ ld r1, r31, REG_OFF(EF_EXIP)

+ stcr r30, ENIP

+ stcr r1, EXIP

br 2f

-1:

+1:

#endif

st r0, r31, REG_OFF(EF_IPFSR)

st r0, r31, REG_OFF(EF_DPFSR)

@@ -2203,163 +2264,167 @@ ASGLOBAL(return_from_exception)

/*#########################################################################*/

/* unknown exception handler */

-GLOBAL(m197_unknown_handler)

- PREP2("unknown", 0, DEBUG_UNKNOWN_BIT, No_SSBR_Stuff, No_Precheck)

- CALL(_C_LABEL(trap197), T_UNKNOWNFLT, r30)

- DONE(DEBUG_UNKNOWN_BIT)

+GLOBAL(m88110_unknown_handler)

+ PREP2("unknown", 0, DEBUG_UNKNOWN_BIT, No_SSBR_Stuff, No_Precheck)

+ CALL(_C_LABEL(m88110_trap), T_UNKNOWNFLT, r30)

+ DONE(DEBUG_UNKNOWN_BIT)

/* interrupt exception handler */

-GLOBAL(m197_interrupt_handler)

- PREP2("interrupt", 1, DEBUG_INTERRUPT_BIT, No_SSBR_Stuff, No_Precheck)

- CALL(_sbc_ext_int, 1, r30)

- DONE(DEBUG_INTERRUPT_BIT)

+GLOBAL(m88110_interrupt_handler)

+ PREP2("interrupt", 1, DEBUG_INTERRUPT_BIT, No_SSBR_Stuff, No_Precheck)

+ CALL(_C_LABEL(m88110_trap), T_INT, r30)

+ DONE(DEBUG_INTERRUPT_BIT)

/* instruction access exception handler */

-GLOBAL(m197_instruction_access_handler)

- PREP2("inst", 2, DEBUG_INSTRUCTION_BIT, No_SSBR_Stuff, No_Precheck)

- CALL(_C_LABEL(trap197), T_INSTFLT, r30)

- DONE(DEBUG_INSTRUCTION_BIT)

+GLOBAL(m88110_instruction_access_handler)

+ PREP2("inst", 2, DEBUG_INSTRUCTION_BIT, No_SSBR_Stuff, No_Precheck)

+ CALL(_C_LABEL(m88110_trap), T_INSTFLT, r30)

+ DONE(DEBUG_INSTRUCTION_BIT)

* data access exception handler --

* See badaddr() below for info about Data_Precheck.

-GLOBAL(m197_data_exception_handler)

- PREP2("data", 3, DEBUG_DATA_BIT, No_SSBR_Stuff, M197_Data_Precheck)

- DONE(DEBUG_DATA_BIT)

+GLOBAL(m88110_data_exception_handler)

+ PREP2("data", 3, DEBUG_DATA_BIT, No_SSBR_Stuff, M88110_Data_Precheck)

+ CALL(_C_LABEL(m88110_trap), T_DATAFLT, r30)

+ DONE(DEBUG_DATA_BIT)

/* misaligned access exception handler */

-GLOBAL(m197_misaligned_handler)

- PREP2("misalign", 4, DEBUG_MISALIGN_BIT, No_SSBR_Stuff, No_Precheck)

- CALL(_C_LABEL(trap197), T_MISALGNFLT, r30)

- DONE(DEBUG_MISALIGN_BIT)

+GLOBAL(m88110_misaligned_handler)

+ PREP2("misalign", 4, DEBUG_MISALIGN_BIT, No_SSBR_Stuff, No_Precheck)

+ CALL(_C_LABEL(m88110_trap), T_MISALGNFLT, r30)

+ DONE(DEBUG_MISALIGN_BIT)

/* unimplemented opcode exception handler */

-GLOBAL(m197_unimplemented_handler)

- PREP2("unimp", 5, DEBUG_UNIMPLEMENTED_BIT, No_SSBR_Stuff, No_Precheck)

- CALL(_C_LABEL(trap197), T_ILLFLT, r30)

- DONE(DEBUG_UNIMPLEMENTED_BIT)

+GLOBAL(m88110_unimplemented_handler)

+ PREP2("unimp", 5, DEBUG_UNIMPLEMENTED_BIT, No_SSBR_Stuff, No_Precheck)

+ CALL(_C_LABEL(m88110_trap), T_ILLFLT, r30)

+ DONE(DEBUG_UNIMPLEMENTED_BIT)

/* privilege exception handler */

-GLOBAL(m197_privilege_handler)

- PREP2("privilege", 6, DEBUG_PRIVILEGE_BIT, No_SSBR_Stuff, No_Precheck)

- CALL(_C_LABEL(trap197), T_PRIVINFLT, r30)

- DONE(DEBUG_PRIVILEGE_BIT)

+GLOBAL(m88110_privilege_handler)

+ PREP2("privilege", 6, DEBUG_PRIVILEGE_BIT, No_SSBR_Stuff, No_Precheck)

+ CALL(_C_LABEL(m88110_trap), T_PRIVINFLT, r30)

+ DONE(DEBUG_PRIVILEGE_BIT)

* I'm not sure what the trap(T_BNDFLT,...) does, but it doesn't send

* a signal to the process...

-GLOBAL(m197_bounds_handler)

- PREP2("bounds", 7, DEBUG_BOUNDS_BIT, No_SSBR_Stuff, No_Precheck)

- CALL(_C_LABEL(trap197), T_BNDFLT, r30)

- DONE(DEBUG_BOUNDS_BIT)

+GLOBAL(m88110_bounds_handler)

+ PREP2("bounds", 7, DEBUG_BOUNDS_BIT, No_SSBR_Stuff, No_Precheck)

+ CALL(_C_LABEL(m88110_trap), T_BNDFLT, r30)

+ DONE(DEBUG_BOUNDS_BIT)

/* integer divide-by-zero exception handler */

-GLOBAL(m197_divide_handler)

- PREP2("divide", 8, DEBUG_DIVIDE_BIT, No_SSBR_Stuff, No_Precheck)

- CALL(_C_LABEL(trap197), T_ZERODIV, r30)

- DONE(DEBUG_DIVIDE_BIT)

+GLOBAL(m88110_divide_handler)

+ PREP2("divide", 8, DEBUG_DIVIDE_BIT, No_SSBR_Stuff, No_Precheck)

+ CALL(_C_LABEL(m88110_trap), T_ZERODIV, r30)

+ DONE(DEBUG_DIVIDE_BIT)

/* integer overflow exception handelr */

-GLOBAL(m197_overflow_handler)

- PREP2("overflow", 9, DEBUG_OVERFLOW_BIT, No_SSBR_Stuff, No_Precheck)

- CALL(_C_LABEL(trap197), T_OVFFLT, r30)

- DONE(DEBUG_OVERFLOW_BIT)

+GLOBAL(m88110_overflow_handler)

+ PREP2("overflow", 9, DEBUG_OVERFLOW_BIT, No_SSBR_Stuff, No_Precheck)

+ CALL(_C_LABEL(m88110_trap), T_OVFFLT, r30)

+ DONE(DEBUG_OVERFLOW_BIT)

/* Floating-point precise handler */

-GLOBAL(m197_fp_precise_handler)

- PREP2("FPU precise", 114, DEBUG_FPp_BIT, No_SSBR_Stuff, No_Precheck)

- CALL(_m88110_Xfp_precise, r0, r30) /* call fp_precise(??, exception_frame)*/

- DONE(DEBUG_FPp_BIT)

+GLOBAL(m88110_fp_precise_handler)

+ PREP2("FPU precise", 114, DEBUG_FPp_BIT, No_SSBR_Stuff, No_Precheck)

+ CALL(_m88110_Xfp_precise, r0, r30) /* call fp_precise(??, exception_frame)*/

+ DONE(DEBUG_FPp_BIT)

-/* MVME197 non-maskable interrupt handler */

-GLOBAL(m197_nonmaskable)

- PREP2("MVME197 non-mask", 11, DEBUG_NON_MASK_BIT, No_SSBR_Stuff, No_Precheck)

- CALL(_C_LABEL(trap197), T_NON_MASK, r30)

- DONE(DEBUG_NON_MASK_BIT)

+/* MVME197 non-maskable interrupt handler (ABORT button) */

+GLOBAL(m88110_nonmaskable)

+ PREP2("MVME197 non-mask", 11, DEBUG_NON_MASK_BIT, No_SSBR_Stuff, No_Precheck)

+ CALL(_C_LABEL(m88110_trap), T_NON_MASK, r30)

+ DONE(DEBUG_NON_MASK_BIT)

/* MVME197 data MMU read miss handler */

-GLOBAL(m197_data_read_miss)

- PREP2("MVME197 read miss", 12, DEBUG_197_READ_BIT, No_SSBR_Stuff, No_Precheck)

- CALL(_C_LABEL(trap197), T_197_READ, r30)

- DONE(DEBUG_197_READ_BIT)

+GLOBAL(m88110_data_read_miss)

+ PREP2("MVME197 read miss", 12, DEBUG_197_READ_BIT, No_SSBR_Stuff, No_Precheck)

+ CALL(_C_LABEL(m88110_trap), T_197_READ, r30)

+ DONE(DEBUG_197_READ_BIT)

/* MVME197 data MMU write miss handler */

-GLOBAL(m197_data_write_miss)

- PREP2("MVME197 write miss", 13, DEBUG_197_WRITE_BIT, No_SSBR_Stuff, No_Precheck)

- CALL(_C_LABEL(trap197), T_197_WRITE, r30)

- DONE(DEBUG_197_WRITE_BIT)

+GLOBAL(m88110_data_write_miss)

+ PREP2("MVME197 write miss", 13, DEBUG_197_WRITE_BIT, No_SSBR_Stuff, No_Precheck)

+ CALL(_C_LABEL(m88110_trap), T_197_WRITE, r30)

+ DONE(DEBUG_197_WRITE_BIT)

/* MVME197 inst MMU ATC miss handler */

-GLOBAL(m197_inst_atc_miss)

- PREP2("MVME197 inst miss", 14, DEBUG_197_INST_BIT, No_SSBR_Stuff, No_Precheck)

- CALL(_C_LABEL(trap197), T_197_INST, r30)

- DONE(DEBUG_197_INST_BIT)

+GLOBAL(m88110_inst_atc_miss)

+ PREP2("MVME197 inst miss", 14, DEBUG_197_INST_BIT, No_SSBR_Stuff, No_Precheck)

+ CALL(_C_LABEL(m88110_trap), T_197_INST, r30)

+ DONE(DEBUG_197_INST_BIT)

/* All standard system calls. */

-GLOBAL(m197_syscall_handler)

- PREP2("syscall", 128, DEBUG_SYSCALL_BIT, No_SSBR_Stuff, No_Precheck)

- ld r13, r30, GENREG_OFF(13)

- CALL(_m197_syscall, r13, r30) /* system call no. is in r13 */

- DONE(DEBUG_SYSCALL_BIT)

+GLOBAL(m88110_syscall_handler)

+ PREP2("syscall", 128, DEBUG_SYSCALL_BIT, No_SSBR_Stuff, No_Precheck)

+ ld r13, r30, GENREG_OFF(13)

+ CALL(_m88110_syscall, r13, r30) /* system call no. is in r13 */

+ DONE(DEBUG_SYSCALL_BIT)

/* trap 496 comes here */

-GLOBAL(m197_bugtrap)

- PREP2("bugsyscall", 496, DEBUG_BUGCALL_BIT, No_SSBR_Stuff, No_Precheck)

- ld r9, r30, GENREG_OFF(9)

- CALL(_bugsyscall, r9, r30) /* system call no. is in r9 */

- DONE(DEBUG_SYSCALL_BIT)

-GLOBAL(m197_sigsys)

- PREP2("sigsys", 0, DEBUG_SIGSYS_BIT, No_SSBR_Stuff, No_Precheck)

- CALL(_C_LABEL(trap197), T_SIGSYS, r30)

- DONE(DEBUG_SIGSYS_BIT)

-GLOBAL(m197_sigtrap)

- PREP2("sigtrap", 0, DEBUG_SIGTRAP_BIT, No_SSBR_Stuff, No_Precheck)

- CALL(_C_LABEL(trap197), T_SIGTRAP, r30)

- DONE(DEBUG_SIGTRAP_BIT)

-GLOBAL(m197_stepbpt)

- PREP2("sigtrap", 0, DEBUG_SIGTRAP_BIT, No_SSBR_Stuff, No_Precheck)

- CALL(_C_LABEL(trap197), T_STEPBPT, r30)

- DONE(DEBUG_SIGTRAP_BIT)

-GLOBAL(m197_userbpt)

- PREP2("sigtrap", 0, DEBUG_SIGTRAP_BIT, No_SSBR_Stuff, No_Precheck)

- CALL(_C_LABEL(trap197), T_USERBPT, r30)

- DONE(DEBUG_SIGTRAP_BIT)

+GLOBAL(m88110_bugtrap)

+ PREP2("bugsyscall", 496, DEBUG_BUGCALL_BIT, No_SSBR_Stuff, No_Precheck)

+ ld r9, r30, GENREG_OFF(9)

+ CALL(_bugsyscall, r9, r30) /* system call no. is in r9 */

+ DONE(DEBUG_BUGCALL_BIT)

+GLOBAL(m88110_sigsys)

+ PREP2("sigsys", 0, DEBUG_SIGSYS_BIT, No_SSBR_Stuff, No_Precheck)

+ CALL(_C_LABEL(m88110_trap), T_SIGSYS, r30)

+ DONE(DEBUG_SIGSYS_BIT)

+GLOBAL(m88110_sigtrap)

+ PREP2("sigtrap", 0, DEBUG_SIGTRAP_BIT, No_SSBR_Stuff, No_Precheck)

+ CALL(_C_LABEL(m88110_trap), T_SIGTRAP, r30)

+ DONE(DEBUG_SIGTRAP_BIT)

+GLOBAL(m88110_stepbpt)

+ PREP2("sigtrap", 0, DEBUG_SIGTRAP_BIT, No_SSBR_Stuff, No_Precheck)

+ CALL(_C_LABEL(m88110_trap), T_STEPBPT, r30)

+ DONE(DEBUG_SIGTRAP_BIT)

+GLOBAL(m88110_userbpt)

+ PREP2("sigtrap", 0, DEBUG_SIGTRAP_BIT, No_SSBR_Stuff, No_Precheck)

+ CALL(_C_LABEL(m88110_trap), T_USERBPT, r30)

+ DONE(DEBUG_SIGTRAP_BIT)

#if DDB

- GLOBAL(m197_break)

- PREP2("break", 130, DEBUG_BREAK_BIT, No_SSBR_Stuff, No_Precheck)

- CALL(_C_LABEL(trap197), T_KDB_BREAK, r30)

- DONE(DEBUG_BREAK_BIT)

- GLOBAL(m197_trace)

- PREP2("trace", 131, DEBUG_TRACE_BIT, No_SSBR_Stuff, No_Precheck)

- CALL(_C_LABEL(trap197), T_KDB_TRACE, r30)

- DONE(DEBUG_TRACE_BIT)

- GLOBAL(m197_entry)

- PREP2("kdb", 132, DEBUG_KDB_BIT, No_SSBR_Stuff, No_Precheck)

- CALL(_C_LABEL(trap197), T_KDB_ENTRY, r30)

- DONE(DEBUG_KDB_BIT)

+GLOBAL(m88110_break)

+ PREP2("break", 130, DEBUG_BREAK_BIT, No_SSBR_Stuff, No_Precheck)

+ CALL(_C_LABEL(m88110_trap), T_KDB_BREAK, r30)

+ DONE(DEBUG_BREAK_BIT)

+GLOBAL(m88110_trace)

+ PREP2("trace", 131, DEBUG_TRACE_BIT, No_SSBR_Stuff, No_Precheck)

+ CALL(_C_LABEL(m88110_trap), T_KDB_TRACE, r30)

+ DONE(DEBUG_TRACE_BIT)

+GLOBAL(m88110_entry)

+ PREP2("kdb", 132, DEBUG_KDB_BIT, No_SSBR_Stuff, No_Precheck)

+ CALL(_C_LABEL(m88110_trap), T_KDB_ENTRY, r30)

+ DONE(DEBUG_KDB_BIT)

#else /* else not DDB */

- GLOBAL(m197_break)

- PREP2("break", 130, DEBUG_BREAK_BIT, No_SSBR_Stuff, No_Precheck)

- CALL(_C_LABEL(trap197), T_UNKNOWNFLT, r30)

- DONE(DEBUG_BREAK_BIT)

- GLOBAL(m197_trace)

- PREP2("trace", 131, DEBUG_TRACE_BIT, No_SSBR_Stuff, No_Precheck)

- CALL(_C_LABEL(trap197), T_UNKNOWNFLT, r30)

- DONE(DEBUG_TRACE_BIT)

- GLOBAL(m197_entry)

- PREP2("unknown", 132, DEBUG_UNKNOWN_BIT, No_SSBR_Stuff, No_Precheck)

- CALL(_C_LABEL(trap197), T_UNKNOWNFLT, r30)

- DONE(DEBUG_KDB_BIT)

+GLOBAL(m88110_break)

+ PREP2("break", 130, DEBUG_BREAK_BIT, No_SSBR_Stuff, No_Precheck)

+ CALL(_C_LABEL(m88110_trap), T_UNKNOWNFLT, r30)

+ DONE(DEBUG_BREAK_BIT)

+GLOBAL(m88110_trace)

+ PREP2("trace", 131, DEBUG_TRACE_BIT, No_SSBR_Stuff, No_Precheck)

+ CALL(_C_LABEL(m88110_trap), T_UNKNOWNFLT, r30)

+ DONE(DEBUG_TRACE_BIT)

+GLOBAL(m88110_entry)

+ PREP2("unknown", 132, DEBUG_UNKNOWN_BIT, No_SSBR_Stuff, No_Precheck)

+ CALL(_C_LABEL(m88110_trap), T_UNKNOWNFLT, r30)

+ DONE(DEBUG_KDB_BIT)

#endif /* DDB */

/*--------------------------------------------------------------------------*/

* The error exception handler.

@@ -2372,7 +2437,33 @@ GLOBAL(m197_userbpt)

* We'll not worry about trashing r26-29 here,

* since they aren't generally used.

-GLOBAL(m197_error_handler)

+GLOBAL(m88110_error_handler)

+ xcr r2, r2, SRX

+ or r2, r0, 10

+ stcr r2, SR0

+ br.n _C_LABEL(m88110_fatal)

+ xcr r2, r2, SRX

+/*

+ * The reset exception handler.

+ * The reset exception is raised when the RST signal is asserted (machine

+ * is reset), the value of VBR is changed after exceptions are enabled,

+ * or when a jmp, br/bsr to addr 0 (accidents do happen :-)

+ *

+ * Upon a real reset, VBR is set to zero (0), so code must be at addr 0

+ * to handle it!!!

+ *

+ * This is totaly different than _error_handler. Shadowing might or

+ * might not be on.

+ * R1-R31 could tell u alot about what happend, so we'll save them.

+ *

+ * We'll not worry about trashing r26-29 here,

+ * since they aren't generally used.

+ */

+GLOBAL(m88110_reset_handler)

+ stcr r0, SR0

+ /* FALL THROUGH */

+GLOBAL(m88110_fatal)

/* pick up the slavestack */

or r26, r0, r31 /* save old stack */

or.u r31, r0, hi16(_intstack_end)

@@ -2386,15 +2477,15 @@ GLOBAL(m197_error_handler)

st r0, r0, r27

br.n 1b

addu r27, r27, 4 /* bump up */

-2: /* stack has been cleared */

+2: /* stack has been cleared */

- /* ensure that stack is 8-byte aligned */

+ /* ensure that stack is 8-byte aligned */

clr r31, r31, 3<0> /* round down to 8-byte boundary */

- /* create exception frame on stack */

+ /* create exception frame on stack */

subu r31, r31, SIZEOF_EF /* r31 now our E.F. */

- /* save old R31 and other R registers */

+ /* save old R31 and other R registers */

st.d r0 , r31, GENREG_OFF(0)

st.d r2 , r31, GENREG_OFF(2)

st.d r4 , r31, GENREG_OFF(4)

@@ -2410,17 +2501,67 @@ GLOBAL(m197_error_handler)

st.d r24, r31, GENREG_OFF(24)

st r30, r31, GENREG_OFF(30)

st r26, r31, GENREG_OFF(31)

+ /* vector is put in SRO (either 0 or 10 at this point) */

+ ldcr r10, SR0

+ st r10, r31, REG_OFF(EF_VECTOR)

+ cmp r10, r10, 0 /* Is it the reset exception? */

+ bb1.n ne, r10, 1f /* If not, skip. */

/* save shadow registers (are OLD if error_handler, though) */

ldcr r10, EPSR

st r10, r31, REG_OFF(EF_EPSR)

- ldcr r10, SXIP

- st r10, r31, REG_OFF(EF_SXIP)

- ldcr r10, SNIP

- st r10, r31, REG_OFF(EF_SNIP)

+ ldcr r10, EXIP

+ st r10, r31, REG_OFF(EF_EXIP)

+ ldcr r10, ENIP

+ st r10, r31, REG_OFF(EF_ENIP)

+ ldcr r10, DSR

+ st r10, r31, REG_OFF(EF_DSR)

+ ldcr r10, DLAR

+ st r10, r31, REG_OFF(EF_DLAR)

+ ldcr r10, DPAR

+ st r10, r31, REG_OFF(EF_DPAR)

+ ldcr r10, ISR

+ st r10, r31, REG_OFF(EF_ISR)

+ ldcr r10, ILAR

+ st r10, r31, REG_OFF(EF_ILAR)

+ ldcr r10, IPAR

+ st r10, r31, REG_OFF(EF_IPAR)

ldcr r10, SR1

+ br.n 2f

st r10, r31, REG_OFF(EF_MODE)

+1:

+ /* retrieve saved shadow registers for error_handler, though) */

+ or.u r30, r0, hi16(_save_frame)

+ or r30, r30, lo16(_save_frame)

+ ld r10, r30, REG_OFF(EF_EPSR)

+ st r10, r31, REG_OFF(EF_EPSR)

+ ld r10, r30, REG_OFF(EF_EXIP)

+ st r10, r31, REG_OFF(EF_ENIP)

+ ld r10, r30, REG_OFF(EF_DSR)

+ st r10, r31, REG_OFF(EF_DSR)

+ ld r10, r30, REG_OFF(EF_DLAR)

+ st r10, r31, REG_OFF(EF_DLAR)

+ ld r10, r30, REG_OFF(EF_DPAR)

+ st r10, r31, REG_OFF(EF_DPAR)

+ ld r10, r30, REG_OFF(EF_ISR)

+ st r10, r31, REG_OFF(EF_ISR)

+ ld r10, r30, REG_OFF(EF_ILAR)

+ st r10, r31, REG_OFF(EF_ILAR)

+ ld r10, r30, REG_OFF(EF_IPAR)

+ st r10, r31, REG_OFF(EF_IPAR)

+ ld r10, r30, REG_OFF(EF_ISAP)

+ st r10, r31, REG_OFF(EF_ISAP)

+ ld r10, r30, REG_OFF(EF_DSAP)

+ st r10, r31, REG_OFF(EF_DSAP)

+ ld r10, r30, REG_OFF(EF_IUAP)

+ st r10, r31, REG_OFF(EF_IUAP)

+ ld r10, r30, REG_OFF(EF_DUAP)

+ st r10, r31, REG_OFF(EF_DUAP)

+ ldcr r10, SR1

+ st r10, r31, REG_OFF(EF_MODE)

+2:

/* shove sr2 into EF_FPLS1 */

ldcr r10, SR2

st r10, r31, REG_OFF(EF_FPLS1)

@@ -2429,8 +2570,6 @@ GLOBAL(m197_error_handler)

ldcr r10, SR3

st r10, r31, REG_OFF(EF_FPHS2)

- /* error vector is zippo numero el'zeroooo */

- st r0, r31, REG_OFF(EF_VECTOR)

* Cheap way to enable FPU and start shadowing again.

@@ -2452,8 +2591,8 @@ GLOBAL(m197_error_handler)

or r20, r20, lo16(0x87654321)

st r20, r31, 0x04

st r20, r31, 0x00

- CALL(_error_fault, r30, r30)

+ CALL(_error_fatal, r30, r30)

/* TURN INTERUPTS back on */

ldcr r1, PSR

@@ -2461,548 +2600,472 @@ GLOBAL(m197_error_handler)

stcr r1, PSR

FLUSH_PIPELINE

-ASGLOBAL(m197_error_loop)

- bsr m197_error_loop

+ASGLOBAL(m88110_error_loop)

+ bsr m88110_error_loop

/* never returns*/

-/*

- * The reset exception handler.

- * The reset exception is raised when the RST signal is asserted (machine

- * is reset), the value of VBR is changed after exceptions are enabled,

- * or when a jmp, br/bsr to addr 0 (accidents do happen :-)

- *

- * To tell the difference, you should check the value of r1 and the valid

- * bit of SXIP.

- *

- * Upon a real reset, VBR is set to zero (0), so code must be at addr 0

- * to handle it!!!

- *

- * This is totaly different than _error_handler. Shadowing might or

- * might not be on.

- * R1-R31 could tell u alot about what happend, so we'll save them.

- *

- * We'll not worry about trashing r26-29 here,

- * since they aren't generally used.

- */

-GLOBAL(m197_reset_handler)

- /* pick up the slavestack */

- or r26, r0, r31 /* save old stack */

- or.u r31, r0, hi16(_intstack_end)

- or r31, r31, lo16(_intstack_end)

- /* zero the stack, so we'll know what we're lookin' at */

- or.u r27, r0, hi16(_intstack)

- or r27, r27, lo16(_intstack)

-1: cmp r28, r27, r31

- bb1 ge, r28, 2f /* branch if at the end of the stack */

- st r0, r0, r27

- br.n 1b

- addu r27, r27, 4 /* bump up */

-2: /* stack has been cleared */

- /* ensure that stack is 8-byte aligned */

- clr r31, r31, 3<0> /* round down to 8-byte boundary */

- /* create exception frame on stack */

- subu r31, r31, SIZEOF_EF /* r31 now our E.F. */

- /* save old R31 and other R registers */

- st.d r0 , r31, GENREG_OFF(0)

- st.d r2 , r31, GENREG_OFF(2)

- st.d r4 , r31, GENREG_OFF(4)

- st.d r6 , r31, GENREG_OFF(6)

- st.d r8 , r31, GENREG_OFF(8)

- st.d r10, r31, GENREG_OFF(10)

- st.d r12, r31, GENREG_OFF(12)

- st.d r14, r31, GENREG_OFF(14)

- st.d r16, r31, GENREG_OFF(16)

- st.d r18, r31, GENREG_OFF(18)

- st.d r20, r31, GENREG_OFF(20)

- st.d r22, r31, GENREG_OFF(22)

- st.d r24, r31, GENREG_OFF(24)

- st r30, r31, GENREG_OFF(30)

- st r26, r31, GENREG_OFF(31)

- /* save shadow registers */

- ldcr r10, EPSR

- st r10, r31, REG_OFF(EF_EPSR)

- ldcr r10, SXIP

- st r10, r31, REG_OFF(EF_SXIP)

- ldcr r10, SNIP

- st r10, r31, REG_OFF(EF_SNIP)

- ldcr r10, SR1

- st r10, r31, REG_OFF(EF_MODE)

- /* shove sr2 into EF_FPLS1 */

- ldcr r10, SR2

- st r10, r31, REG_OFF(EF_FPLS1)

- /* shove sr3 into EF_FPHS2 */

- ldcr r10, SR3

- st r10, r31, REG_OFF(EF_FPHS2)

- /* error vector is zippo numero el'zeroooo */

- st r0, r31, REG_OFF(EF_VECTOR)

+ASGLOBAL(m88110_setup_phase_one)

+ /***************** REGISTER STATUS BLOCK ***********************\

+ * SR0: current thread (if any, null if not) *

+ * SR1: saved copy of exception-time register now holding FLAGS *

+ * SR2: saved copy of exception-time r1 *

+ * SR3: must be preserved .. may be the exception-time stack *

+ * r1: return address to calling exception handler *

+ * FLAGS: CPU status flags *

+ *************************************************** *

+ * immediate goal: *

+ * Decide where we're going to put the exception frame. *

+ * Might be at the end of R31, SR3, or the thread's *

+ * pcb. *

+ \***************************************************************/

+ /* Check if we are coming in from a FPU restart exception.

+ If so, the pcb will be in SR3 */

+ NOP

+ xcr r1, r1, SR2

+ NOP

+ bb1 FLAG_ENABLING_FPU, FLAGS, m88110_use_SR3_pcb

+ /* are we coming in from user mode? If so, pick up process pcb */

+ bb0 FLAG_FROM_KERNEL, FLAGS, m88110_pickup_stack

+ /* Interrupt in kernel mode, not FPU restart */

+ASGLOBAL(m88110_already_on_kernel_stack)

+ /***************** REGISTER STATUS BLOCK ***********************\

+ * SR0: current thread (if any, null if not) *

+ * SR1: saved copy of exception-time register now holding FLAGS *

+ * SR2: return address to the calling exception handler *

+ * SR3: must be preserved; may be important for other exceptions *

+ * FLAGS: CPU status flags *

+ *************************************************** *

+ * immediate goal: *

+ * We're already on the kernel stack, but not having *

+ * needed to use SR3. We can just make room on the *

+ * stack (r31) for our exception frame. *

+ \***************************************************************/

+ subu r31, r31, SIZEOF_EF /* r31 now our E.F. */

+ st FLAGS,r31, REG_OFF(EF_FLAGS) /* save flags */

+ st r1, r31, GENREG_OFF(1) /* save prev. r1 (now r1 free)*/

+ ldcr r1, SR3 /* save previous SR3 */

+ st r1, r31, REG_OFF(EF_SR3)

+ addu r1, r31, SIZEOF_EF /* save previous r31 */

+ br.n m88110_have_pcb

+ st r1, r31, GENREG_OFF(31)

+ASGLOBAL(m88110_use_SR3_pcb)

+ /***************** REGISTER STATUS BLOCK ***********************\

+ * SR0: current thread (if any, null if not) *

+ * SR1: saved copy of exception-time register now holding FLAGS *

+ * SR2: return address to the calling exception handler *

+ * SR3: must be preserved; exception-time stack pointer *

+ * FLAGS: CPU status flags *

+ *************************************************** *

+ * immediate goal: *

+ * An exception occured while enabling the FPU. Since r31 *

+ * is the user's r31 while enabling the FPU, we had put *

+ * our pcb pointer into SR3, so make room from *

+ * there for our stack pointer. *

+ * We need to check if SR3 is the old stack pointer or the *

+ * pointer off to the user pcb. If it pointing to the user *

+ * pcb, we need to pick up the kernel stack. Otherwise *

+ * we need to allocate a frame upon it. *

+ * We look at the EPSR to see if it was from user mode *

+ * Unfortunately, we have no registers free at the moment *

+ * But we know register 0 in the pcb frame will always be *

+ * zero, so we can use it as scratch storage. *

+ * *

+ \***************************************************************/

+ xcr r2, r2, SRX

+ or r2, r0, 10

+ stcr r2, SR0

+ br.n _C_LABEL(m88110_fatal)

+ xcr r2, r2, SRX

+ /* Testing!!! */

+ xcr r30, r30, SR3 /* r30 = old exception frame */

+ st r1, r30, GENREG_OFF(0) /* free up r1 */

+ ld r1, r30, REG_OFF(EF_EPSR) /* get back the epsr */

+ bb0.n PSR_SUPERVISOR_MODE_BIT, r1, 1f /* if user mode */

+ ld r1, r30, GENREG_OFF(0) /* restore r1 */

+ /* we were in kernel mode - dump frame upon the stack */

+ st r0, r30, GENREG_OFF(0) /* repair old frame */

+ subu r30, r30, SIZEOF_EF /* r30 now our E.F. */

+ st FLAGS,r30, REG_OFF(EF_FLAGS) /* save flags */

+ st r1, r30, GENREG_OFF(1) /* save prev. r1 (now r1 free) */

+ st r31, r30, GENREG_OFF(31) /* save previous r31 */

+ or r31, r0, r30 /* make r31 our pointer. */

+ addu r30, r30, SIZEOF_EF /* r30 now has previous SR3 */

+ st r30, r31, REG_OFF(EF_SR3) /* save previous SR3 */

+ br.n m88110_have_pcb

+ xcr r30, r30, SR3 /* restore r30 */

+1:

+ /* we took an exception while restarting the FPU from user space.

+ * Consequently, we never picked up a stack. Do so now.

+ * R1 is currently free (saved in the exception frame pointed at by

+ * r30) */

+ or.u r1, r0, hi16(_kstack)

+ ld r1, r1, lo16(_kstack)

+ addu r1, r1, USIZE-SIZEOF_EF

+ st FLAGS,r1, REG_OFF(EF_FLAGS) /* store flags */

+ st r31, r1, GENREG_OFF(31) /* store r31 - now free */

+ st r30, r1, REG_OFF(EF_SR3) /* store old SR3 (pcb) */

+ or r31, r1, r0 /* make r31 our exception frame pointer */

+ ld r1, r30, GENREG_OFF(0) /* restore old r1 */

+ st r0, r30, GENREG_OFF(0) /* repair that frame */

+ st r1, r31, GENREG_OFF(1) /* store r1 in its proper place */

+ br.n m88110_have_pcb

+ xcr r30, r30, SR3 /* restore r30 */

+ASGLOBAL(m88110_pickup_stack)

+ /***************** REGISTER STATUS BLOCK ***********************\

+ * SR0: current thread *

+ * SR1: saved copy of exception-time register now holding FLAGS *

+ * SR2: return address to the calling exception handler *

+ * SR3: free *

+ * FLAGS: CPU status flags *

+ *************************************************** *

+ * immediate goal: *

+ * Since we're servicing an exception from user mode, we *

+ * know that SR3 is free. We use it to free up a temp. *

+ * register to be used in getting the thread's pcb *

+ \***************************************************************/

+ stcr r31, SR3 /* save previous r31 */

+ /* switch to the thread's kernel stack. */

+ or.u r31, r0, hi16(_curpcb)

+ ld r31, r31, lo16(_curpcb)

+ addu r31, r31, PCB_USER_STATE /* point to user save area */

+ st FLAGS,r31, REG_OFF(EF_FLAGS) /* save flags */

+ st r1, r31, GENREG_OFF(1) /* save prev. r1 (now r1 free)*/

+ ldcr r1, SR3 /* save previous r31 */

+ st r1, r31, GENREG_OFF(31)

+ /*FALLTHROUGH */

+ASGLOBAL(m88110_have_pcb)

+ /***************** REGISTER STATUS BLOCK ***********************\

+ * SR0: current thread *

+ * SR1: saved copy of exception-time register now holding FLAGS *

+ * SR2: return address to the calling exception handler *

+ * SR3: free *

+ * r1: free *

+ * FLAGS: CPU status flags *

+ * r31: our exception frame *

+ * Valid in the exception frame: *

+ * Exception-time r1, r31, FLAGS. *

+ * Exception SR3, if appropriate. *

+ *************************************************** *

+ * immediate goal: *

+ * Save the shadow registers that need to be saved to *

+ * the exception frame. *

+ \***************************************************************/

+ stcr TMP, SR3 /* free up TMP, TMP2, TMP3 */

+ SAVE_TMP2

+ SAVE_TMP3

+ /* save some exception-time registers to the exception frame */

+ ldcr TMP, EPSR

+ st TMP, r31, REG_OFF(EF_EPSR)

+ ldcr TMP2, EXIP

+ st TMP2, r31, REG_OFF(EF_EXIP)

+ bb0.n 0, TMP2, 1f

+ /* The instruction was NOT in the delay slot, zero ENIP. */

+ st r0, r31, REG_OFF(EF_ENIP)

+ /* The instruction was in the delay slot, save ENIP. */

+ ldcr TMP3, ENIP

+ st TMP3, r31, REG_OFF(EF_ENIP)

+1:

+ /* NO SFIP on mc88110, zero it */

+ st r0, r31, REG_OFF(EF_SFIP)

+ /* get and store the cpu number */

+ extu TMP, FLAGS, FLAG_CPU_FIELD_WIDTH<0> /* TMP = cpu# */

+ st TMP, r31, REG_OFF(EF_CPU)

- * Cheap way to enable FPU and start shadowing again.

+ * Save Pbus fault status register from data and inst CMMU.

- ldcr r10, PSR

- clr r10, r10, 1<PSR_FPU_DISABLE_BIT> /* enable the FPU */

- clr r10, r10, 1<PSR_SHADOW_FREEZE_BIT> /* also enable shadowing */

- stcr r10, PSR /* bang */

- FLUSH_PIPELINE

- /* put pointer to regs into r30... r31 will become a simple stack */

- or r30, r31, r0

- subu r31, r31, 0x10 /* make some breathing space */

- st r30, r31, 0x0c /* store frame pointer on the st */

- st r30, r31, 0x08 /* store again for the debugger to recognize */

- or.u r20, r0, hi16(0x87654321)

- or r20, r20, lo16(0x87654321)

- st r20, r31, 0x04

- st r20, r31, 0x00

- CALL(_error_reset, r30, r30)

- /* TURN INTERUPTS back on */

- ldcr r1, PSR

- clr r1, r1, 1<PSR_INTERRUPT_DISABLE_BIT>

- stcr r1, PSR

- FLUSH_PIPELINE

-ASGLOBAL(m197_error_loop2)

- bsr m197_error_loop2

-/* never returns*/

-ASGLOBAL(m197_setup_phase_one)

- /***************** REGISTER STATUS BLOCK ***********************\

- * SR0: current thread (if any, null if not) *

- * SR1: saved copy of exception-time register now holding FLAGS *

- * SR2: saved copy of exception-time r1 *

- * SR3: must be preserved .. may be the exception-time stack *

- * r1: return address to calling exception handler *

- * FLAGS: CPU status flags *

- *************************************************** *

- * immediate goal: *

- * Decide where we're going to put the exception frame. *

- * Might be at the end of R31, SR3, or the thread's *

- * pcb. *

- \***************************************************************/

- /* Check if we are coming in from a FPU restart exception.

- If so, the pcb will be in SR3 */

- NOP

- xcr r1, r1, SR2

- NOP

- bb1 FLAG_ENABLING_FPU, FLAGS, m197_use_SR3_pcb

- /* are we coming in from user mode? If so, pick up thread pcb */

- bb0 FLAG_FROM_KERNEL, FLAGS, m197_pickup_stack

- /* Interrupt in kernel mode, not FPU restart */

-ASGLOBAL(m197_already_on_kernel_stack)

- /***************** REGISTER STATUS BLOCK ***********************\

- * SR0: current thread (if any, null if not) *

- * SR1: saved copy of exception-time register now holding FLAGS *

- * SR2: return address to the calling exception handler *

- * SR3: must be preserved; may be important for other exceptions *

- * FLAGS: CPU status flags *

- *************************************************** *

- * immediate goal: *

- * We're already on the kernel stack, but not having *

- * needed to use SR3. We can just make room on the *

- * stack (r31) for our exception frame. *

- \***************************************************************/

- subu r31, r31, SIZEOF_EF /* r31 now our E.F. */

- st FLAGS,r31, REG_OFF(EF_FLAGS) /* save flags */

- st r1, r31, GENREG_OFF(1) /* save prev. r1 (now r1 free)*/

- ldcr r1, SR3 /* save previous SR3 */

- st r1, r31, REG_OFF(EF_SR3)

- addu r1, r31, SIZEOF_EF /* save previous r31 */

- br.n m197_have_pcb

- st r1, r31, GENREG_OFF(31)

-ASGLOBAL(m197_use_SR3_pcb)

- /***************** REGISTER STATUS BLOCK ***********************\

- * SR0: current thread (if any, null if not) *

- * SR1: saved copy of exception-time register now holding FLAGS *

- * SR2: return address to the calling exception handler *

- * SR3: must be preserved; exception-time stack pointer *

- * FLAGS: CPU status flags *

- *************************************************** *

- * immediate goal: *

- * An exception occurred while enabling the FPU. Since r31 *

- * is the user's r31 while enabling the FPU, we had put *

- * our pcb pointer into SR3, so make room from *

- * there for our stack pointer. *

- * We need to check if SR3 is the old stack pointer or the *

- * pointer off to the user pcb. If it pointing to the user *

- * pcb, we need to pick up the kernel stack. Otherwise *

- * we need to allocate a frame upon it. *

- * We look at the EPSR to see if it was from user mode *

- * Unfortunately, we have no registers free at the moment *

- * But we know register 0 in the pcb frame will always be *

- * zero, so we can use it as scratch storage. *

- * *

- \***************************************************************/

- xcr r30, r30, SR3 /* r30 = old exception frame */

- st r1, r30, GENREG_OFF(0) /* free up r1 */

- ld r1, r30, REG_OFF(EF_EPSR) /* get back the epsr */

- bb0.n PSR_SUPERVISOR_MODE_BIT, r1, 1f /* if user mode */

- ld r1, r30, GENREG_OFF(0) /* restore r1 */

- /* we were in kernel mode - dump frame upon the stack */

- st r0, r30, GENREG_OFF(0) /* repair old frame */

- subu r30, r30, SIZEOF_EF /* r30 now our E.F. */

- st FLAGS,r30, REG_OFF(EF_FLAGS) /* save flags */

- st r1, r30, GENREG_OFF(1) /* save prev. r1 (now r1 free) */

- st r31, r30, GENREG_OFF(31) /* save previous r31 */

- or r31, r0, r30 /* make r31 our pointer. */

- addu r30, r30, SIZEOF_EF /* r30 now has previous SR3 */

- st r30, r31, REG_OFF(EF_SR3) /* save previous SR3 */

- br.n m197_have_pcb

- xcr r30, r30, SR3 /* restore r30 */

-1:

- /* we took an exception while restarting the FPU from user space.

- * Consequently, we never picked up a stack. Do so now.

- * R1 is currently free (saved in the exception frame pointed at by

- * r30) */

- or.u r1, r0, hi16(_kstack)

- ld r1, r1, lo16(_kstack)

- addu r1, r1, USIZE-SIZEOF_EF

- st FLAGS,r1, REG_OFF(EF_FLAGS) /* store flags */

- st r31, r1, GENREG_OFF(31) /* store r31 - now free */

- st r30, r1, REG_OFF(EF_SR3) /* store old SR3 (pcb) */

- or r31, r1, r0 /* make r31 our exception frame pointer */

- ld r1, r30, GENREG_OFF(0) /* restore old r1 */

- st r0, r30, GENREG_OFF(0) /* repair that frame */

- st r1, r31, GENREG_OFF(1) /* store r1 in its proper place */

- br.n m197_have_pcb

- xcr r30, r30, SR3 /* restore r30 */

-ASGLOBAL(m197_pickup_stack)

- /***************** REGISTER STATUS BLOCK ***********************\

- * SR0: current thread *

- * SR1: saved copy of exception-time register now holding FLAGS *

- * SR2: return address to the calling exception handler *

- * SR3: free *

- * FLAGS: CPU status flags *

- *************************************************** *

- * immediate goal: *

- * Since we're servicing an exception from user mode, we *

- * know that SR3 is free. We use it to free up a temp. *

- * register to be used in getting the thread's pcb *

- \***************************************************************/

- stcr r31, SR3 /* save previous r31 */

- /* switch to the thread's kernel stack. */

- or.u r31, r0, hi16(_curpcb)

- ld r31, r31, lo16(_curpcb)

- addu r31, r31, PCB_USER_STATE /* point to user save area */

- st FLAGS,r31, REG_OFF(EF_FLAGS) /* save flags */

- st r1, r31, GENREG_OFF(1) /* save prev. r1 (now r1 free)*/

- ldcr r1, SR3 /* save previous r31 */

- st r1, r31, GENREG_OFF(31)

- /*FALLTHROUGH */

-ASGLOBAL(m197_have_pcb)

- /***************** REGISTER STATUS BLOCK ***********************\

- * SR0: current thread *

- * SR1: saved copy of exception-time register now holding FLAGS *

- * SR2: return address to the calling exception handler *

- * SR3: free *

- * r1: free *

- * FLAGS: CPU status flags *

- * r31: our exception frame *

- * Valid in the exception frame: *

- * Exception-time r1, r31, FLAGS. *

- * Exception SR3, if appropriate. *

- *************************************************** *

- * immediate goal: *

- * Save the shadow registers that need to be saved to *

- * the exception frame. *

- \***************************************************************/

- stcr TMP, SR3 /* free up TMP, TMP2, TMP3 */

- SAVE_TMP2

- SAVE_TMP3

- /* save some exception-time registers to the exception frame */

- ldcr TMP, EPSR

- st TMP, r31, REG_OFF(EF_EPSR)

- ldcr TMP3, SNIP

- st TMP3, r31, REG_OFF(EF_SNIP)

- /*

- * Save Pbus fault status register from data and inst CMMU.

- */

- ldcr TMP, ISR

- ldcr TMP2, ILAR

- ldcr TMP3, IPAR

- st TMP, r31, REG_OFF(EF_ISR)

- st TMP2, r31, REG_OFF(EF_ILAR)

- st TMP3, r31, REG_OFF(EF_IPAR)

- ldcr TMP, ISAP

- st TMP, r31, REG_OFF(EF_DMT0) /* hack ef! */

- ldcr TMP, DSR

- ldcr TMP2, DLAR

- ldcr TMP3, DPAR

- st TMP, r31, REG_OFF(EF_DSR)

- st TMP2, r31, REG_OFF(EF_DLAR)

- st TMP3, r31, REG_OFF(EF_DPAR)

- ldcr TMP, DSAP

- st TMP, r31, REG_OFF(EF_DMT1) /* hack ef! */

- ldcr TMP2, SXIP

- st TMP2, r31, REG_OFF(EF_SXIP)

- ldcr r1, SR2

- jmp r1 /* return */

+ ldcr TMP, ISR

+ ldcr TMP2, ILAR

+ ldcr TMP3, IPAR

+ st TMP, r31, REG_OFF(EF_ISR)

+ st TMP2, r31, REG_OFF(EF_ILAR)

+ st TMP3, r31, REG_OFF(EF_IPAR)

+ ldcr TMP, ISAP

+ ldcr TMP2, IUAP

+ st TMP, r31, REG_OFF(EF_ISAP)

+ st TMP2, r31, REG_OFF(EF_IUAP)

+ ldcr TMP, DSR

+ ldcr TMP2, DLAR

+ ldcr TMP3, DPAR

+ st TMP, r31, REG_OFF(EF_DSR)

+ st TMP2, r31, REG_OFF(EF_DLAR)

+ st TMP3, r31, REG_OFF(EF_DPAR)

+ ldcr TMP, DSAP

+ ldcr TMP2, DUAP

+ st TMP, r31, REG_OFF(EF_DSAP)

+ st TMP2, r31, REG_OFF(EF_DUAP)

+ ldcr r1, SR2

+ jmp r1 /* return */

/************************************************************************/

-ASGLOBAL(m197_setup_phase_two)

- /***************** REGISTER STATUS BLOCK ***********************\

- * SR0: saved return address to calling exception handler *

- * SR1: saved copy of exception-time register now holding FLAGS *

- * SR2: free *

- * SR3: saved TMP *

- * r1: return address to calling exception handler *

- * TMP: possibly revised SSBR *

- * TMP2: free *

- * TMP3: free *

- * FLAGS: CPU status flags *

- * r31: our exception frame *

- * Valid in the exception frame: *

- * Exception-time r1, r31, FLAGS. *

- * Exception-time TMP2, TMP3. *

- * Exception-time espr, sfip, snip, sxip. *

- * Exception number (EF_VECTOR). *

- * Dmt0 *

- * Other data pipeline control registers, if appropriate. *

- * FPU control registers, if appropriate. *

- * Exception SR3, if appropriate. *

- *************************************************** *

- * immediate goal: *

- * restore the system to the exception-time state (except *

- * SR3 will be OUR stack pointer) so that we may resart the FPU. *

- \***************************************************************/

- /*stcr r1, SR0*/ /* save return address */

- RESTORE_TMP2 /* done with extra temp regs */

- RESTORE_TMP3 /* done with extra temp regs */

- ldcr TMP, PSR

- clr TMP, TMP, 1<PSR_FPU_DISABLE_BIT> /* enable the FPU */

- clr TMP, TMP, 1<PSR_SHADOW_FREEZE_BIT> /* also enable shadowing */

- stcr TMP, EPSR

- or.u TMP, r0, hi16(m197_fpu_enable)

- or TMP, TMP, lo16(m197_fpu_enable)

- stcr TMP, EXIP /* jump to here fpu_enable */

- addu TMP, TMP, 4

- stcr TMP, ENIP /* and then continue after that */

- set FLAGS, FLAGS, 1<FLAG_ENABLING_FPU> /* note what we're doing.*/

- xcr FLAGS, FLAGS, SR1

- st r1, r31, REG_OFF(EF_RET) /* save the return address */

- ld r1, r31, GENREG_OFF(1) /* get original r1 */

- xcr TMP, r31, SR3 /* TMP now restored. R31 now saved in SR3 */

- ld r31, r31, GENREG_OFF(31) /* get original r31 */

- /***************** REGISTER STATUS BLOCK ***********************\

- * SR0: current thread *

- * SR1: CPU flags *

- * SR2: free *

- * SR3: pointer to our exception frame (our stack pointer) *

- * r1 through r31: original exception-time values *

- * *

- * Valid in the exception frame: *

- * Exception-time FLAGS. *

- * Exception-time espr, sfip, snip, sxip. *

- * Exception number (EF_VECTOR). *

- * Dmt0 *

- * Other data pipeline control registers, if appropriate. *

- * FPU control registers, if appropriate. *

- * Exception SR3, if appropriate. *

- * Held temporarly in the exception frame: *

- * Return address to the calling excption handler. *

- *************************************************** *

- * immediate goal: *

- * Do an RTE to restart the fpu and jump to "fpu_enable" *

- * Another exception (or exceptions) may be raised in *

- * this, which is why FLAG_ENABLING_FPU is set in SR1. *

- \***************************************************************/

- NOP

- RTE /* jumps to "fpu_enable" on the next line to enable the FPU. */

-ASGLOBAL(m197_fpu_enable)

- FLUSH_PIPELINE

- xcr TMP, TMP, SR3 /* get E.F. pointer */

- st.d r30, TMP, GENREG_OFF(30) /* save previous r30, r31 */

- or r31, TMP, r0 /* transfer E.F. pointer to r31 */

- ld TMP, r31, REG_OFF(EF_SR3) /* get previous SR3; maybe important*/

- /* make sure that the FLAG_ENABLING_FPU bit is off */

- xcr FLAGS,FLAGS,SR1

- clr FLAGS,FLAGS,1<FLAG_ENABLING_FPU>

- xcr FLAGS,FLAGS,SR1

- xcr TMP, TMP, SR3 /* replace TMP, SR3 */

- /* now save all regs to the exception frame. */

- st.d r0 , r31, GENREG_OFF(0)

- st.d r2 , r31, GENREG_OFF(2)

- st.d r4 , r31, GENREG_OFF(4)

- st.d r6 , r31, GENREG_OFF(6)

- st.d r8 , r31, GENREG_OFF(8)

- st.d r10, r31, GENREG_OFF(10)

- st.d r12, r31, GENREG_OFF(12)

- st.d r14, r31, GENREG_OFF(14)

- st.d r16, r31, GENREG_OFF(16)

- st.d r18, r31, GENREG_OFF(18)

- st.d r20, r31, GENREG_OFF(20)

- st.d r22, r31, GENREG_OFF(22)

- st.d r24, r31, GENREG_OFF(24)

- st.d r26, r31, GENREG_OFF(26)

- st.d r28, r31, GENREG_OFF(28)

+ASGLOBAL(m88110_setup_phase_two)

+ /***************** REGISTER STATUS BLOCK ***********************\

+ * SR0: saved return address to calling exception handler *

+ * SR1: saved copy of exception-time register now holding FLAGS *

+ * SR2: free *

+ * SR3: saved TMP *

+ * r1: return address to calling exception handler *

+ * TMP: possibly revised SSBR *

+ * TMP2: free *

+ * TMP3: free *

+ * FLAGS: CPU status flags *

+ * r31: our exception frame *

+ * Valid in the exception frame: *

+ * Exception-time r1, r31, FLAGS. *

+ * Exception-time TMP2, TMP3. *

+ * Exception-time espr, enip, exip. *

+ * Exception number (EF_VECTOR). *

+ * Dmt0 *

+ * Other data pipeline control registers, if appropriate. *

+ * FPU control registers, if appropriate. *

+ * Exception SR3, if appropriate. *

+ *************************************************** *

+ * immediate goal: *

+ * restore the system to the exception-time state (except *

+ * SR3 will be OUR stack pointer) so that we may resart the FPU. *

+ \***************************************************************/

+ /*stcr r1, SR0*/ /* save return address */

+ RESTORE_TMP2 /* done with extra temp regs */

+ RESTORE_TMP3 /* done with extra temp regs */

+ ldcr TMP, PSR

+ clr TMP, TMP, 1<PSR_FPU_DISABLE_BIT> /* enable the FPU */

+ clr TMP, TMP, 1<PSR_SHADOW_FREEZE_BIT> /* also enable shadowing */

+ stcr TMP, EPSR

+ or.u TMP, r0, hi16(m88110_fpu_enable)

+ or TMP, TMP, lo16(m88110_fpu_enable)

+ stcr TMP, EXIP /* jump to here fpu_enable */

+ addu TMP, TMP, 4

+ stcr TMP, ENIP /* and then continue after that */

+ set FLAGS, FLAGS, 1<FLAG_ENABLING_FPU> /* note what we're doing.*/

+ xcr FLAGS, FLAGS, SR1

+ st r1, r31, REG_OFF(EF_RET) /* save the return address */

+ ld r1, r31, GENREG_OFF(1) /* get original r1 */

+ ldcr TMP, SR3

+ stcr r31, SR3 /* TMP now restored. R31 now saved in SR3 */

+ ld r31, r31, GENREG_OFF(31) /* get original r31 */

+ /***************** REGISTER STATUS BLOCK ***********************\

+ * SR0: current thread *

+ * SR1: CPU flags *

+ * SR2: free *

+ * SR3: pointer to our exception frame (our stack pointer) *

+ * r1 through r31: original exception-time values *

+ * *

+ * Valid in the exception frame: *

+ * Exception-time FLAGS. *

+ * Exception-time espr, sfip, enip, exip. *

+ * Exception number (EF_VECTOR). *

+ * Dmt0 *

+ * Other data pipeline control registers, if appropriate. *

+ * FPU control registers, if appropriate. *

+ * Exception SR3, if appropriate. *

+ * Held temporarly in the exception frame: *

+ * Return address to the calling excption handler. *

+ *************************************************** *

+ * immediate goal: *

+ * Do an RTE to restart the fpu and jump to "fpu_enable" *

+ * Another exception (or exceptions) may be raised in *

+ * this, which is why FLAG_ENABLING_FPU is set in SR1. *

+ \***************************************************************/

+ NOP

+ RTE /* jumps to "fpu_enable" on the next line to enable the FPU. */

+ASGLOBAL(m88110_fpu_enable)

+ FLUSH_PIPELINE

+ /* Now we can handle another exception!!! */

+ /* Now that EFZE is cleared, we can clear these */

+ stcr r0, ISR /* Clear ISR */

+ stcr r0, ILAR /* Clear ILAR */

+ stcr r0, IPAR /* Clear IPAR */

+ stcr r0, DSR /* Clear DSR */

+ stcr r0, DLAR /* Clear DLAR */

+ stcr r0, DPAR /* Clear DPAR */

+ xcr TMP, TMP, SR3 /* get E.F. pointer */

+ st.d r30, TMP, GENREG_OFF(30) /* save previous r30, r31 */

+ or r31, TMP, r0 /* transfer E.F. pointer to r31 */

+ ld TMP, r31, REG_OFF(EF_SR3) /* get previous SR3; maybe important*/

+ /* make sure that the FLAG_ENABLING_FPU bit is off */

+ xcr FLAGS,FLAGS,SR1

+ clr FLAGS,FLAGS,1<FLAG_ENABLING_FPU>

+ xcr FLAGS,FLAGS,SR1

+ xcr TMP, TMP, SR3 /* replace TMP, SR3 */

+ /* now save all regs to the exception frame. */

+ st.d r0 , r31, GENREG_OFF(0)

+ st.d r2 , r31, GENREG_OFF(2)

+ st.d r4 , r31, GENREG_OFF(4)

+ st.d r6 , r31, GENREG_OFF(6)

+ st.d r8 , r31, GENREG_OFF(8)

+ st.d r10, r31, GENREG_OFF(10)

+ st.d r12, r31, GENREG_OFF(12)

+ st.d r14, r31, GENREG_OFF(14)

+ st.d r16, r31, GENREG_OFF(16)

+ st.d r18, r31, GENREG_OFF(18)

+ st.d r20, r31, GENREG_OFF(20)

+ st.d r22, r31, GENREG_OFF(22)

+ st.d r24, r31, GENREG_OFF(24)

+ st.d r26, r31, GENREG_OFF(26)

+ st.d r28, r31, GENREG_OFF(28)

#ifdef JEFF_DEBUG

- /* mark beginning of frame with notable value */

- or.u r20, r0, hi16(0x12345678)

- or r20, r20, lo16(0x12345678)

- st r20, r31, GENREG_OFF(0)

+ /* mark beginning of frame with notable value */

+ or.u r20, r0, hi16(0x12345678)

+ or r20, r20, lo16(0x12345678)

+ st r20, r31, GENREG_OFF(0)

#endif

- /***************** REGISTER STATUS BLOCK ***********************\

- * SR0: current thread *

- * SR1: free *

- * SR2: free *

- * SR3: previous exception-time SR3 *

- * r1: return address to the calling exception handler *

- * r2 through r30: free *

- * r31: our exception frame *

- * *

- * Valid in the exception frame: *

- * Exception-time r0 through r31. *

- * Exception-time FLAGS. *

- * Exception-time espr, sfip, snip, sxip. *

- * Exception number (EF_VECTOR). *

- * Dmt0 *

- * Other data pipeline control registers, if appropriate. *

- * FPU control registers, if appropriate. *

- * Exception SR3, if appropriate. *

- *************************************************** *

- * immediate goal: *

- * Pick up a stack if we came in from user mode. Put *

- * A copy of the exception frame pointer into r30 *

- * bump the stack a doubleword and write the exception *

- * frame pointer. *

- * if not an interrupt exception, *

- * Turn on interrupts and service any outstanding *

- * data access exceptions. *

- * Return to calling exception handler to *

- * service the exception. *

- \***************************************************************/

- /*

- * If it's not the interrupt exception, enable interrupts and

- * take care of any data access exceptions......

- */

- or r30, r0, r31 /* get a copy of the e.f. pointer */

- ld r2, r31, REG_OFF(EF_EPSR)

- bb1 PSR_SUPERVISOR_MODE_BIT, r2, 1f /* If in kernel mode */

+ /***************** REGISTER STATUS BLOCK ***********************\

+ * SR0: current thread *

+ * SR1: free *

+ * SR2: free *

+ * SR3: previous exception-time SR3 *

+ * r1: return address to the calling exception handler *

+ * r2 through r30: free *

+ * r31: our exception frame *

+ * *

+ * Valid in the exception frame: *

+ * Exception-time r0 through r31. *

+ * Exception-time FLAGS. *

+ * Exception-time espr, enip, exip. *

+ * Exception number (EF_VECTOR). *

+ * DSR *

+ * Other data pipeline control registers, if appropriate. *

+ * FPU control registers, if appropriate. *

+ * Exception SR3, if appropriate. *

+ *************************************************** *

+ * immediate goal: *

+ * Pick up a stack if we came in from user mode. Put *

+ * A copy of the exception frame pointer into r30 *

+ * bump the stack a doubleword and write the exception *

+ * frame pointer. *

+ * if not an interrupt exception, *

+ * Turn on interrupts and service any outstanding *

+ * data access exceptions. *

+ * Return to calling exception handler to *

+ * service the exception. *

+ \***************************************************************/

+ /*

+ * If it's not the interrupt exception, enable interrupts and

+ * take care of any data access exceptions......

+ */

+ or r30, r0, r31 /* get a copy of the e.f. pointer */

+ ld r2, r31, REG_OFF(EF_EPSR)

+ bb1 PSR_SUPERVISOR_MODE_BIT, r2, 1f /* If in kernel mode */

#if INTSTACK

* If interrupt exception, switch to interrupt stack if not

* already there. Else, switch to kernel stack.

- ld r3, r31, REG_OFF(EF_VECTOR)

- cmp r3, r3, 1 /* is interrupt ? */

- bb0 eq, r3, 2f

- or.u r31, r0, hi16(_intstack_end) /* swith to int stack */

- or r31, r31, lo16(_intstack_end)

- br 3f

+ ld r3, r31, REG_OFF(EF_VECTOR)

+ cmp r3, r3, 1 /* is interrupt ? */

+ bb0 eq, r3, 2f

+ or.u r31, r0, hi16(_intstack_end) /* swith to int stack */

+ or r31, r31, lo16(_intstack_end)

+ br 3f

#endif

- or.u r31, r0, hi16(_kstack)

- ld r31, r31, lo16(_kstack)

- addu r31, r31, USIZE /* point at proper end */

- br 3f

+ or.u r31, r0, hi16(_kstack)

+ ld r31, r31, lo16(_kstack)

+ addu r31, r31, USIZE /* point at proper end */

+ br 3f

#if INTSTACK

- ld r3, r31, REG_OFF(EF_VECTOR)

- cmp r3, r3, 1 /* is interrupt ? */

- bb0 eq, r3, 3f /* no, we will stay on kern stack */

- or.u r31, r0, hi16(_intstack_end) /* swith to int stack */

- or r31, r31, lo16(_intstack_end)

-#endif /* INTSTACK */

- /* This label is here for debugging */

-m197_exception_handler_has_ksp: global m197_exception_handler_has_ksp

-3: /*

- here - r30 holds a pointer to the exception frame.

- r31 is a pointer to the kernel stack/interrupt stack.

- */

- subu r31, r31, 8 /* make some breathing space */

- st r30, r31, 0 /* store frame pointer on the stack */

+ ld r3, r31, REG_OFF(EF_VECTOR)

+ cmp r3, r3, 1 /* is interrupt ? */

+ bb0 eq, r3, 3f /* no, we will stay on kern stack */

+ or.u r31, r0, hi16(_intstack_end) /* swith to int stack */

+ or r31, r31, lo16(_intstack_end)

+#endif /* INTSTACK */

+ /* This label is here for debugging */

+m88110_exception_handler_has_ksp: global m88110_exception_handler_has_ksp

+3: /*

+ * here - r30 holds a pointer to the exception frame.

+ * r31 is a pointer to the kernel stack/interrupt stack.

+ */

+ subu r31, r31, 8 /* make some breathing space */

+ st r30, r31, 0 /* store frame pointer on the stack */

#if DDB

- st r30, r31, 4 /* store it again for the debugger to recognize */

+ st r30, r31, 4 /* store it again for the debugger to recognize */

#endif /* DDB */

- ld r2, r30, REG_OFF(EF_VECTOR)

- bcnd.n eq0, r2, m197_return_to_calling_exception_handler /* is error */

- ld r14, r30, REG_OFF(EF_RET)

- cmp r3, r2, 1 /* interrupt is exception #1 ;Is an interrupt? */

- bb1.n eq, r3, m197_return_to_calling_exception_handler /* skip if so */

+ ld r2, r30, REG_OFF(EF_VECTOR)

+ bcnd.n eq0, r2, m88110_return_to_calling_exception_handler /* is error */

+ ld r14, r30, REG_OFF(EF_RET) /* load return value XXX!!! */

+ cmp r3, r2, 1 /* interrupt is exception #1 ;Is an interrupt? */

+ bb1.n eq, r3, m88110_return_to_calling_exception_handler /* skip if so */

#if DDB

- cmp r3, r2, 130 /* DDB break exception */

- bb1.n eq, r3, m197_return_to_calling_exception_handler

+ cmp r3, r2, 130 /* DDB break exception */

+ bb1.n eq, r3, m88110_return_to_calling_exception_handler

- cmp r3, r2, 132 /* DDB entry exception */

- bb1.n eq, r3, m197_return_to_calling_exception_handler

+ cmp r3, r2, 132 /* DDB entry exception */

+ bb1.n eq, r3, m88110_return_to_calling_exception_handler

#endif

- ldcr r2, PSR

- clr r2, r2, 1<PSR_INTERRUPT_DISABLE_BIT> /* enable interrupts */

- stcr r2, PSR

+ ldcr r2, PSR

+ clr r2, r2, 1<PSR_INTERRUPT_DISABLE_BIT> /* enable interrupts */

+ stcr r2, PSR

#if DDB

- FLUSH_PIPELINE

+ FLUSH_PIPELINE

#endif

+#if 1 /* test */

+ br m88110_return_to_calling_exception_handler

+#endif

+ /* service any outstanding data pipeline stuff

+ - check dsr... anything outstanding?*/

- /* service any outstanding data pipeline stuff

- - check dsr... anything outstanding?*/

- ld r3, r30, REG_OFF(EF_DSR)

- cmp r3, r3, 0

- bb1 eq, r3, m197_return_to_calling_exception_handler

+ ld r3, r30, REG_OFF(EF_DSR)

+ cmp r3, r3, 0

+ bb1 eq, r3, m88110_return_to_calling_exception_handler

- r30 can be clobbered by calls. So stuff its value into a

- preserved register, say r15. R14 is in use (see return_to_... below).

+ * r30 can be clobbered by calls. So stuff its value into a

+ * preserved register, say r15. R14 is in use (see return_to_... below).

- or r15, r0, r30

- CALL(_C_LABEL(trap197), T_DATAFLT, r15)

-/* restore it... */

- or r30, r0, r15

+ or r15, r0, r30

+#if 0

+ CALL(_C_LABEL(test_trap), r15, r0)

+#endif

+ CALL(_C_LABEL(m88110_trap), T_DATAFLT, r15)

- /* clear the dsr word in the E.F */

- st r0, r30, REG_OFF(EF_DSR)

+ /* restore it... */

+ or r30, r0, r15

-ASGLOBAL(m197_return_to_calling_exception_handler)

- jmp r14 /* loaded above */

+ /* clear the dsr word in the E.F */

+ st r0, r30, REG_OFF(EF_DSR)

+ASGLOBAL(m88110_return_to_calling_exception_handler)

+ jmp r14 /* loaded above */

+ data

+ .align 8

+GLOBAL(save_frame)

+ space SIZEOF_EF

#endif

diff --git a/sys/arch/mvme88k/mvme88k/locore_c_routines.c b/sys/arch/mvme88k/mvme88k/locore_c_routines.c
index 4b4ea004b59..da7b6fb247d 100644
--- a/sys/arch/mvme88k/mvme88k/locore_c_routines.c
+++ b/sys/arch/mvme88k/mvme88k/locore_c_routines.c

@@ -1,4 +1,4 @@

-/* $OpenBSD: locore_c_routines.c,v 1.19 2001/12/22 09:49:39 smurph Exp $ */

+/* $OpenBSD: locore_c_routines.c,v 1.20 2001/12/22 17:57:11 smurph Exp $ */

* Mach Operating System

@@ -338,20 +338,20 @@ vector_init(m88k_exception_vector_area *vector, unsigned *vector_init_list)

#ifdef M88110

case CPU_88110:

while (num < 496) {

- SET_VECTOR(num, to, m197_sigsys);

+ SET_VECTOR(num, to, m88110_sigsys);

num++;

}

num++; /* skip 496, BUG ROM vector */

- SET_VECTOR(450, to, m197_syscall_handler);

+ SET_VECTOR(450, to, m88110_syscall_handler);

while (num <= SIGSYS_MAX)

- SET_VECTOR(num++, to, m197_sigsys);

+ SET_VECTOR(num++, to, m88110_sigsys);

while (num <= SIGTRAP_MAX)

- SET_VECTOR(num++, to, m197_sigtrap);

+ SET_VECTOR(num++, to, m88110_sigtrap);

- SET_VECTOR(504, to, m197_stepbpt);

- SET_VECTOR(511, to, m197_userbpt);

+ SET_VECTOR(504, to, m88110_stepbpt);

+ SET_VECTOR(511, to, m88110_userbpt);

break;

#endif /* MVME197 */

#ifdef M88100

diff --git a/sys/arch/mvme88k/mvme88k/m88100_fp.S b/sys/arch/mvme88k/mvme88k/m88100_fp.S
index 61788c215e8..0d61f346c39 100644
--- a/sys/arch/mvme88k/mvme88k/m88100_fp.S
+++ b/sys/arch/mvme88k/mvme88k/m88100_fp.S

@@ -1,4 +1,4 @@

-/* $OpenBSD: m88100_fp.S,v 1.15 2001/12/16 23:49:46 miod Exp $ */

+/* $OpenBSD: m88100_fp.S,v 1.16 2001/12/22 17:57:11 smurph Exp $ */

* Mach Operating System

@@ -164,7 +164,7 @@ fp_p_trap:

st r3,r31,32 /* save exception frame */

or r2,r0,T_FPEPFLT /* load trap type */

or r3, r29, r0

- bsr _C_LABEL(trap18x) /* trap */

+ bsr _C_LABEL(m88100_trap) /* trap */

ld r1,r31,36 /* recover return address */

addu r31,r31,40 /* deallocate stack */

br fp_p_return

diff --git a/sys/arch/mvme88k/mvme88k/m88110_fp.S b/sys/arch/mvme88k/mvme88k/m88110_fp.S
index 533e8275451..9b8c073efbf 100644
--- a/sys/arch/mvme88k/mvme88k/m88110_fp.S
+++ b/sys/arch/mvme88k/mvme88k/m88110_fp.S

@@ -1,4 +1,4 @@

-/* $OpenBSD: m88110_fp.S,v 1.8 2001/12/16 23:49:46 miod Exp $ */

+/* $OpenBSD: m88110_fp.S,v 1.9 2001/12/22 17:57:11 smurph Exp $ */

@@ -82,7 +82,7 @@ ASGLOBAL(m88110_FPuimp)

st r3,r31,32 /* save exception frame */

or r2,r0,T_FPEPFLT /* load trap type */

or r3, r29, r0

- bsr _C_LABEL(trap197) /* trap */

+ bsr _C_LABEL(m88110_trap) /* trap */

ld r1,r31,36 /* recover return address */

addu r31,r31,40 /* deallocate stack */

jmp r1

@@ -93,7 +93,7 @@ ASGLOBAL(m88110_FPpriviol)

st r3,r31,32 /* save exception frame */

or r2,r0,T_PRIVINFLT /* load trap type */

or r3, r29, r0

- bsr _C_LABEL(trap197) /* trap */

+ bsr _C_LABEL(m88110_trap) /* trap */

ld r1,r31,36 /* recover return address */

addu r31,r31,40 /* deallocate stack */

jmp r1

diff --git a/sys/arch/mvme88k/mvme88k/machdep.c b/sys/arch/mvme88k/mvme88k/machdep.c
index b92c53827b6..1c5ccafe92f 100644
--- a/sys/arch/mvme88k/mvme88k/machdep.c
+++ b/sys/arch/mvme88k/mvme88k/machdep.c

@@ -1,4 +1,4 @@

-/* $OpenBSD: machdep.c,v 1.80 2001/12/22 09:49:39 smurph Exp $ */

+/* $OpenBSD: machdep.c,v 1.81 2001/12/22 17:57:11 smurph Exp $ */

@@ -1725,7 +1725,7 @@ m188_ext_int(u_int v, struct m88100_saved_state *eframe)

out_m188:

disable_interrupt();

if (eframe->dmt0 & DMT_VALID) {

- trap18x(T_DATAFLT, eframe);

+ m88100_trap(T_DATAFLT, eframe);

data_access_emulation((unsigned *)eframe);

eframe->dmt0 &= ~DMT_VALID;

}

@@ -1852,7 +1852,7 @@ m187_ext_int(u_int v, struct m88100_saved_state *eframe)

out:

if (eframe->dmt0 & DMT_VALID) {

- trap18x(T_DATAFLT, eframe);

+ m88100_trap(T_DATAFLT, eframe);

data_access_emulation((unsigned *)eframe);

eframe->dmt0 &= ~DMT_VALID;

}

diff --git a/sys/arch/mvme88k/mvme88k/trap.c b/sys/arch/mvme88k/mvme88k/trap.c
index fdd18259bc8..c96090f858a 100644
--- a/sys/arch/mvme88k/mvme88k/trap.c
+++ b/sys/arch/mvme88k/mvme88k/trap.c

@@ -1,4 +1,4 @@

-/* $OpenBSD: trap.c,v 1.31 2001/12/22 10:34:32 smurph Exp $ */

+/* $OpenBSD: trap.c,v 1.32 2001/12/22 17:57:11 smurph Exp $ */

@@ -196,7 +196,7 @@ unsigned last_vector = 0;

/*ARGSUSED*/

void

-trap18x(unsigned type, struct m88100_saved_state *frame)

+m88100_trap(unsigned type, struct m88100_saved_state *frame)

{

struct proc *p;

u_quad_t sticks = 0;

@@ -685,11 +685,12 @@ outtahere:

userret(p, frame, sticks);

}

#endif /* m88100 */

+unsigned v_fault = 0;

#ifdef M88110

/*ARGSUSED*/

void

-trap197(unsigned type, struct m88100_saved_state *frame)

+m88110_trap(unsigned type, struct m88100_saved_state *frame)

{

struct proc *p;

u_quad_t sticks = 0;

@@ -716,6 +717,11 @@ trap197(unsigned type, struct m88100_saved_state *frame)

if ((p = curproc) == NULL)

p = &proc0;

+#if 1

+ if (type != T_INT && type != T_ASTFLT && type != T_KDB_ENTRY ) {

+ printf("m88110_trap: %d %s\n", type, frame->vector < trap_types ? trap_type[frame->vector] : "unknown");

+ }

+#endif

if (USERMODE(frame->epsr)) {

sticks = p->p_sticks;

@@ -1000,6 +1006,7 @@ m88110_user_fault:

if ((frame->isr & CMMU_ISR_SI) /* seg fault */

|| (frame->isr & CMMU_ISR_PI)) { /* page fault */

result = uvm_fault(map, va, 0, ftype);

+ v_fault++;

} else if ((frame->isr & CMMU_ISR_BE)

|| (frame->isr & CMMU_ISR_SP)

|| (frame->isr & CMMU_ISR_TBE)) { /* bus error */

@@ -1017,15 +1024,13 @@ m88110_user_fault:

}

if (result != 0) {

-#if 0

+#ifdef smurph_debug

printf("Access failed! result = %d\n\n", result);

frame->mode = v_fault;

regdump(frame);

Debugger();

sig = result == EACCES ? SIGBUS : SIGSEGV;

fault_type = result == EACCES ? BUS_ADRERR : SEGV_MAPERR;

-#else

- result = 0;

#endif

}

break;

@@ -1230,7 +1235,7 @@ error_reset(struct m88100_saved_state *frame)

#ifdef M88100

void

-syscall(register_t code, struct m88100_saved_state *tf)

+m88100_syscall(register_t code, struct m88100_saved_state *tf)

{

@@ -1389,7 +1394,7 @@ syscall(register_t code, struct m88100_saved_state *tf)

/* Instruction pointers opperate differently on mc88110 */

void

-m197_syscall(register_t code, struct m88100_saved_state *tf)

+m88110_syscall(register_t code, struct m88100_saved_state *tf)

{

@@ -1445,7 +1450,7 @@ m197_syscall(register_t code, struct m88100_saved_state *tf)

}

/* Callp currently points to syscall, which returns ENOSYS. */

+ printf("syscall code is %d\n", code);

if (code < 0 || code >= nsys)

callp += p->p_emul->e_nosys;

else {