diff options
author | Miod Vallat <miod@cvs.openbsd.org> | 2003-09-16 20:53:42 +0000 |
---|---|---|
committer | Miod Vallat <miod@cvs.openbsd.org> | 2003-09-16 20:53:42 +0000 |
commit | 6d588810256755cc4fdc46448292d1fb9b79ebc2 (patch) | |
tree | 07f27c6f1052c23b7611c838d5d928082f3f76a9 /sys/arch/mvme88k | |
parent | e797da6f452d30adb2b2b7cc02fa8b2e4028f39c (diff) |
Do not use | !FOO to mention undesirable flags, but rather & ~FOO - hopefully
this had no side effects...
Diffstat (limited to 'sys/arch/mvme88k')
-rw-r--r-- | sys/arch/mvme88k/mvme88k/m8820x.c | 91 |
1 files changed, 16 insertions, 75 deletions
diff --git a/sys/arch/mvme88k/mvme88k/m8820x.c b/sys/arch/mvme88k/mvme88k/m8820x.c index 20bbb639e8c..532e5bf4098 100644 --- a/sys/arch/mvme88k/mvme88k/m8820x.c +++ b/sys/arch/mvme88k/mvme88k/m8820x.c @@ -1,4 +1,4 @@ -/* $OpenBSD: m8820x.c,v 1.17 2003/09/16 20:46:11 miod Exp $ */ +/* $OpenBSD: m8820x.c,v 1.18 2003/09/16 20:53:41 miod Exp $ */ /* * Copyright (c) 2001 Steve Murphree, Jr. * Copyright (c) 1996 Nivas Madhur @@ -874,18 +874,14 @@ m8820x_cmmu_init() * Set the SCTR, SAPR, and UAPR to some known state * (I don't trust the reset to do it). */ - tmp = - ! CMMU_SCTR_PE | /* not parity enable */ - ! CMMU_SCTR_SE | /* not snoop enable */ - ! CMMU_SCTR_PR ; /* not priority arbitration */ + tmp = 0 & ~( + CMMU_SCTR_PE | /* not parity enable */ + CMMU_SCTR_SE | /* not snoop enable */ + CMMU_SCTR_PR); /* not priority arbitration */ m8820x_cmmu[cmmu_num].cmmu_regs->sctr = tmp; - tmp = - (0x00000 << PG_BITS) | /* segment table base address */ - AREA_D_WT | /* write through */ - AREA_D_G | /* global */ - AREA_D_CI | /* cache inhibit */ - ! AREA_D_TE ; /* not translation enable */ + tmp = ((0x00000 << PG_BITS) | AREA_D_WT | AREA_D_G | + AREA_D_CI) & ~AREA_D_TE; m8820x_cmmu[cmmu_num].cmmu_regs->sapr = m8820x_cmmu[cmmu_num].cmmu_regs->uapr = tmp; @@ -926,14 +922,9 @@ m8820x_cmmu_init() * breakpoints, etc, and modify code. */ if (brdtyp == BRD_188) { - tmp = - ! CMMU_SCTR_PE | /* not parity enable */ - CMMU_SCTR_SE | /* snoop enable */ - ! CMMU_SCTR_PR ; /* not priority arbitration */ + tmp = CMMU_SCTR_SE & ~(CMMU_SCTR_PE | CMMU_SCTR_PR); } else { - tmp = - ! CMMU_SCTR_PE | /* not parity enable */ - ! CMMU_SCTR_PR ; /* not priority arbitration */ + tmp = 0 & ~(CMMU_SCTR_PE | CMMU_SCTR_PR); } m8820x_cmmu_set(CMMU_SCTR, tmp, 0, cpu, DATA_CMMU, 0, 0); m8820x_cmmu_set(CMMU_SCTR, tmp, 0, cpu, INST_CMMU, 0, 0); @@ -956,21 +947,11 @@ m8820x_cmmu_init() * be cached, and we don't have those no-caching zones * set up yet.... */ - tmp = - (0x00000 << PG_BITS) | /* segment table base address */ - AREA_D_WT | /* write through */ - AREA_D_G | /* global */ - AREA_D_CI | /* cache inhibit */ - ! AREA_D_TE ; /* not translation enable */ - /* - REGS(cpu, INST_CMMU).sapr = tmp; - */ + tmp = ((0x00000 << PG_BITS) | AREA_D_WT | AREA_D_G | AREA_D_CI) + & ~AREA_D_TE; m8820x_cmmu_set(CMMU_SAPR, tmp, MODE_VAL, cpu, INST_CMMU, 0, 0); - /* - REGS(cpu, DATA_CMMU).scr = CMMU_FLUSH_SUPER_ALL; - */ m8820x_cmmu_set(CMMU_SCR, CMMU_FLUSH_SUPER_ALL, ACCESS_VAL|MODE_VAL, cpu, DATA_CMMU, CMMU_ACS_SUPER, 0); } @@ -991,24 +972,15 @@ m8820x_cmmu_shutdown_now() */ for (cmmu_num = 0; cmmu_num < MAX_CMMUS; cmmu_num++) { if (brdtyp == BRD_188) { - tmp = - ! CMMU_SCTR_PE | /* parity enable */ - ! CMMU_SCTR_SE | /* snoop enable */ - ! CMMU_SCTR_PR ; /* priority arbitration */ + tmp = 0 & ~(CMMU_SCTR_PE | CMMU_SCTR_SE | CMMU_SCTR_PR); } else { - tmp = - ! CMMU_SCTR_PE | /* parity enable */ - ! CMMU_SCTR_PR ; /* priority arbitration */ + tmp = 0 & ~(CMMU_SCTR_PE | CMMU_SCTR_PR); } m8820x_cmmu[cmmu_num].cmmu_regs->sctr = tmp; - tmp = - (0x00000 << PG_BITS) | /* segment table base address */ - ! AREA_D_WT | /* write through */ - ! AREA_D_G | /* global */ - AREA_D_CI | /* cache inhibit */ - ! AREA_D_TE ; /* translation disable */ + tmp = ((0x00000 << PG_BITS) | AREA_D_CI) & + ~(AREA_D_WT | AREA_D_G | AREA_D_TE); m8820x_cmmu[cmmu_num].cmmu_regs->sapr = tmp; m8820x_cmmu[cmmu_num].cmmu_regs->uapr = tmp; @@ -1048,7 +1020,7 @@ m8820x_cmmu_parity_enable() * Better be at splhigh, or even better, with interrupts * disabled. */ -#define ILLADDRESS U(0x0F000000) /* any faulty address */ +#define ILLADDRESS 0x0F000000 /* any faulty address */ unsigned m8820x_cmmu_cpu_number() @@ -1087,27 +1059,6 @@ m8820x_cmmu_cpu_number() return 0; /* to make compiler happy */ } -#if 0 -/* - * Functions that actually modify CMMU registers. - */ -void -m8820x_cmmu_remote_set(unsigned cpu, unsigned r, unsigned data, unsigned x) -{ - *(unsigned *volatile)(r + (char *)®S(cpu,data)) = x; -} - -/* - * cmmu_cpu_lock should be held when called if read - * the CMMU_SCR or CMMU_SAR. - */ -unsigned -m8820x_cmmu_remote_get(unsigned cpu, unsigned r, unsigned data) -{ - return (*(unsigned *volatile)(r + (char *)®S(cpu,data))); -} -#endif - /* Needs no locking - read only registers */ unsigned m8820x_cmmu_get_idr(data) @@ -1182,10 +1133,6 @@ m8820x_cmmu_set_batc_entry(cpu, entry_no, data, value) #ifdef SHADOW_BATC CMMU(cpu,data)->batc[entry_no] = value; #endif -#if 0 /* was for debugging piece (peace?) of mind */ - REGS(cpu,data).scr = CMMU_FLUSH_SUPER_ALL; - REGS(cpu,data).scr = CMMU_FLUSH_USER_ALL; -#endif CMMU_UNLOCK; } @@ -1210,12 +1157,6 @@ m8820x_cmmu_set_pair_batc_entry(cpu, entry_no, value) CMMU(cpu,INST_CMMU)->batc[entry_no] = value; #endif -#if 0 /* was for debugging piece (peace?) of mind */ - REGS(cpu,INST_CMMU).scr = CMMU_FLUSH_SUPER_ALL; - REGS(cpu,INST_CMMU).scr = CMMU_FLUSH_USER_ALL; - REGS(cpu,DATA_CMMU).scr = CMMU_FLUSH_SUPER_ALL; - REGS(cpu,DATA_CMMU).scr = CMMU_FLUSH_USER_ALL; -#endif CMMU_UNLOCK; } |