Feature sync with macppc

1 files changed, 126 insertions, 96 deletions

diff --git a/sys/arch/mvmeppc/dev/cpu.c b/sys/arch/mvmeppc/dev/cpu.c
index 9dea046353e..66f513f4943 100644
--- a/sys/arch/mvmeppc/dev/cpu.c
+++ b/sys/arch/mvmeppc/dev/cpu.c
@@ -1,9 +1,9 @@
-/*	$OpenBSD: cpu.c,v 1.7 2004/01/14 20:50:49 miod Exp $ */
+/*	$OpenBSD: cpu.c,v 1.8 2004/11/18 16:10:28 miod Exp $ */
 
 /*
  * Copyright (c) 1997 Per Fogelstrom
  * Copyright (c) 1997 RTMX Inc
- * 
+ *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions
  * are met:
@@ -41,21 +41,35 @@
 
 #include <machine/autoconf.h>
 
+/* only valid on 603(e,ev) and G3, G4 */
+#define HID0_DOZE	(1 << (31-8))
+#define HID0_NAP	(1 << (31-9))
+#define HID0_SLEEP	(1 << (31-10))
+#define HID0_DPM	(1 << (31-11))
+#define HID0_SGE	(1 << (31-24))
+#define HID0_BTIC	(1 << (31-26))
+#define HID0_LRSTK	(1 << (31-27))
+#define HID0_FOLD	(1 << (31-28))
+#define HID0_BHT	(1 << (31-29))
+
 char cpu_model[80];
 char machine[] = MACHINE;	/* cpu architecture */
 
 /* Definition of the driver for autoconfig. */
-static int	cpumatch(struct device *, void *, void *);
-static void	cpuattach(struct device *, struct device *, void *);
+int	cpumatch(struct device *, void *, void *);
+void	cpuattach(struct device *, struct device *, void *);
 
 struct cfattach cpu_ca = {
 	sizeof(struct device), cpumatch, cpuattach
 };
+
 struct cfdriver cpu_cd = {
 	NULL, "cpu", DV_DULL
 };
 
-static int
+void config_l2cr(int cpu);
+
+int
 cpumatch(parent, cfdata, aux)
 	struct device *parent;
 	void *cfdata;
@@ -70,100 +84,100 @@ cpumatch(parent, cfdata, aux)
 	return (1);
 }
 
-void config_l2cr(void);
-
-static void
-cpuattach(parent, dev, aux)
-	struct device *parent;
-	struct device *dev;
-	void *aux;
+void
+cpuattach(struct device *parent, struct device *dev, void *aux)
 {
-	int cpu, pvr;
-#ifdef OFW
-	char name[32];
-	int qhandle, phandle;
-	unsigned int clock_freq = 0;
-#endif
+	unsigned int cpu, pvr, hid0;
 
-	__asm__ ("mfpvr %0" : "=r"(pvr));
+	pvr = ppc_mfpvr();
 	cpu = pvr >> 16;
 	switch (cpu) {
-	case 1:
-		snprintf(cpu_model, sizeof cpu_model, "601");
+	case PPC_CPU_MPC601:
+		snprintf(cpu_model, sizeof(cpu_model), "601");
+		break;
+	case PPC_CPU_MPC603:
+		snprintf(cpu_model, sizeof(cpu_model), "603");
 		break;
-	case 3:
-		snprintf(cpu_model, sizeof cpu_model, "603");
+	case PPC_CPU_MPC604:
+		snprintf(cpu_model, sizeof(cpu_model), "604");
 		break;
-	case 4:
-		snprintf(cpu_model, sizeof cpu_model, "604");
+	case PPC_CPU_MPC603e:
+		snprintf(cpu_model, sizeof(cpu_model), "603e");
 		break;
-	case 5:
-		snprintf(cpu_model, sizeof cpu_model, "602");
+	case PPC_CPU_MPC603ev:
+		snprintf(cpu_model, sizeof(cpu_model), "603ev");
 		break;
-	case 6:
-		snprintf(cpu_model, sizeof cpu_model, "603e");
+	case PPC_CPU_MPC750:
+		snprintf(cpu_model, sizeof(cpu_model), "750");
 		break;
-	case 7:
-		snprintf(cpu_model, sizeof cpu_model, "603ev");
+	case PPC_CPU_MPC604ev:
+		snprintf(cpu_model, sizeof(cpu_model), "604ev");
 		break;
-	case 8:
-		snprintf(cpu_model, sizeof cpu_model, "750");
+	case PPC_CPU_MPC7400:
+		snprintf(cpu_model, sizeof(cpu_model), "7400");
 		break;
-	case 9:
-		snprintf(cpu_model, sizeof cpu_model, "604ev");
+	case PPC_CPU_IBM750FX:
+		snprintf(cpu_model, sizeof(cpu_model), "750FX");
 		break;
-	case 12:
-		snprintf(cpu_model, sizeof cpu_model, "7400(G4)");
+	case PPC_CPU_MPC7410:
+		snprintf(cpu_model, sizeof(cpu_model), "7410");
 		break;
-	case 20:
-		snprintf(cpu_model, sizeof cpu_model, "620");
+	case PPC_CPU_MPC7450:
+		if ((pvr & 0xf) < 3)
+			snprintf(cpu_model, sizeof(cpu_model), "7450");
+		 else
+			snprintf(cpu_model, sizeof(cpu_model), "7451");
+		break;
+	case PPC_CPU_MPC7455:
+		snprintf(cpu_model, sizeof(cpu_model), "7455");
 		break;
 	default:
-		snprintf(cpu_model, sizeof cpu_model, "Version %x", cpu);
+		snprintf(cpu_model, sizeof(cpu_model), "Version %x", cpu);
 		break;
 	}
 	snprintf(cpu_model + strlen(cpu_model),
-	    sizeof cpu_model - strlen(cpu_model),
+	    sizeof(cpu_model) - strlen(cpu_model),
 	    " (Revision %x)", pvr & 0xffff);
 	printf(": %s", cpu_model);
 
-	/* This should only be executed on openfirmware systems... */
-#ifdef OFW
-	for (qhandle = OF_peer(0); qhandle; qhandle = phandle) {
-                if (OF_getprop(qhandle, "device_type", name, sizeof name) >= 0
-                    && !strcmp(name, "cpu")
-                    && OF_getprop(qhandle, "clock-frequency",
-                                  &clock_freq , sizeof clock_freq ) >= 0)
-		{
-			break;
-		}
-                if (phandle = OF_child(qhandle))
-                        continue;
-                while (qhandle) {
-                        if (phandle = OF_peer(qhandle))
-                                break;
-                        qhandle = OF_parent(qhandle);
-                }
+	/* power savings mode */
+	hid0 = ppc_mfhid0();
+	switch (cpu) {
+	case PPC_CPU_MPC603:
+	case PPC_CPU_MPC603e:
+	case PPC_CPU_MPC750:
+	case PPC_CPU_MPC7400:
+	case PPC_CPU_IBM750FX:
+	case PPC_CPU_MPC7410:
+		/* select DOZE mode */
+		hid0 &= ~(HID0_NAP | HID0_SLEEP);
+		hid0 |= HID0_DOZE | HID0_DPM;
+		break;
+	case PPC_CPU_MPC7450:
+	case PPC_CPU_MPC7455:
+		/* select NAP mode */
+		hid0 &= ~(HID0_DOZE | HID0_SLEEP);
+		hid0 |= HID0_NAP | HID0_DPM;
+		/* try some other flags */
+		hid0 |= HID0_SGE | HID0_BTIC;
+		hid0 |= HID0_LRSTK | HID0_FOLD | HID0_BHT;
+		/* Disable BTIC on 7450 Rev 2.0 or earlier */
+		if (cpu == PPC_CPU_MPC7450 && (pvr & 0xffff) < 0x0200)
+			hid0 &= ~HID0_BTIC;
+		break;
 	}
+	ppc_mthid0(hid0);
 
-	if (clock_freq != 0) {
-		/* Openfirmware stores clock in HZ, not MHz */
-		clock_freq /= 1000000;
-		printf(": %d MHz", clock_freq);
-
-	}
-#endif
-	/* if processor is G3 or G4, configure l2 cache */ 
-	if  ( (cpu == 8) || (cpu == 12) ) {
-		config_l2cr();
+	/* if processor is G3 or G4, configure l2 cache */
+	if (cpu == PPC_CPU_MPC750 || cpu == PPC_CPU_MPC7400 ||
+	    cpu == PPC_CPU_IBM750FX || cpu == PPC_CPU_MPC7410 ||
+	    cpu == PPC_CPU_MPC7450 || cpu == PPC_CPU_MPC7455) {
+		config_l2cr(cpu);
 	}
 	printf("\n");
-
-
 }
 
-#define L2CR 1017
-
+/* L2CR bit definitions */
 #define L2CR_L2E        0x80000000 /* 0: L2 enable */
 #define L2CR_L2PE       0x40000000 /* 1: L2 data parity enable */
 #define L2CR_L2SIZ      0x30000000 /* 2-3: L2 size */
@@ -196,56 +210,74 @@ cpuattach(parent, dev, aux)
 #define L2CR_L2DF       0x00004000 /* 17: L2 differential clock. */
 #define L2CR_L2BYP      0x00002000 /* 18: L2 DLL bypass. */
 #define L2CR_L2IP       0x00000001 /* 31: L2 global invalidate in progress
-                                      (read only). */
+				       (read only). */
 #ifdef L2CR_CONFIG
 u_int l2cr_config = L2CR_CONFIG;
 #else
 u_int l2cr_config = 0;
 #endif
 
+/* L3CR bit definitions */
+#define   L3CR_L3E                0x80000000 /*  0: L3 enable */
+#define   L3CR_L3SIZ              0x10000000 /*  3: L3 size (0=1MB, 1=2MB) */
+
 void
-config_l2cr()
+config_l2cr(int cpu)
 {
 	u_int l2cr, x;
 
-	__asm __volatile ("mfspr %0, 1017" : "=r"(l2cr));
+	l2cr = ppc_mfl2cr();
 
 	/*
 	 * Configure L2 cache if not enabled.
 	 */
 	if ((l2cr & L2CR_L2E) == 0 && l2cr_config != 0) {
 		l2cr = l2cr_config;
-		asm volatile ("mtspr 1017,%0" :: "r"(l2cr));
+		ppc_mtl2cr(l2cr);
 
 		/* Wait for L2 clock to be stable (640 L2 clocks). */
 		delay(100);
 
 		/* Invalidate all L2 contents. */
 		l2cr |= L2CR_L2I;
-		asm volatile ("mtspr 1017,%0" :: "r"(l2cr));
+		ppc_mtl2cr(l2cr);
 		do {
-			asm volatile ("mfspr %0, 1017" : "=r"(x));
+			x = ppc_mfl2cr();
 		} while (x & L2CR_L2IP);
-				      
+
 		/* Enable L2 cache. */
 		l2cr &= ~L2CR_L2I;
 		l2cr |= L2CR_L2E;
-		asm volatile ("mtspr 1017,%0" :: "r"(l2cr));
+		ppc_mtl2cr(l2cr);
 	}
 
 	if (l2cr & L2CR_L2E) {
-		switch (l2cr & L2CR_L2SIZ) {
-		case L2SIZ_256K:
-			printf(": 256KB");
-			break;
-		case L2SIZ_512K:
-			printf(": 512KB");
-			break;
-		case L2SIZ_1M:  
-			printf(": 1MB");
-			break;
-		default:
-			printf(": unknown size");
+		if (cpu == PPC_CPU_MPC7450 || cpu == PPC_CPU_MPC7455) {
+			u_int l3cr;
+
+			printf(": 256KB L2 cache");
+
+			l3cr = ppc_mfl3cr();
+			if (l3cr & L3CR_L3E)
+				printf(", %cMB L3 cache",
+				    l3cr & L3CR_L3SIZ ? '2' : '1');
+		} else if (cpu == PPC_CPU_IBM750FX)
+			printf(": 512KB L2 cache");
+		else {
+			switch (l2cr & L2CR_L2SIZ) {
+			case L2SIZ_256K:
+				printf(": 256KB");
+				break;
+			case L2SIZ_512K:
+				printf(": 512KB");
+				break;
+			case L2SIZ_1M:
+				printf(": 1MB");
+				break;
+			default:
+				printf(": unknown size");
+			}
+			printf(" backside cache");
 		}
 #if 0
 		switch (l2cr & L2CR_L2RAM) {
@@ -261,12 +293,10 @@ config_l2cr()
 		default:
 			printf(" unknown type");
 		}
-		
+
 		if (l2cr & L2CR_L2PE)
-			printf(" with parity");  
+			printf(" with parity");
 #endif
-		printf(" backside cache");
 	} else
 		printf(": L2 cache not enabled");
-		
 }