Change len in syncicache(_, len) from int to size_t

The powerpc64 part is under #if 0, so this change affects only macppc.
Simplify powerpc64's __syncicache (which had size_t len) and copy it
to macppc's syncicache (which had int len).

macppc was looping while ((l -= CACHELINESIZE) > 0).  The loop would
be infinite if l became an unsigned type like size_t.  It is simpler
to set size_t i = 0, do i += by, and loop while (i < len).  It helps
that dcbst and icbi can add 2 registers, from + i.

1 files changed, 11 insertions, 17 deletions

diff --git a/sys/arch/powerpc64/powerpc64/syncicache.c b/sys/arch/powerpc64/powerpc64/syncicache.c
index d462efbfbf7..6afd1282e6f 100644
--- a/sys/arch/powerpc64/powerpc64/syncicache.c
+++ b/sys/arch/powerpc64/powerpc64/syncicache.c
@@ -1,4 +1,4 @@
-/*	$OpenBSD: syncicache.c,v 1.4 2022/08/29 02:01:18 jsg Exp $	*/
+/*	$OpenBSD: syncicache.c,v 1.5 2022/10/21 21:26:49 gkoehler Exp $	*/
 
 /*-
  * SPDX-License-Identifier: BSD-4-Clause
@@ -43,25 +43,20 @@ void
 __syncicache(void *from, size_t len)
 {
 #if 0
-	size_t	l, off;
-	char	*p;
-
-	off = (uintptr_t)from & (cacheline_size - 1);
-	l = len += off;
-	p = (char *)from - off;
+	size_t	by, i;
 
+	by = cacheline_size;
+	i = 0;
 	do {
-		__asm volatile ("dcbst 0,%0" :: "r"(p));
-		p += cacheline_size;
-		l -= cacheline_size;
-	} while (l + cacheline_size > cacheline_size);
+		__asm volatile ("dcbst %0,%1" :: "r"(from), "r"(i));
+		i += by;
+	} while (i < len);
 	__asm volatile ("sync");
-	p = (char *)from - off;
+	i = 0;
 	do {
-		__asm volatile ("icbi 0,%0" :: "r"(p));
-		p += cacheline_size;
-		len -= cacheline_size;
-	} while (len + cacheline_size > cacheline_size);
+		__asm volatile ("icbi %0,%1" :: "r"(from), "r"(i));
+		i += by;
+	} while (i < len);
 	__asm volatile ("sync; isync");
 #else
 	sync();
@@ -69,4 +64,3 @@ __syncicache(void *from, size_t len)
 	isync();
 #endif
 }
-