Rework the per-cpu cache information. Use a common struct to store the line

size, the number of sets, and the total size (and the set size, for convenience)
per cache (I$, D$, L2, L3).
This allows cpu.c to print the number of ways (sets) of L2 and L3 caches from
the cache information, rather than hardcoding this from the processor type.

5 files changed, 22 insertions, 44 deletions

diff --git a/sys/arch/sgi/include/cpu.h b/sys/arch/sgi/include/cpu.h
index 18181df485a..093e917370f 100644
--- a/sys/arch/sgi/include/cpu.h
+++ b/sys/arch/sgi/include/cpu.h
@@ -1,4 +1,4 @@
-/*	$OpenBSD: cpu.h,v 1.14 2012/06/24 16:26:04 miod Exp $ */
+/*	$OpenBSD: cpu.h,v 1.15 2014/03/09 10:12:17 miod Exp $ */
 /*-
  * Copyright (c) 1992, 1993
  *	The Regents of the University of California.  All rights reserved.
@@ -55,7 +55,6 @@ void hw_cpu_spinup_trampoline(struct cpu_info *);
 int  hw_ipi_intr_establish(int (*)(void *), u_long);
 void hw_ipi_intr_set(u_long);
 void hw_ipi_intr_clear(u_long);
-void hw_cpu_init_secondary(struct cpu_info *);
 #endif	/* MULTIPROCESSOR && !_LOCORE */
 
 
diff --git a/sys/arch/sgi/localbus/tcc.c b/sys/arch/sgi/localbus/tcc.c
index e8d3233ffd0..0e6ff894cb8 100644
--- a/sys/arch/sgi/localbus/tcc.c
+++ b/sys/arch/sgi/localbus/tcc.c
@@ -1,4 +1,4 @@
-/*	$OpenBSD: tcc.c,v 1.2 2012/10/03 11:18:23 miod Exp $	*/
+/*	$OpenBSD: tcc.c,v 1.3 2014/03/09 10:12:17 miod Exp $	*/
 
 /*
  * Copyright (c) 2012 Miodrag Vallat.
@@ -142,16 +142,14 @@ void tcc_virtual(struct cpu_info *, vaddr_t, vsize_t, uint64_t);
 void
 tcc_ConfigCache(struct cpu_info *ci)
 {
-	uint l2line, l2size;
+	struct cache_info l2;
 
-	l2line = ci->ci_l2line;
-	l2size = ci->ci_l2size;
+	l2 = ci->ci_l2;
 
 	tfp_ConfigCache(ci);
 
-	if (l2size != 0) {
-		ci->ci_l2line = l2line;
-		ci->ci_l2size = l2size;
+	if (l2.size != 0) {
+		ci->ci_l2 = l2;
 
 		ci->ci_SyncCache = tcc_SyncCache;
 		ci->ci_SyncDCachePage = tcc_SyncDCachePage;
@@ -167,7 +165,7 @@ tcc_SyncCache(struct cpu_info *ci)
 	uint64_t idx;
 
 	mips_sync();
-	tfp_InvalidateICache(ci, 0, ci->ci_l1instcachesize);
+	tfp_InvalidateICache(ci, 0, ci->ci_l1inst.size);
 
 	/*
 	 * The following relies upon the fact that the (line, set)
@@ -175,7 +173,7 @@ tcc_SyncCache(struct cpu_info *ci)
 	 * a huge number of sets and only one line, we can span the
 	 * whole cache.
 	 */
-	idx = (uint64_t)ci->ci_l2size / TCC_CACHE_LINE;
+	idx = (uint64_t)ci->ci_l2.size / TCC_CACHE_LINE;
 	while (idx != 0) {
 		idx--;
 		tcc_cache_index(idx, 0,
diff --git a/sys/arch/sgi/sgi/ip22_machdep.c b/sys/arch/sgi/sgi/ip22_machdep.c
index 2f398319ba7..909f75146d8 100644
--- a/sys/arch/sgi/sgi/ip22_machdep.c
+++ b/sys/arch/sgi/sgi/ip22_machdep.c
@@ -1,4 +1,4 @@
-/*	$OpenBSD: ip22_machdep.c,v 1.14 2012/09/29 21:46:02 miod Exp $	*/
+/*	$OpenBSD: ip22_machdep.c,v 1.15 2014/03/09 10:12:17 miod Exp $	*/
 
 /*
  * Copyright (c) 2012 Miodrag Vallat.
@@ -115,8 +115,10 @@ ip22_arcbios_walk_component(arc_config_t *cf)
 		 * SS is Log2(cache size in 4KB units)
 		 *   (should be between 0007 and 0009)
 		 */
-		ci->ci_l2size = (1 << 12) << (key & 0x0000ffff);
-		ci->ci_l2line = 1 << ((key >> 16) & 0xff);
+		ci->ci_l2.size = (1 << 12) << (key & 0x0000ffff);
+		ci->ci_l2.linesize = 1 << ((key >> 16) & 0xff);
+		ci->ci_l2.setsize = ci->ci_l2.size;
+		ci->ci_l2.sets = 1;
 
 		ip22_arcwalk_results |= IP22_HAS_L2;
 	}
@@ -752,7 +754,7 @@ ip22_cache_halt(int howto)
 void
 ip22_ConfigCache(struct cpu_info *ci)
 {
-	uint l2line, l2size;
+	struct cache_info l2;
 
 	/*
 	 * Note that we are relying upon machdep.c only invoking us if we
@@ -763,12 +765,11 @@ ip22_ConfigCache(struct cpu_info *ci)
 		return;
 	}
 
-	l2line = ci->ci_l2line;
-	l2size = ci->ci_l2size;
+	l2 = ci->ci_l2;
 
 	Mips5k_ConfigCache(ci);
 
-	if (l2line != IP22_L2_LINE) {
+	if (ci->ci_l2.linesize != IP22_L2_LINE) {
 		/*
 		 * This should not happen. Better not try and tame an
 		 * unknown beast.
@@ -776,8 +777,7 @@ ip22_ConfigCache(struct cpu_info *ci)
 		return;
 	}
 
-	ci->ci_l2line = l2line;
-	ci->ci_l2size = l2size;
+	ci->ci_l2 = l2;
 
 	ci->ci_SyncCache = ip22_SyncCache;
 	ci->ci_IOSyncDCache = ip22_IOSyncDCache;
@@ -794,7 +794,7 @@ ip22_SyncCache(struct cpu_info *ci)
 	Mips5k_SyncCache(ci);
 
 	sva = PHYS_TO_XKPHYS(IP22_CACHE_TAG_ADDRESS, CCA_NC);
-	eva = sva + ci->ci_l2size;
+	eva = sva + ci->ci_l2.size;
 
 	while (sva < eva) {
 		*(volatile uint32_t *)sva = 0;
@@ -833,7 +833,7 @@ ip22_IOSyncDCache(struct cpu_info *ci, vaddr_t _va, size_t _sz, int how)
 #endif
 			}
 
-			pa &= ci->ci_l2size - 1;
+			pa &= ci->ci_l2.size - 1;
 			pa |= PHYS_TO_XKPHYS(IP22_CACHE_TAG_ADDRESS, CCA_NC);
 
 			while (sz != 0) {
diff --git a/sys/arch/sgi/sgi/ip30_machdep.c b/sys/arch/sgi/sgi/ip30_machdep.c
index 501bbf7f3d8..0ab4b9f6297 100644
--- a/sys/arch/sgi/sgi/ip30_machdep.c
+++ b/sys/arch/sgi/sgi/ip30_machdep.c
@@ -1,4 +1,4 @@
-/*	$OpenBSD: ip30_machdep.c,v 1.58 2014/01/06 21:41:15 miod Exp $	*/
+/*	$OpenBSD: ip30_machdep.c,v 1.59 2014/03/09 10:12:17 miod Exp $	*/
 
 /*
  * Copyright (c) 2008, 2009 Miodrag Vallat.
@@ -607,23 +607,4 @@ hw_ipi_intr_clear(u_long cpuid)
 {
 	xheart_intr_clear(HEART_ISR_IPI(cpuid));
 }
-
-void
-hw_cpu_init_secondary(struct cpu_info *ci)
-{
-	/*
-	 * When attaching secondary processors, cache information is not
-	 * available yet.  But since the MP-capable systems we run on
-	 * currently all have R10k-style caches, we can quickly compute
-	 * the needed values.
-	 */
-	ci->ci_cacheways = 2;
-	ci->ci_l1instcachesize = 32 * 1024;
-	ci->ci_l1instcacheline = 64;
-	ci->ci_l1datacachesize = 32 * 1024;
-	ci->ci_l1datacacheline = 32;
-	ci->ci_l2size = ci->ci_hw.l2size;
-	ci->ci_l2line = 64;			/* safe default */
-	ci->ci_l3size = 0;
-}
 #endif
diff --git a/sys/arch/sgi/sgi/machdep.c b/sys/arch/sgi/sgi/machdep.c
index 137e553e0b0..96114a5ea23 100644
--- a/sys/arch/sgi/sgi/machdep.c
+++ b/sys/arch/sgi/sgi/machdep.c
@@ -1,4 +1,4 @@
-/*	$OpenBSD: machdep.c,v 1.133 2013/09/28 12:40:31 miod Exp $ */
+/*	$OpenBSD: machdep.c,v 1.134 2014/03/09 10:12:17 miod Exp $ */
 
 /*
  * Copyright (c) 2003-2004 Opsycon AB  (www.opsycon.se / www.opsycon.com)
@@ -532,7 +532,7 @@ mips_init(int argc, void *argv, caddr_t boot_esym)
 		extern void xtlb_miss_err_r4k;
 		extern void xtlb_miss_err_r4000SC;
 
-		if (ci->ci_l2size == 0 ||
+		if (ci->ci_l2.size == 0 ||
 		    ((cp0_get_prid() >> 4) & 0x0f) >= 4) /* R4400 */
 			xtlb_handler = (vaddr_t)&xtlb_miss_err_r4k;
 		else {