diff options
| author | Mark Kettenis <kettenis@cvs.openbsd.org> | 2012-08-29 20:33:17 +0000 |
|---|---|---|
| committer | Mark Kettenis <kettenis@cvs.openbsd.org> | 2012-08-29 20:33:17 +0000 |
| commit | 3dedeea696f0eea7042acc587783d890538c20c5 (patch) | |
| tree | 61f281656c57a76b9ad8f60c28e5107d986f5388 /sys/arch/sparc64/include | |
| parent | b5604b45f5e758b43e5114e50f575ca3de2b0168 (diff) | |
The low-level guts to support MTP (Multi-Threaded Processing) on the
Fujitsu SPARC64-VI and SPARC64-VII CPUs. Since the two threads on each core
share the TLBs of the core we cannot enter different mappings for the same
virtual address. Instead we use a scratch register to store the per-cpu
pointer. This is very similar to what we do on sun4v.
For now we still only attach the first thread of each SPARC64-VI/VII core
since we currently don't handle the VMT (Vertical Multi-Threading) of the
SPARC64-VI very well.
Diffstat (limited to 'sys/arch/sparc64/include')
| -rw-r--r-- | sys/arch/sparc64/include/ctlreg.h | 4 |
1 files changed, 3 insertions, 1 deletions
diff --git a/sys/arch/sparc64/include/ctlreg.h b/sys/arch/sparc64/include/ctlreg.h index 43652728816..a451e2ce00f 100644 --- a/sys/arch/sparc64/include/ctlreg.h +++ b/sys/arch/sparc64/include/ctlreg.h @@ -1,4 +1,4 @@ -/* $OpenBSD: ctlreg.h,v 1.23 2009/11/30 22:59:29 kettenis Exp $ */ +/* $OpenBSD: ctlreg.h,v 1.24 2012/08/29 20:33:16 kettenis Exp $ */ /* $NetBSD: ctlreg.h,v 1.28 2001/08/06 23:55:34 eeh Exp $ */ /* @@ -127,6 +127,8 @@ #define ASI_AFSR 0x4c /* [4u] asynchronous fault status register */ #define ASI_AFAR 0x4d /* [4u] asynchronous fault address register */ +#define ASI_SCRATCH 0x4f /* [VI] scratch registers */ + #define ASI_ICACHE_DATA 0x66 /* [4u] diagnostic access to D-cache data RAM */ #define ASI_ICACHE_TAG 0x67 /* [4u] diagnostic access to D-cache tag RAM */ #define ASI_FLUSH_I_PAGE_PRIMARY 0x68 /* [4u] flush D-cache page using primary context */ |