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authorMartin Pieuchot <mpi@cvs.openbsd.org>2017-05-27 15:11:04 +0000
committerMartin Pieuchot <mpi@cvs.openbsd.org>2017-05-27 15:11:04 +0000
commit7918eeb9bc31b1361411b91b1459769f2f782ab9 (patch)
tree63f5d20e40377dff1a2c5c97f10950cf2d700513 /sys/arch/sparc64
parent50b9150459cd5e9e117297a922c447ed329bd35f (diff)
Move SPINLOCK_SPIN_HOOK to the header used by other archs in order to
prepare the terrain for MI locks. ok kettenis@
Diffstat (limited to 'sys/arch/sparc64')
-rw-r--r--sys/arch/sparc64/include/lock.h64
-rw-r--r--sys/arch/sparc64/sparc64/lock_machdep.c46
2 files changed, 62 insertions, 48 deletions
diff --git a/sys/arch/sparc64/include/lock.h b/sys/arch/sparc64/include/lock.h
index a34bb3d7be3..5b3e63db804 100644
--- a/sys/arch/sparc64/include/lock.h
+++ b/sys/arch/sparc64/include/lock.h
@@ -1,8 +1,66 @@
-/* $OpenBSD: lock.h,v 1.10 2015/02/11 00:14:11 dlg Exp $ */
-
-/* public domain */
+/* $OpenBSD: lock.h,v 1.11 2017/05/27 15:11:03 mpi Exp $ */
+/*
+ * Copyright (c) 2012 Mark Kettenis <kettenis@openbsd.org>
+ *
+ * Permission to use, copy, modify, and distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
#ifndef _MACHINE_LOCK_H_
#define _MACHINE_LOCK_H_
+#ifdef _KERNEL
+
+/*
+ * On processors with multiple threads we force a thread switch.
+ *
+ * On UltraSPARC T2 and its successors, the optimal way to do this
+ * seems to be to do three nop reads of %ccr. This works on
+ * UltraSPARC T1 as well, even though three nop casx operations seem
+ * to be slightly more optimal. Since these instructions are
+ * effectively nops, executing them on earlier non-CMT processors is
+ * harmless, so we make this the default.
+ *
+ * On SPARC T4 and later, we can use the processor-specific pause
+ * instruction.
+ *
+ * On SPARC64 VI and its successors we execute the processor-specific
+ * sleep instruction.
+ */
+#define SPINLOCK_SPIN_HOOK \
+do { \
+ __asm volatile( \
+ "999: rd %%ccr, %%g0 \n" \
+ " rd %%ccr, %%g0 \n" \
+ " rd %%ccr, %%g0 \n" \
+ " .section .sun4v_pause_patch, \"ax\" \n" \
+ " .word 999b \n" \
+ " .word 0xb7802080 ! pause 128 \n" \
+ " .word 999b + 4 \n" \
+ " nop \n" \
+ " .word 999b + 8 \n" \
+ " nop \n" \
+ " .previous \n" \
+ " .section .sun4u_mtp_patch, \"ax\" \n" \
+ " .word 999b \n" \
+ " .word 0x81b01060 ! sleep \n" \
+ " .word 999b + 4 \n" \
+ " nop \n" \
+ " .word 999b + 8 \n" \
+ " nop \n" \
+ " .previous \n" \
+ : : : "memory"); \
+} while (0)
+
+
+#endif /* _KERNEL */
#endif /* _MACHINE_LOCK_H_ */
diff --git a/sys/arch/sparc64/sparc64/lock_machdep.c b/sys/arch/sparc64/sparc64/lock_machdep.c
index 355e5cc6fa0..4680a5fffbe 100644
--- a/sys/arch/sparc64/sparc64/lock_machdep.c
+++ b/sys/arch/sparc64/sparc64/lock_machdep.c
@@ -1,4 +1,4 @@
-/* $OpenBSD: lock_machdep.c,v 1.15 2017/05/25 03:19:39 dlg Exp $ */
+/* $OpenBSD: lock_machdep.c,v 1.16 2017/05/27 15:11:03 mpi Exp $ */
/*
* Copyright (c) 2007 Artur Grabowski <art@openbsd.org>
@@ -42,50 +42,6 @@ __mp_lock_init(struct __mp_lock *mpl)
extern int __mp_lock_spinout;
#endif
-/*
- * On processors with multiple threads we force a thread switch.
- *
- * On UltraSPARC T2 and its successors, the optimal way to do this
- * seems to be to do three nop reads of %ccr. This works on
- * UltraSPARC T1 as well, even though three nop casx operations seem
- * to be slightly more optimal. Since these instructions are
- * effectively nops, executing them on earlier non-CMT processors is
- * harmless, so we make this the default.
- *
- * On SPARC T4 and later, we can use the processor-specific pause
- * instruction.
- *
- * On SPARC64 VI and its successors we execute the processor-specific
- * sleep instruction.
- */
-static __inline void
-__mp_lock_spin_hook(void)
-{
- __asm volatile(
- "999: rd %%ccr, %%g0 \n"
- " rd %%ccr, %%g0 \n"
- " rd %%ccr, %%g0 \n"
- " .section .sun4v_pause_patch, \"ax\" \n"
- " .word 999b \n"
- " .word 0xb7802080 ! pause 128 \n"
- " .word 999b + 4 \n"
- " nop \n"
- " .word 999b + 8 \n"
- " nop \n"
- " .previous \n"
- " .section .sun4u_mtp_patch, \"ax\" \n"
- " .word 999b \n"
- " .word 0x81b01060 ! sleep \n"
- " .word 999b + 4 \n"
- " nop \n"
- " .word 999b + 8 \n"
- " nop \n"
- " .previous \n"
- : : : "memory");
-}
-
-#define SPINLOCK_SPIN_HOOK __mp_lock_spin_hook()
-
static __inline void
__mp_lock_spin(struct __mp_lock *mpl, u_int me)
{