Having common ienab_bic() and ienab_bis() entry points for sun4/4c and sun4m

is stupid, since the bits in the interrupt enable register are completely
different between 4/4c and 4m.

Instead, provide distinct, explicit function names to handle the interrupt
enable register.

5 files changed, 58 insertions, 77 deletions

diff --git a/sys/arch/sparc/sparc/autoconf.c b/sys/arch/sparc/sparc/autoconf.c
index 5473726a7c3..6aaebc18c88 100644
--- a/sys/arch/sparc/sparc/autoconf.c
+++ b/sys/arch/sparc/sparc/autoconf.c
@@ -1,4 +1,4 @@
-/*	$OpenBSD: autoconf.c,v 1.90 2010/07/01 03:20:38 matthew Exp $	*/
+/*	$OpenBSD: autoconf.c,v 1.91 2010/07/06 20:40:01 miod Exp $	*/
 /*	$NetBSD: autoconf.c,v 1.73 1997/07/29 09:41:53 fair Exp $ */
 
 /*
@@ -280,7 +280,7 @@ bootstrap()
 		setpte4m(SI_INTR_VA, pte);
 
 		/* Now disable interrupts */
-		ienab_bis(SINTR_MA);
+		intreg_set_4m(SINTR_MA);
 
 		/* Send all interrupts to primary processor */
 		*((u_int *)ICR_ITR) = 0;
@@ -312,8 +312,13 @@ bootstrap()
 	}
 #endif /* SUN4M */
 
+#if defined(SUN4) || defined(SUN4C)
 	if (CPU_ISSUN4OR4C) {
 		/* Map Interrupt Enable Register */
+		/*
+		 * XXX on non-Sun4, we ought to get the address from
+		 * XXX the `interrupt-enable' node.
+		 */
 		pmap_kenter_pa(INTRREG_VA,
 			   INT_ENABLE_REG_PHYSADR | PMAP_NC | PMAP_OBIO,
 			   VM_PROT_READ | VM_PROT_WRITE);
@@ -321,6 +326,7 @@ bootstrap()
 		/* Disable all interrupts */
 		*((unsigned char *)INTRREG_VA) = 0;
 	}
+#endif
 }
 
 /*
@@ -811,11 +817,11 @@ cpu_configure()
 	/* Enable device interrupts */
 #if defined(SUN4M)
 	if (CPU_ISSUN4M)
-		ienab_bic(SINTR_MA);
+		intreg_clr_4m(SINTR_MA);
 #endif
 #if defined(SUN4) || defined(SUN4C)
 	if (CPU_ISSUN4OR4C)
-		ienab_bis(IE_ALLIE);
+		intreg_set_44c(IE_ALLIE);
 #endif
 	(void)spl0();
 
diff --git a/sys/arch/sparc/sparc/clock.c b/sys/arch/sparc/sparc/clock.c
index 5bdae89edc7..d043e7c6834 100644
--- a/sys/arch/sparc/sparc/clock.c
+++ b/sys/arch/sparc/sparc/clock.c
@@ -1,4 +1,4 @@
-/*	$OpenBSD: clock.c,v 1.24 2006/12/10 16:12:41 miod Exp $	*/
+/*	$OpenBSD: clock.c,v 1.25 2010/07/06 20:40:01 miod Exp $	*/
 /*	$NetBSD: clock.c,v 1.52 1997/05/24 20:16:05 pk Exp $ */
 
 /*
@@ -252,7 +252,7 @@ oclockattach(parent, self, aux)
 	/* 
 	 * calibrate delay() 
 	 */
-	ienab_bic(IE_L14 | IE_L10);	/* disable all clock intrs */
+	intreg_clr_44c(IE_L14 | IE_L10);	/* disable all clock intrs */
 	for (timerblurb = 1; ; timerblurb++) {
 		volatile register char *ireg = &i7->clk_intr_reg;
 		int ival;
@@ -611,10 +611,10 @@ cpu_initclocks()
 
 		i7->clk_intr_reg = INTERSIL_INTER_CSECONDS; /* 1/100 sec */
 
-		ienab_bic(IE_L14 | IE_L10);	/* disable all clock intrs */
+		intreg_clr_44c(IE_L14 | IE_L10);/* disable all clock intrs */
 		intersil_disable(i7);		/* disable clock */
 		dummy = intersil_clear(i7);	/* clear interrupts */
-		ienab_bis(IE_L10);		/* enable l10 interrupt */
+		intreg_set_44c(IE_L10);		/* enable l10 interrupt */
 		intersil_enable(i7);		/* enable clock */
 
 		return;
@@ -653,12 +653,13 @@ cpu_initclocks()
 
 #if defined(SUN4M)
 	if (CPU_ISSUN4M)
-		ienab_bic(SINTR_T);
+		intreg_clr_4m(SINTR_T);
 #endif
 
+#if defined(SUN4) || defined(SUN4C)
 	if (CPU_ISSUN4OR4C)
-		ienab_bis(IE_L14 | IE_L10);
-
+		intreg_set_44c(IE_L14 | IE_L10);
+#endif
 }
 
 /*
@@ -673,9 +674,7 @@ setstatclockrate(newhz)
 }
 
 /*
- * Level 10 (clock) interrupts.  If we are using the FORTH PROM for
- * console input, we need to check for that here as well, and generate
- * a software interrupt to read it.
+ * Level 10 (clock) interrupts.
  */
 int
 clockintr(cap)
@@ -695,8 +694,8 @@ clockintr(cap)
 #if defined(SUN4)
 	if (oldclk) {
 		discard = intersil_clear(i7);
-		ienab_bic(IE_L10);  /* clear interrupt */
-		ienab_bis(IE_L10);  /* enable interrupt */
+		intreg_clr_44c(IE_L10);	/* clear interrupt */
+		intreg_set_44c(IE_L10);	/* enable interrupt */
 		goto forward;
 	}
 #endif
diff --git a/sys/arch/sparc/sparc/intr.c b/sys/arch/sparc/sparc/intr.c
index d13183cd2a9..80041ae3627 100644
--- a/sys/arch/sparc/sparc/intr.c
+++ b/sys/arch/sparc/sparc/intr.c
@@ -1,4 +1,4 @@
-/*	$OpenBSD: intr.c,v 1.32 2009/04/10 20:53:54 miod Exp $ */
+/*	$OpenBSD: intr.c,v 1.33 2010/07/06 20:40:01 miod Exp $ */
 /*	$NetBSD: intr.c,v 1.20 1997/07/29 09:42:03 fair Exp $ */
 
 /*
@@ -465,7 +465,7 @@ softintr_establish(int level, void (*fn)(void *), void *arg)
 	 * to be passed to raise().
 	 * On a sun4 or sun4c, the appropriate bit to set
 	 * in the interrupt enable register is stored, to be
-	 * passed to ienab_bis().
+	 * passed to intreg_set_44c().
 	 */
 	ipl = hw = level;
 #if defined(SUN4) || defined(SUN4C)
@@ -533,18 +533,25 @@ softintr_schedule(void *arg)
 	if (sih->sih_pending == 0) {
 		sih->sih_pending++;
 
+		switch (cputyp) {
+		default:
 #if defined(SUN4M)
-		if (CPU_ISSUN4M)
+		case CPU_SUN4M:
 			raise(0, sih->sih_hw);
+			break;
 #endif
 #if defined(SUN4) || defined(SUN4C)
-		if (CPU_ISSUN4OR4C)
-			ienab_bis(sih->sih_hw);
+		case CPU_SUN4:
+		case CPU_SUN4C:
+			intreg_set_44c(sih->sih_hw);
+			break;
 #endif
 #if defined(solbourne)
-		if (CPU_ISKAP)
+		case CPU_KAP:
 			ienab_bis(sih->sih_hw);
+			break;
 #endif
+		}
 	}
 	splx(s);
 }
diff --git a/sys/arch/sparc/sparc/intreg.h b/sys/arch/sparc/sparc/intreg.h
index 436977f41e4..1a8439fb9ef 100644
--- a/sys/arch/sparc/sparc/intreg.h
+++ b/sys/arch/sparc/sparc/intreg.h
@@ -1,4 +1,4 @@
-/*	$OpenBSD: intreg.h,v 1.9 2009/04/10 20:53:54 miod Exp $	*/
+/*	$OpenBSD: intreg.h,v 1.10 2010/07/06 20:40:01 miod Exp $	*/
 /*	$NetBSD: intreg.h,v 1.6 1997/07/22 20:19:10 pk Exp $ */
 
 /*
@@ -43,11 +43,13 @@
 
 #include <sparc/sparc/vaddrs.h>
 
+#if defined(SUN4) || defined(SUN4C)
+
 /*
  * sun4c interrupt enable register.
  *
- * The register is a single byte.  C code must use the ienab_bis and
- * ienab_bic functions found in locore.s.
+ * The register is a single byte.  C code must use the intreg_set_44c and
+ * intreg_clr_44c functions found in locore.s.
  *
  * The register's physical address is defined here as the register
  * must be mapped early in the boot process (otherwise NMI handling
@@ -69,21 +71,14 @@
 #define	IE_ALLIE	0x01	/* enable interrupts */
 
 #ifndef _LOCORE
-void	ienab_bis(int bis);	/* set given bits */
-void	ienab_bic(int bic);	/* clear given bits */
+void	intreg_set_44c(int);	/* set given bits */
+void	intreg_clr_44c(int);	/* clear given bits */
 #endif
 
-#if defined(SUN4M)
-#ifdef notyet
-#define IENAB_SYS	((_MAXNBPG * _MAXNCPU) + 0xc)
-#define IENAB_P0	0x0008
-#define IENAB_P1	0x1008
-#define IENAB_P2	0x2008
-#define IENAB_P3	0x3008
-#endif /* notyet */
-#endif
+#endif /* SUN4 || SUN4C */
 
 #if defined(SUN4M)
+
 /*
  * Interrupt Control Registers, located in IO space.
  * (mapped to `locore' for now..)
@@ -140,5 +135,9 @@ void	ienab_bic(int bic);	/* clear given bits */
 				"\022A\023SC\024T\025VI\065MI\027F" \
 				"\034V\035M\036I\037ME\040MA"
 
-
+#ifndef _LOCORE
+void	intreg_clr_4m(int);
+void	intreg_set_4m(int);
 #endif
+
+#endif	/* SUN4M */
diff --git a/sys/arch/sparc/sparc/locore.s b/sys/arch/sparc/sparc/locore.s
index 2f25726fb26..36d89c293be 100644
--- a/sys/arch/sparc/sparc/locore.s
+++ b/sys/arch/sparc/sparc/locore.s
@@ -1,4 +1,4 @@
-/*	$OpenBSD: locore.s,v 1.86 2010/06/29 21:28:11 miod Exp $	*/
+/*	$OpenBSD: locore.s,v 1.87 2010/07/06 20:40:01 miod Exp $	*/
 /*	$NetBSD: locore.s,v 1.73 1997/09/13 20:36:48 pk Exp $	*/
 
 /*
@@ -1840,7 +1840,7 @@ memfault_sun4c:
 	 * This code is essentially the same as that at `nmi' below,
 	 * but the register usage is different and we cannot merge.
 	 */
-	sethi	%hi(INTRREG_VA), %l5	! ienab_bic(IE_ALLIE);
+	sethi	%hi(INTRREG_VA), %l5	! intreg_clr_44c(IE_ALLIE);
 	ldub	[%l5 + %lo(INTRREG_VA)], %o0
 	andn	%o0, IE_ALLIE, %o0
 	stb	%o0, [%l5 + %lo(INTRREG_VA)]
@@ -2286,7 +2286,7 @@ return_from_syscall:
 
 /*
  * Interrupts.  Software interrupts must be cleared from the software
- * interrupt enable register.  Rather than calling ienab_bic for each,
+ * interrupt enable register.  Rather than calling intreg_clr_* for each,
  * we do them in-line before enabling traps.
  *
  * After preliminary setup work, the interrupt is passed to each
@@ -3851,8 +3851,6 @@ Lgandul:	nop
 	MUNGE(NOP_ON_4M_10)
 	MUNGE(NOP_ON_4M_11)
 	MUNGE(NOP_ON_4M_12)
-	MUNGE(NOP_ON_4M_13)
-	MUNGE(NOP_ON_4M_14)
 	b,a	2f
 
 1:
@@ -5384,34 +5382,18 @@ ENTRY(loadfpstate)
 	 ld	[%o0 + FS_FSR], %fsr	! setfsr(f->fs_fsr);
 
 /*
- * ienab_bis(bis) int bis;
- * ienab_bic(bic) int bic;
+ * intreg_set_44c(int bis);
+ * intreg_clr_44c(int bic);
  *
  * Set and clear bits in the interrupt register.
  */
 
-#if defined(SUN4M) && (defined(SUN4) || defined(SUN4C))
-ENTRY(ienab_bis)
-NOP_ON_4M_13:
-	b,a	_C_LABEL(ienab_bis_4_4c)
-	b,a	_C_LABEL(ienab_bis_4m)
-
-ENTRY(ienab_bic)
-NOP_ON_4M_14:
-	b,a	_C_LABEL(ienab_bic_4_4c)
-	b,a	_C_LABEL(ienab_bic_4m)
-#endif
-
 #if defined(SUN4) || defined(SUN4C)
 /*
  * Since there are no read-modify-write instructions for this,
  * and one of the interrupts is nonmaskable, we must disable traps.
  */
-#if defined(SUN4M)
-ENTRY(ienab_bis_4_4c)
-#else
-ENTRY(ienab_bis)
-#endif
+ENTRY(intreg_set_44c)
 	! %o0 = bits to set
 	rd	%psr, %o2
 	wr	%o2, PSR_ET, %psr	! disable traps
@@ -5425,11 +5407,7 @@ ENTRY(ienab_bis)
 	retl
 	 nop
 
-#if defined(SUN4M)
-ENTRY(ienab_bic_4_4c)
-#else
-ENTRY(ienab_bic)
-#endif
+ENTRY(intreg_clr_44c)
 	! %o0 = bits to clear
 	rd	%psr, %o2
 	wr	%o2, PSR_ET, %psr	! disable traps
@@ -5442,26 +5420,18 @@ ENTRY(ienab_bic)
 	nop
 	retl
 	 nop
-#endif
+#endif	/* SUN4 || SUN4C */
 
 #if defined(SUN4M)
 /*
  * sun4m has separate registers for clearing/setting the interrupt mask.
  */
-#if defined(SUN4) || defined(SUN4C)
-ENTRY(ienab_bis_4m)
-#else
-ENTRY(ienab_bis)
-#endif
+ENTRY(intreg_set_4m)
 	set	ICR_SI_SET, %o1
 	retl
 	 st	%o0, [%o1]
 
-#if defined(SUN4) || defined(SUN4C)
-ENTRY(ienab_bic_4m)
-#else
-ENTRY(ienab_bic)
-#endif
+ENTRY(intreg_clr_4m)
 	set	ICR_SI_CLR, %o1
 	retl
 	 st	%o0, [%o1]