Add some additional Intel CPUID values for recent and upcoming processors.

With some additions from sthen@

ok kettenis@ sthen@

4 files changed, 61 insertions, 5 deletions

diff --git a/sys/arch/amd64/amd64/identcpu.c b/sys/arch/amd64/amd64/identcpu.c
index c5063b90c25..05f04c3ba86 100644
--- a/sys/arch/amd64/amd64/identcpu.c
+++ b/sys/arch/amd64/amd64/identcpu.c
@@ -1,4 +1,4 @@
-/*	$OpenBSD: identcpu.c,v 1.26 2009/12/09 21:42:10 deraadt Exp $	*/
+/*	$OpenBSD: identcpu.c,v 1.27 2010/03/21 23:00:57 jsg Exp $	*/
 /*	$NetBSD: identcpu.c,v 1.1 2003/04/26 18:39:28 fvdl Exp $	*/
 
 /*
@@ -93,15 +93,29 @@ const struct {
 	{ CPUID_3DNOW,	"3DNOW" }
 }, cpu_cpuid_ecxfeatures[] = {
 	{ CPUIDECX_SSE3,	"SSE3" },
+	{ CPUIDECX_PCLMUL,	"PCLMUL" },
 	{ CPUIDECX_MWAIT,	"MWAIT" },
 	{ CPUIDECX_DSCPL,	"DS-CPL" },
 	{ CPUIDECX_VMX,		"VMX" },
 	{ CPUIDECX_SMX,		"SMX" },
 	{ CPUIDECX_EST,		"EST" },
 	{ CPUIDECX_TM2,		"TM2" },
+	{ CPUIDECX_SSSE3,	"SSSE3" },
 	{ CPUIDECX_CNXTID,	"CNXT-ID" },
+	{ CPUIDECX_FMA3,	"FMA3" },
 	{ CPUIDECX_CX16,	"CX16" },
-	{ CPUIDECX_XTPR,	"xTPR" }
+	{ CPUIDECX_XTPR,	"xTPR" },
+	{ CPUIDECX_PDCM,	"PDCM" },
+	{ CPUIDECX_DCA,		"DCA" },
+	{ CPUIDECX_SSE41,	"SSE4.1" },
+	{ CPUIDECX_SSE42,	"SSE4.2" },
+	{ CPUIDECX_X2APIC,	"x2APIC" },
+	{ CPUIDECX_MOVBE,	"MOVBE" },
+	{ CPUIDECX_POPCNT,	"POPCNT" },
+	{ CPUIDECX_AES,		"AES" },
+	{ CPUIDECX_XSAVE,	"XSAVE" },
+	{ CPUIDECX_OSXSAVE,	"OSXSAVE" },
+	{ CPUIDECX_AVX,		"AVX" }
 };
 
 int
diff --git a/sys/arch/amd64/include/specialreg.h b/sys/arch/amd64/include/specialreg.h
index 9ea389d0b52..cbbc8cc0bae 100644
--- a/sys/arch/amd64/include/specialreg.h
+++ b/sys/arch/amd64/include/specialreg.h
@@ -1,4 +1,4 @@
-/*	$OpenBSD: specialreg.h,v 1.17 2009/10/07 02:15:48 kevlo Exp $	*/
+/*	$OpenBSD: specialreg.h,v 1.18 2010/03/21 23:00:57 jsg Exp $	*/
 /*	$NetBSD: specialreg.h,v 1.1 2003/04/26 18:39:48 fvdl Exp $	*/
 /*	$NetBSD: x86/specialreg.h,v 1.2 2003/04/25 21:54:30 fvdl Exp $	*/
 
@@ -123,15 +123,29 @@
 #define	CPUID_SBF	0x80000000	/* signal break on FERR */
 
 #define	CPUIDECX_SSE3	0x00000001	/* streaming SIMD extensions #3 */
+#define CPUIDECX_PCLMUL	0x00000002	/* Carryless Multiplication */
 #define CPUIDECX_MWAIT	0x00000008	/* Monitor/Mwait */
 #define CPUIDECX_DSCPL	0x00000010	/* CPL Qualified Debug Store */
 #define CPUIDECX_VMX	0x00000020	/* Virtual Machine Extensions */
 #define CPUIDECX_SMX	0x00000040	/* Safer Mode Extensions */
 #define CPUIDECX_EST	0x00000080	/* enhanced SpeedStep */
 #define CPUIDECX_TM2	0x00000100	/* thermal monitor 2 */
+#define CPUIDECX_SSSE3	0x00000200	/* Supplemental Streaming SIMD Ext. 3 */
 #define CPUIDECX_CNXTID	0x00000400	/* Context ID */
+#define CPUIDECX_FMA3	0x00001000	/* Fused Multiply Add */
 #define CPUIDECX_CX16	0x00002000	/* has CMPXCHG16B instruction */
 #define CPUIDECX_XTPR	0x00004000	/* xTPR Update Control */
+#define CPUIDECX_PDCM	0x00008000	/* Perfmon and Debug Capability */
+#define CPUIDECX_DCA	0x00040000	/* Direct Cache Access */
+#define CPUIDECX_SSE41	0x00080000	/* Streaming SIMD Extensions 4.1 */
+#define CPUIDECX_SSE42	0x00100000	/* Streaming SIMD Extensions 4.2 */
+#define CPUIDECX_X2APIC	0x00200000	/* Extended xAPIC Support */
+#define CPUIDECX_MOVBE	0x00400000	/* MOVBE Instruction */
+#define CPUIDECX_POPCNT	0x00800000	/* POPCNT Instruction */
+#define CPUIDECX_AES	0x02000000	/* AES Instruction */
+#define CPUIDECX_XSAVE	0x04000000	/* XSAVE/XSTOR States */
+#define CPUIDECX_OSXSAVE	0x08000000	/* OSXSAVE */
+#define CPUIDECX_AVX	0x10000000	/* Advanced Vector Extensions */
 
 /*
  * AMD/VIA processor specific flags.
diff --git a/sys/arch/i386/i386/machdep.c b/sys/arch/i386/i386/machdep.c
index 14db05ddc26..1b8e2d8959d 100644
--- a/sys/arch/i386/i386/machdep.c
+++ b/sys/arch/i386/i386/machdep.c
@@ -1,4 +1,4 @@
-/*	$OpenBSD: machdep.c,v 1.468 2009/12/09 14:27:34 oga Exp $	*/
+/*	$OpenBSD: machdep.c,v 1.469 2010/03/21 23:00:57 jsg Exp $	*/
 /*	$NetBSD: machdep.c,v 1.214 1996/11/10 03:16:17 thorpej Exp $	*/
 
 /*-
@@ -993,15 +993,29 @@ const struct cpu_cpuid_feature i386_cpuid_features[] = {
 
 const struct cpu_cpuid_feature i386_cpuid_ecxfeatures[] = {
 	{ CPUIDECX_SSE3,	"SSE3" },
+	{ CPUIDECX_PCLMUL,	"PCLMUL" },
 	{ CPUIDECX_MWAIT,	"MWAIT" },
 	{ CPUIDECX_DSCPL,	"DS-CPL" },
 	{ CPUIDECX_VMX,		"VMX" },
 	{ CPUIDECX_SMX,		"SMX" },
 	{ CPUIDECX_EST,		"EST" },
 	{ CPUIDECX_TM2,		"TM2" },
+	{ CPUIDECX_SSSE3,	"SSSE3" },
 	{ CPUIDECX_CNXTID,	"CNXT-ID" },
+	{ CPUIDECX_FMA3,	"FMA3" },
 	{ CPUIDECX_CX16,	"CX16" },
 	{ CPUIDECX_XTPR,	"xTPR" },
+	{ CPUIDECX_PDCM,	"PDCM" },
+	{ CPUIDECX_DCA,		"DCA" },
+	{ CPUIDECX_SSE41,	"SSE4.1" },
+	{ CPUIDECX_SSE42,	"SSE4.2" },
+	{ CPUIDECX_X2APIC,	"x2APIC" },
+	{ CPUIDECX_MOVBE,	"MOVBE" },
+	{ CPUIDECX_POPCNT,	"POPCNT" },
+	{ CPUIDECX_AES,		"AES" },
+	{ CPUIDECX_XSAVE,	"XSAVE" },
+	{ CPUIDECX_OSXSAVE,	"OSXSAVE" },
+	{ CPUIDECX_AVX,		"AVX" },
 };
 
 void
diff --git a/sys/arch/i386/include/specialreg.h b/sys/arch/i386/include/specialreg.h
index c20cd56473c..2d116f57310 100644
--- a/sys/arch/i386/include/specialreg.h
+++ b/sys/arch/i386/include/specialreg.h
@@ -1,4 +1,4 @@
-/*	$OpenBSD: specialreg.h,v 1.37 2009/10/07 02:15:48 kevlo Exp $	*/
+/*	$OpenBSD: specialreg.h,v 1.38 2010/03/21 23:00:57 jsg Exp $	*/
 /*	$NetBSD: specialreg.h,v 1.7 1994/10/27 04:16:26 cgd Exp $	*/
 
 /*-
@@ -132,15 +132,29 @@
 #define CPUID_LONG	0x20000000	/* long mode (AMD64, ext cpuid) */
 
 #define CPUIDECX_SSE3	0x00000001	/* has SSE3 instructions */
+#define CPUIDECX_PCLMUL	0x00000002	/* Carryless Multiplication */
 #define CPUIDECX_MWAIT	0x00000008	/* Monitor/Mwait */
 #define CPUIDECX_DSCPL	0x00000010	/* CPL Qualified Debug Store */
 #define CPUIDECX_VMX	0x00000020	/* Virtual Machine Extensions */
 #define CPUIDECX_SMX	0x00000040	/* Safer Mode Extensions */
 #define CPUIDECX_EST	0x00000080	/* enhanced SpeedStep */
 #define CPUIDECX_TM2	0x00000100	/* thermal monitor 2 */
+#define CPUIDECX_SSSE3	0x00000200	/* Supplemental Streaming SIMD Ext. 3 */
 #define CPUIDECX_CNXTID	0x00000400	/* Context ID */
+#define CPUIDECX_FMA3	0x00001000	/* Fused Multiply Add */
 #define CPUIDECX_CX16	0x00002000	/* has CMPXCHG16B instruction */
 #define CPUIDECX_XTPR	0x00004000	/* xTPR Update Control */
+#define CPUIDECX_PDCM	0x00008000	/* Perfmon and Debug Capability */
+#define CPUIDECX_DCA	0x00040000	/* Direct Cache Access */
+#define CPUIDECX_SSE41	0x00080000	/* Streaming SIMD Extensions 4.1 */
+#define CPUIDECX_SSE42	0x00100000	/* Streaming SIMD Extensions 4.2 */
+#define CPUIDECX_X2APIC	0x00200000	/* Extended xAPIC Support */
+#define CPUIDECX_MOVBE	0x00400000	/* MOVBE Instruction */
+#define CPUIDECX_POPCNT	0x00800000	/* POPCNT Instruction */
+#define CPUIDECX_AES	0x02000000	/* AES Instruction */
+#define CPUIDECX_XSAVE	0x04000000	/* XSAVE/XSTOR States */
+#define CPUIDECX_OSXSAVE	0x08000000	/* OSXSAVE */
+#define CPUIDECX_AVX	0x10000000	/* Advanced Vector Extensions */
 
 /*
  * Model-specific registers for the i386 family