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authorMiod Vallat <miod@cvs.openbsd.org>2004-07-26 16:36:31 +0000
committerMiod Vallat <miod@cvs.openbsd.org>2004-07-26 16:36:31 +0000
commit36fdea8bf6448d484950985e7147469562aeb6ad (patch)
treea1c7fefdab493596e580b82cb628bdec62c7f3dd /sys/arch
parent8dc7425a02200fd0354b8168093fb6223df45bcd (diff)
Typos in comments.
Diffstat (limited to 'sys/arch')
-rw-r--r--sys/arch/luna88k/dev/mb89352.c6
-rw-r--r--sys/arch/luna88k/dev/mb89352reg.h4
2 files changed, 5 insertions, 5 deletions
diff --git a/sys/arch/luna88k/dev/mb89352.c b/sys/arch/luna88k/dev/mb89352.c
index 6ed3d6adceb..df64be521d7 100644
--- a/sys/arch/luna88k/dev/mb89352.c
+++ b/sys/arch/luna88k/dev/mb89352.c
@@ -1,4 +1,4 @@
-/* $OpenBSD: mb89352.c,v 1.1 2004/04/21 15:23:54 aoyama Exp $ */
+/* $OpenBSD: mb89352.c,v 1.2 2004/07/26 16:36:29 miod Exp $ */
/* $NetBSD: mb89352.c,v 1.5 2000/03/23 07:01:31 thorpej Exp $ */
/* NecBSD: mb89352.c,v 1.4 1998/03/14 07:31:20 kmatsuda Exp */
@@ -1425,10 +1425,10 @@ out:
/*
* spc_dataout_pio: perform a data transfer using the FIFO datapath in the spc
* Precondition: The SCSI bus should be in the DOUT phase, with REQ asserted
- * and ACK deasserted (i.e. waiting for a data byte)
+ * and ACK deasserted (i.e. waiting for a data byte).
*
* This new revision has been optimized (I tried) to make the common case fast,
- * and the rarer cases (as a result) somewhat more comlex
+ * and the rarer cases (as a result) somewhat more complex.
*/
int
spc_dataout_pio(sc, p, n)
diff --git a/sys/arch/luna88k/dev/mb89352reg.h b/sys/arch/luna88k/dev/mb89352reg.h
index 8e1db8ed60d..52fffcbd074 100644
--- a/sys/arch/luna88k/dev/mb89352reg.h
+++ b/sys/arch/luna88k/dev/mb89352reg.h
@@ -1,4 +1,4 @@
-/* $OpenBSD: mb89352reg.h,v 1.2 2004/04/29 14:35:20 miod Exp $ */
+/* $OpenBSD: mb89352reg.h,v 1.3 2004/07/26 16:36:29 miod Exp $ */
/* $NetBSD: mb89352reg.h,v 1.3 2003/08/07 16:31:02 agc Exp $ */
/* NecBSD: mb89352reg.h,v 1.3 1998/03/14 07:04:34 kmatsuda Exp */
@@ -100,7 +100,7 @@
#define SCMD 0x02 /* Command Register (R/W) */
#define TMOD 0x03 /* Transmit Mode Register (synch models) */
#define INTS 0x04 /* Interrupt sense (R); Interrupt Reset (W) */
-#define PSNS 0x05 /* Phase Sence (R); SPC Diagnostic Control (W) */
+#define PSNS 0x05 /* Phase Sense (R); SPC Diagnostic Control (W) */
#define SSTS 0x06 /* SPC status (R/O) */
#define SERR 0x07 /* SPC error status (R/O) */
#define PCTL 0x08 /* Phase Control (R/W) */