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authorMiod Vallat <miod@cvs.openbsd.org>2015-09-24 18:37:51 +0000
committerMiod Vallat <miod@cvs.openbsd.org>2015-09-24 18:37:51 +0000
commit3f7b3e77cfc4e58513781b309dabf35564938930 (patch)
tree098a266c96be61cb7b3fd21061993663d7a3fa09 /sys/arch
parent8940a7386ef8c3e010d9764d7899f8521049972c (diff)
IP26 streaming cache controller bus error interrupts are reported as hardware
level 4 interrupts, just like memory controller bus errors; register the tcc(4) handler with the right cause register bitmask, and teach imc(4) not to claim the interrupt if it did not trigger it.
Diffstat (limited to 'sys/arch')
-rw-r--r--sys/arch/sgi/localbus/imc.c18
-rw-r--r--sys/arch/sgi/localbus/tcc.c5
2 files changed, 17 insertions, 6 deletions
diff --git a/sys/arch/sgi/localbus/imc.c b/sys/arch/sgi/localbus/imc.c
index 367b9277e87..99e9ad0db79 100644
--- a/sys/arch/sgi/localbus/imc.c
+++ b/sys/arch/sgi/localbus/imc.c
@@ -1,4 +1,4 @@
-/* $OpenBSD: imc.c,v 1.19 2014/12/10 12:27:56 mikeb Exp $ */
+/* $OpenBSD: imc.c,v 1.20 2015/09/24 18:37:50 miod Exp $ */
/* $NetBSD: imc.c,v 1.32 2011/07/01 18:53:46 dyoung Exp $ */
/*
@@ -742,9 +742,21 @@ imc_bus_error(uint32_t hwpend, struct trap_frame *tf)
int cpuquiet = 0, gioquiet = 0;
cpustat = imc_read(IMC_CPU_ERRSTAT);
- cpuaddr = imc_read(IMC_CPU_ERRADDR);
giostat = imc_read(IMC_GIO_ERRSTAT);
- gioaddr = imc_read(IMC_GIO_ERRADDR);
+
+ if (sys_config.system_type == SGI_IP26) {
+ /*
+ * We are sharing the bus error interrupt with the streaming
+ * cache controller. This interrupt might not be ours.
+ */
+ if (cpustat == 0 && giostat == 0)
+ return 0;
+ }
+
+ if (cpustat != 0)
+ cpuaddr = imc_read(IMC_CPU_ERRADDR);
+ if (giostat != 0)
+ gioaddr = imc_read(IMC_GIO_ERRADDR);
switch (sys_config.system_type) {
case SGI_IP28:
diff --git a/sys/arch/sgi/localbus/tcc.c b/sys/arch/sgi/localbus/tcc.c
index fdce1bc822f..5b18db1c7d6 100644
--- a/sys/arch/sgi/localbus/tcc.c
+++ b/sys/arch/sgi/localbus/tcc.c
@@ -1,4 +1,4 @@
-/* $OpenBSD: tcc.c,v 1.6 2015/09/20 12:49:15 miod Exp $ */
+/* $OpenBSD: tcc.c,v 1.7 2015/09/24 18:37:50 miod Exp $ */
/*
* Copyright (c) 2012 Miodrag Vallat.
@@ -79,7 +79,7 @@ tcc_attach(struct device *parent, struct device *self, void *aux)
tcc_bus_reset();
/* Enable bus error and machine check interrupts. */
- set_intr(INTPRI_BUSERR_TCC, CR_BERR, tcc_bus_error);
+ set_intr(INTPRI_BUSERR_TCC, CR_INT_4, tcc_bus_error);
tcc_write(TCC_INTR, TCC_INTR_MCHECK_ENAB | TCC_INTR_BERR_ENAB);
/* Enable all cache sets. */
@@ -121,7 +121,6 @@ tcc_bus_error(uint32_t hwpend, struct trap_frame *tf)
(intr & (TCC_INTR_MCHECK | TCC_INTR_BERR)));
tcc_write(TCC_ERROR, errack);
- cp0_reset_cause(CR_BERR);
return hwpend;
}