Convert to bus_space; but it still uses kvtop()...

3 files changed, 626 insertions, 943 deletions

diff --git a/sys/arch/mvme88k/dev/vs.c b/sys/arch/mvme88k/dev/vs.c
index c60e08d6f0e..04eded4d60d 100644
--- a/sys/arch/mvme88k/dev/vs.c
+++ b/sys/arch/mvme88k/dev/vs.c
@@ -1,6 +1,7 @@
-/*	$OpenBSD: vs.c,v 1.37 2004/05/21 10:24:42 miod Exp $ */
+/*	$OpenBSD: vs.c,v 1.38 2004/05/22 19:34:12 miod Exp $	*/
 
 /*
+ * Copyright (c) 2004, Miodrag Vallat.
  * Copyright (c) 1999 Steve Murphree, Jr.
  * Copyright (c) 1990 The Regents of the University of California.
  * All rights reserved.
@@ -34,7 +35,7 @@
  */
 
 /*
- * MVME328S scsi adaptor driver
+ * MVME328S SCSI adaptor driver
  */
 
 /* This card lives in D16 space */
@@ -90,13 +91,14 @@ struct cfdriver vs_cd = {
 int	do_vspoll(struct vs_softc *, int, int);
 void	thaw_queue(struct vs_softc *, int);
 M328_SG	vs_alloc_scatter_gather(void);
-M328_SG	vs_build_memory_structure(struct scsi_xfer *, M328_IOPB *);
+M328_SG	vs_build_memory_structure(struct vs_softc *, struct scsi_xfer *,
+	    bus_addr_t);
 int	vs_checkintr(struct vs_softc *, struct scsi_xfer *, int *);
 void	vs_chksense(struct scsi_xfer *);
 void	vs_dealloc_scatter_gather(M328_SG);
 int	vs_eintr(void *);
-M328_CQE *vs_getcqe(struct vs_softc *);
-M328_IOPB *vs_getiopb(struct vs_softc *);
+bus_addr_t vs_getcqe(struct vs_softc *);
+bus_addr_t vs_getiopb(struct vs_softc *);
 int	vs_initialize(struct vs_softc *);
 int	vs_intr(struct vs_softc *);
 void	vs_link_sg_element(sg_list_element_t *, vaddr_t, int);
@@ -110,34 +112,28 @@ void	vs_scsidone(struct vs_softc *, struct scsi_xfer *, int);
 static __inline__ void vs_clear_return_info(struct vs_softc *);
 
 int
-vsmatch(pdp, vcf, args)
-	struct device *pdp;
-	void *vcf, *args;
+vsmatch(struct device *device, void *cf, void *args)
 {
 	struct confargs *ca = args;
 	bus_space_tag_t iot = ca->ca_iot;
 	bus_space_handle_t ioh;
 	int rc;
 
-	if (bus_space_map(iot, ca->ca_paddr, PAGE_SIZE, 0, &ioh) != 0)
+	if (bus_space_map(iot, ca->ca_paddr, S_SHORTIO, 0, &ioh) != 0)
 		return 0;
 	rc = badvaddr((vaddr_t)bus_space_vaddr(iot, ioh), 1);
-	bus_space_unmap(iot, ioh, PAGE_SIZE);
+	bus_space_unmap(iot, ioh, S_SHORTIO);
 
 	return rc == 0;
 }
 
 void
-vsattach(parent, self, args)
-	struct device *parent, *self;
-	void *args;
+vsattach(struct device *parent, struct device *self, void *args)
 {
 	struct vs_softc *sc = (struct vs_softc *)self;
 	struct confargs *ca = args;
 	int evec;
 	int tmp;
-	bus_space_tag_t iot = ca->ca_iot;
-	bus_space_handle_t ioh;
 
 	/* get the next available vector for the error interrupt */
 	evec = vme_findvec(ca->ca_vec);
@@ -149,15 +145,16 @@ vsattach(parent, self, args)
 	if (ca->ca_ipl < 0)
 		ca->ca_ipl = IPL_BIO;
 
-	if (bus_space_map(iot, ca->ca_paddr, PAGE_SIZE, 0, &ioh) != 0) {
+	printf(" vec 0x%x", evec);
+
+	sc->sc_paddr = ca->ca_paddr;
+	sc->sc_iot = ca->ca_iot;
+	if (bus_space_map(sc->sc_iot, sc->sc_paddr, S_SHORTIO, 0,
+	    &sc->sc_ioh) != 0) {
 		printf(": can't map registers!\n");
 		return;
 	}
 
-	printf(" vec 0x%x", evec);
-
-	sc->sc_vsreg = (void *)bus_space_vaddr(iot, ioh);
-
 	sc->sc_ipl = ca->ca_ipl;
 	sc->sc_nvec = ca->ca_vec;
 	sc->sc_evec = evec;
@@ -191,24 +188,23 @@ vsattach(parent, self, args)
 	 * (see dk_establish).
 	 */
 	tmp = bootpart;
-	if (ca->ca_paddr != bootaddr)
+	if (sc->sc_paddr != bootaddr)
 		bootpart = -1;		/* invalid flag to dk_establish */
 	config_found(self, &sc->sc_link, scsiprint);
 	bootpart = tmp;		    /* restore old value */
 }
 
 int
-do_vspoll(sc, to, canreset)
-	struct vs_softc *sc;
-	int to;
-	int canreset;
+do_vspoll(struct vs_softc *sc, int to, int canreset)
 {
 	int i;
+	int crsw;
+
 	if (to <= 0 ) to = 50000;
 	/* use cmd_wait values? */
 	i = 10000;
 
-	while (!(CRSW & (M_CRSW_CRBV | M_CRSW_CC))) {
+	while (((crsw = CRSW) & (M_CRSW_CRBV | M_CRSW_CC)) == 0) {
 		if (--i <= 0) {
 			i = 50000;
 			--to;
@@ -217,7 +213,8 @@ do_vspoll(sc, to, canreset)
 					vs_reset(sc);
 					vs_resync(sc);
 				}
-				printf ("timed out: timeout %d crsw 0x%x\n", to, CRSW);
+				printf("%s: timeout %d crsw 0x%x\n",
+				    sc->sc_dev.dv_xname, to, crsw);
 				return 1;
 			}
 		}
@@ -226,9 +223,7 @@ do_vspoll(sc, to, canreset)
 }
 
 int
-vs_poll(sc, xs)
-	struct vs_softc *sc;
-	struct scsi_xfer *xs;
+vs_poll(struct vs_softc *sc, struct scsi_xfer *xs)
 {
 	int status;
 	int to;
@@ -261,9 +256,7 @@ vs_poll(sc, xs)
 }
 
 void
-thaw_queue(sc, target)
-	struct vs_softc *sc;
-	int target;
+thaw_queue(struct vs_softc *sc, int target)
 {
 	THAW(target);
 
@@ -273,10 +266,7 @@ thaw_queue(sc, target)
 }
 
 void
-vs_scsidone(sc, xs, stat)
-	struct vs_softc *sc;
-	struct scsi_xfer *xs;
-	int stat;
+vs_scsidone(struct vs_softc *sc, struct scsi_xfer *xs, int stat)
 {
 	int tgt;
 	xs->status = stat;
@@ -296,41 +286,38 @@ vs_scsidone(sc, xs, stat)
 }
 
 int
-vs_scsicmd(xs)
-	struct scsi_xfer *xs;
+vs_scsicmd(struct scsi_xfer *xs)
 {
 	struct scsi_link *slp = xs->sc_link;
 	struct vs_softc *sc = slp->adapter_softc;
 	int flags, option;
 	unsigned int iopb_len;
-	M328_CQE *mc = (M328_CQE*)&sc->sc_vsreg->sh_MCE;
-	M328_CRB *crb = (M328_CRB *)&sc->sc_vsreg->sh_CRB;
-	M328_IOPB *miopb = (M328_IOPB *)&sc->sc_vsreg->sh_MCE_IOPB;
-	M328_CQE *cqep;
-	M328_IOPB *iopb;
+	bus_addr_t cqep, iopb;
 	M328_CMD *m328_cmd;
 
 	flags = xs->flags;
 	if (flags & SCSI_POLL) {
-		cqep = mc;
-		iopb = miopb;
+		cqep = sh_MCE;
+		iopb = sh_MCE_IOPB;
 	} else {
 		cqep = vs_getcqe(sc);
-		if (cqep == NULL) {
+		if (cqep == 0) {
 			xs->error = XS_DRIVER_STUFFUP;
 			return (TRY_AGAIN_LATER);
 		}
 		iopb = vs_getiopb(sc);
 	}
 
-	d16_bzero(iopb, sizeof(M328_IOPB));
+	vs_bzero(iopb, IOPB_LONG_SIZE);
+
+	iopb_len = IOPB_SHORT_SIZE + xs->cmdlen;
+	bus_space_write_region_1(sc->sc_iot, sc->sc_ioh, iopb + IOPB_SCSI_DATA,
+	    (u_int8_t *)xs->cmd, xs->cmdlen);
 
-	iopb_len = sizeof(M328_short_IOPB) + xs->cmdlen;
-	d16_bcopy(xs->cmd, &iopb->iopb_SCSI[0], xs->cmdlen);
-	iopb->iopb_CMD = IOPB_SCSI;
-	iopb->iopb_UNIT = (slp->lun << 3) | slp->target;
-	iopb->iopb_NVCT = (u_char)sc->sc_nvec;
-	iopb->iopb_EVCT = (u_char)sc->sc_evec;
+	vs_write(2, iopb + IOPB_CMD, IOPB_PASSTHROUGH);
+	vs_write(2, iopb + IOPB_UNIT, (slp->lun << 3) | slp->target);
+	vs_write(1, iopb + IOPB_NVCT, sc->sc_nvec);
+	vs_write(1, iopb + IOPB_EVCT, sc->sc_evec);
 
 	/*
 	 * Since the 88k doesn't support cache snooping, we have
@@ -339,47 +326,47 @@ vs_scsicmd(xs)
 	 */
 	dma_cachectl((vaddr_t)xs->data, xs->datalen,
 	    flags & SCSI_DATA_IN ? DMA_CACHE_SYNC_INVAL : DMA_CACHE_SYNC);
-
+	
 	option = 0;
-	if (flags & SCSI_DATA_IN)
-		option |= OPT_READ;
 	if (flags & SCSI_DATA_OUT)
-		option |= OPT_WRITE;
+		option |= M_OPT_DIR;
 
 	if (flags & SCSI_POLL) {
-		iopb->iopb_OPTION = option | OPT_INTDIS;
-		iopb->iopb_LEVEL = 0;
+		vs_write(2, iopb + IOPB_OPTION, option);
+		vs_write(2, iopb + IOPB_LEVEL, 0);
 	} else {
-		iopb->iopb_OPTION = option | OPT_INTEN;
-		iopb->iopb_LEVEL = sc->sc_ipl;
+		vs_write(2, iopb + IOPB_OPTION, option | M_OPT_IE);
+		vs_write(2, iopb + IOPB_LEVEL, sc->sc_ipl);
 	}
-	iopb->iopb_ADDR = ADDR_MOD;
+	vs_write(2, iopb + IOPB_ADDR, ADDR_MOD);
 
 	/*
 	 * Wait until we can use the command queue entry.
 	 * Should only have to wait if the master command
 	 * queue entry is busy and we are polling.
 	 */
-	while (cqep->cqe_QECR & M_QECR_GO);
+	while (vs_read(2, cqep + CQE_QECR) & M_QECR_GO)
+		;
 
-	cqep->cqe_IOPB_ADDR = OFF(iopb);
-	cqep->cqe_IOPB_LENGTH = iopb_len;
-	cqep->cqe_WORK_QUEUE = flags & SCSI_POLL ? 0 : slp->target + 1;
+	vs_write(2, cqep + CQE_IOPB_ADDR, iopb);
+	vs_write(1, cqep + CQE_IOPB_LENGTH, iopb_len);
+	vs_write(1, cqep + CQE_WORK_QUEUE,
+	    flags & SCSI_POLL ? 0 : slp->target + 1);
 
 	MALLOC(m328_cmd, M328_CMD*, sizeof(M328_CMD), M_DEVBUF, M_WAITOK);
 
 	m328_cmd->xs = xs;
 	if (xs->datalen != 0)
-		m328_cmd->top_sg_list = vs_build_memory_structure(xs, iopb);
+		m328_cmd->top_sg_list = vs_build_memory_structure(sc, xs, iopb);
 	else
 		m328_cmd->top_sg_list = NULL;
 
-	LV(cqep->cqe_CTAG, m328_cmd);
+	vs_write(4, cqep + CQE_CTAG, (u_int32_t)m328_cmd);
 
-	if (crb->crb_CRSW & M_CRSW_AQ) {
-		cqep->cqe_QECR = M_QECR_AA;
-	}
-	cqep->cqe_QECR |= M_QECR_GO;
+	if (crb_read(2, CRB_CRSW) & M_CRSW_AQ)
+		vs_write(2, cqep + CQE_QECR, M_QECR_AA);
+
+	vs_write(2, cqep + CQE_QECR, vs_read(2, cqep + CQE_QECR) | M_QECR_GO);
 
 	if (flags & SCSI_POLL) {
 		/* poll for the command to complete */
@@ -390,16 +377,12 @@ vs_scsicmd(xs)
 }
 
 void
-vs_chksense(xs)
-	struct scsi_xfer *xs;
+vs_chksense(struct scsi_xfer *xs)
 {
 	int s;
 	struct scsi_link *slp = xs->sc_link;
 	struct vs_softc *sc = slp->adapter_softc;
 	struct scsi_sense *ss;
-	M328_CQE *mc = (M328_CQE*)&sc->sc_vsreg->sh_MCE;
-	M328_IOPB *riopb = (M328_IOPB *)&sc->sc_vsreg->sh_RET_IOPB;
-	M328_IOPB *miopb = (M328_IOPB *)&sc->sc_vsreg->sh_MCE_IOPB;
 
 	/* ack and clear the error */
 	if (CRSW & M_CRSW_ER)
@@ -407,156 +390,140 @@ vs_chksense(xs)
 	CRB_CLR_DONE;
 	xs->status = 0;
 
-	d16_bzero(miopb, sizeof(M328_IOPB));
+	vs_bzero(sh_MCE_IOPB, IOPB_LONG_SIZE);
 	/* This is a command, so point to it */
-	ss = (void *)&miopb->iopb_SCSI[0];
-	d16_bzero(ss, sizeof(*ss));
+	ss = (void *)(bus_space_vaddr(sc->sc_iot, sc->sc_ioh) +
+	    sh_MCE_IOPB + IOPB_SCSI_DATA);
 	ss->opcode = REQUEST_SENSE;
 	ss->byte2 = slp->lun << 5;
 	ss->length = sizeof(struct scsi_sense_data);
 
-	miopb->iopb_CMD = IOPB_SCSI;
-	miopb->iopb_OPTION = OPT_READ;
-	miopb->iopb_NVCT = (u_char)sc->sc_nvec;
-	miopb->iopb_EVCT = (u_char)sc->sc_evec;
-	miopb->iopb_LEVEL = 0; /*sc->sc_ipl;*/
-	miopb->iopb_ADDR = ADDR_MOD;
-	LV(miopb->iopb_BUFF, kvtop((vaddr_t)&xs->sense));
-	LV(miopb->iopb_LENGTH, sizeof(struct scsi_sense_data));
-
-	d16_bzero(mc, sizeof(M328_CQE));
-	mc->cqe_IOPB_ADDR = OFF(miopb);
-	mc->cqe_IOPB_LENGTH = sizeof(M328_short_IOPB) +
-			      sizeof(struct scsi_sense);
-	mc->cqe_WORK_QUEUE = 0;
-	mc->cqe_QECR = M_QECR_GO;
+	mce_iopb_write(2, IOPB_CMD, IOPB_PASSTHROUGH);
+	mce_iopb_write(2, IOPB_OPTION, 0);
+	mce_iopb_write(1, IOPB_NVCT, sc->sc_nvec);
+	mce_iopb_write(1, IOPB_EVCT, sc->sc_evec);
+	mce_iopb_write(2, IOPB_LEVEL, 0 /* sc->sc_ipl */);
+	mce_iopb_write(2, IOPB_ADDR, ADDR_MOD);
+	mce_iopb_write(4, IOPB_BUFF, kvtop((vaddr_t)&xs->sense));
+	mce_iopb_write(4, IOPB_LENGTH, sizeof(struct scsi_sense_data));
+
+	vs_bzero(sh_MCE, CQE_SIZE);
+	mce_write(2, CQE_IOPB_ADDR, sh_MCE_IOPB);
+	mce_write(1, CQE_IOPB_LENGTH,
+	    IOPB_SHORT_SIZE + sizeof(struct scsi_sense));
+	mce_write(1, CQE_WORK_QUEUE, 0);
+	mce_write(2, CQE_QECR, M_QECR_GO);
 
 	/* poll for the command to complete */
 	s = splbio();
 	do_vspoll(sc, 0, 1);
-	xs->status = riopb->iopb_STATUS >> 8;
+	xs->status = vs_read(2, sh_RET_IOPB + IOPB_STATUS) >> 8;
 	splx(s);
 }
 
-M328_CQE *
-vs_getcqe(sc)
-	struct vs_softc *sc;
+bus_addr_t
+vs_getcqe(struct vs_softc *sc)
 {
-	M328_MCSB *mcsb = (M328_MCSB *)&sc->sc_vsreg->sh_MCSB;
-	M328_CQE *cqep;
+	bus_addr_t cqep;
 	int qhdp;
 
-	qhdp = mcsb->mcsb_QHDP;
-	cqep = (M328_CQE *)&sc->sc_vsreg->sh_CQE[qhdp];
+	qhdp = mcsb_read(2, MCSB_QHDP);
+	cqep = sh_CQE(qhdp);
 
-	if (cqep->cqe_QECR & M_QECR_GO) {
+	if (vs_read(2, cqep + CQE_QECR) & M_QECR_GO) {
 		/* should never happen */
-		return NULL;
+		return 0;
 	}
 
 	if (++qhdp == NUM_CQE)
 		qhdp = 0;
-	mcsb->mcsb_QHDP = qhdp;
+	mcsb_write(2, MCSB_QHDP, qhdp);
 
-	d16_bzero(cqep, sizeof(M328_CQE));
+	vs_bzero(cqep, CQE_SIZE);
 	return cqep;
 }
 
-M328_IOPB *
-vs_getiopb(sc)
-	struct vs_softc *sc;
+bus_addr_t
+vs_getiopb(struct vs_softc *sc)
 {
-	M328_MCSB *mcsb = (M328_MCSB *)&sc->sc_vsreg->sh_MCSB;
-	M328_IOPB *iopb;
+	bus_addr_t iopb;
 	int qhdp;
 
 	/*
 	 * Since we are always invoked after vs_getcqe(), qhdp has already
 	 * been incremented...
 	 */
-	qhdp = mcsb->mcsb_QHDP;
+	qhdp = mcsb_read(2, MCSB_QHDP);
 	if (--qhdp < 0)
 		qhdp = NUM_CQE - 1;
 
-	iopb = (M328_IOPB *)&sc->sc_vsreg->sh_IOPB[qhdp];
+	iopb = sh_IOPB(qhdp);
 	return iopb;
 }
 
 int
-vs_initialize(sc)
-	struct vs_softc *sc;
+vs_initialize(struct vs_softc *sc)
 {
-	M328_CIB *cib = (M328_CIB *)&sc->sc_vsreg->sh_CIB;
-	M328_CQE *mc = (M328_CQE*)&sc->sc_vsreg->sh_MCE;
-	M328_CRB *crb = (M328_CRB *)&sc->sc_vsreg->sh_CRB;
-	M328_IOPB *riopb = (M328_IOPB *)&sc->sc_vsreg->sh_RET_IOPB;
-	M328_MCSB *mcsb = (M328_MCSB *)&sc->sc_vsreg->sh_MCSB;
-	M328_IOPB *iopb;
-	M328_WQCF *wiopb = (M328_WQCF *)&sc->sc_vsreg->sh_MCE_IOPB;
 	int i;
 
 	CRB_CLR_DONE;
-	mcsb->mcsb_QHDP = 0;
-
-	d16_bzero(cib, sizeof(M328_CIB));
-	cib->cib_NCQE = 10;
-	cib->cib_BURST = 0;
-	cib->cib_NVECT = (sc->sc_ipl << 8) | sc->sc_nvec;
-	cib->cib_EVECT = (sc->sc_ipl << 8) | sc->sc_evec;
-	cib->cib_PID = 0x07;
-	cib->cib_SID = 0x00;
-	cib->cib_CRBO = OFF(crb);
-	cib->cib_SELECT_msw = HI(SELECTION_TIMEOUT);
-	cib->cib_SELECT_lsw = LO(SELECTION_TIMEOUT);
-	cib->cib_WQ0TIMO_msw = HI(4);
-	cib->cib_WQ0TIMO_lsw = LO(4);
-	cib->cib_VMETIMO_msw = 0; /*HI(VME_BUS_TIMEOUT);*/
-	cib->cib_VMETIMO_lsw = 0; /*LO(VME_BUS_TIMEOUT);*/
-	cib->cib_ERR_FLGS = M_ERRFLGS_RIN | M_ERRFLGS_RSE;
-	cib->cib_SBRIV = (sc->sc_ipl << 8) | sc->sc_evec;
-	cib->cib_SOF0 = 0x15;
-	cib->cib_SRATE0 = 100 / 4;
-	cib->cib_SOF1 = 0x0;
-	cib->cib_SRATE1 = 0x0;
-
-	iopb = (M328_IOPB *)&sc->sc_vsreg->sh_MCE_IOPB;
-	d16_bzero(iopb, sizeof(M328_IOPB));
-	iopb->iopb_CMD = CNTR_INIT;
-	iopb->iopb_OPTION = 0;
-	iopb->iopb_NVCT = (u_char)sc->sc_nvec;
-	iopb->iopb_EVCT = (u_char)sc->sc_evec;
-	iopb->iopb_LEVEL = 0; /*sc->sc_ipl;*/
-	iopb->iopb_ADDR = SHIO_MOD;
-	LV(iopb->iopb_BUFF, OFF(cib));
-	LV(iopb->iopb_LENGTH, sizeof(M328_CIB));
-
-	d16_bzero(mc, sizeof(M328_CQE));
-	mc->cqe_IOPB_ADDR = OFF(iopb);
-	mc->cqe_IOPB_LENGTH = sizeof(M328_IOPB);
-	mc->cqe_WORK_QUEUE = 0;
-	mc->cqe_QECR = M_QECR_GO;
+	mcsb_write(2, MCSB_QHDP, 0);
+
+	vs_bzero(sh_CIB, CIB_SIZE);
+	cib_write(2, CIB_NCQE, NUM_CQE);
+	cib_write(2, CIB_BURST, 0);
+	cib_write(2, CIB_NVECT, (sc->sc_ipl << 8) | sc->sc_nvec);
+	cib_write(2, CIB_EVECT, (sc->sc_ipl << 8) | sc->sc_evec);
+	cib_write(2, CIB_PID, 7);
+	cib_write(2, CIB_SID, 0);
+	cib_write(2, CIB_CRBO, sh_CRB);
+	cib_write(4, CIB_SELECT, SELECTION_TIMEOUT);
+	cib_write(4, CIB_WQTIMO, 4);
+	cib_write(4, CIB_VMETIMO, 0 /* VME_BUS_TIMEOUT */);
+	cib_write(2, CIB_ERR_FLGS, M_ERRFLGS_RIN | M_ERRFLGS_RSE);
+	cib_write(2, CIB_SBRIV, (sc->sc_ipl << 8) | sc->sc_evec);
+	cib_write(1, CIB_SOF0, 0x15);
+	cib_write(1, CIB_SRATE0, 100 / 4);
+	cib_write(1, CIB_SOF1, 0);
+	cib_write(1, CIB_SRATE1, 0);
+
+	vs_bzero(sh_MCE_IOPB, IOPB_LONG_SIZE);
+	mce_iopb_write(2, IOPB_CMD, CNTR_INIT);
+	mce_iopb_write(2, IOPB_OPTION, 0);
+	mce_iopb_write(1, IOPB_NVCT, sc->sc_nvec);
+	mce_iopb_write(1, IOPB_EVCT, sc->sc_evec);
+	mce_iopb_write(2, IOPB_LEVEL, 0 /* sc->sc_ipl */);
+	mce_iopb_write(2, IOPB_ADDR, SHIO_MOD);
+	mce_iopb_write(4, IOPB_BUFF, sh_CIB);
+	mce_iopb_write(4, IOPB_LENGTH, CIB_SIZE);
+
+	vs_bzero(sh_MCE, CQE_SIZE);
+	mce_write(2, CQE_IOPB_ADDR, sh_MCE_IOPB);
+	mce_write(1, CQE_IOPB_LENGTH, IOPB_LONG_SIZE);
+	mce_write(1, CQE_WORK_QUEUE, 0);
+	mce_write(2, CQE_QECR, M_QECR_GO);
 
 	/* poll for the command to complete */
 	do_vspoll(sc, 0, 1);
 
 	/* initialize work queues */
 	for (i = 1; i < 8; i++) {
-		d16_bzero(wiopb, sizeof(M328_IOPB));
-		wiopb->wqcf_CMD = CNTR_INIT_WORKQ;
-		wiopb->wqcf_OPTION = 0;
-		wiopb->wqcf_NVCT = (u_char)sc->sc_nvec;
-		wiopb->wqcf_EVCT = (u_char)sc->sc_evec;
-		wiopb->wqcf_ILVL = 0; /*sc->sc_ipl;*/
-		wiopb->wqcf_WORKQ = i;
-		wiopb->wqcf_WOPT = (WQO_FOE | WQO_INIT);
-		wiopb->wqcf_SLOTS = JAGUAR_MAX_Q_SIZ;
-		LV(wiopb->wqcf_CMDTO, 4); /* 1 second */
-
-		d16_bzero(mc, sizeof(M328_CQE));
-		mc->cqe_IOPB_ADDR = OFF(wiopb);
-		mc->cqe_IOPB_LENGTH = sizeof(M328_IOPB);
-		mc->cqe_WORK_QUEUE = 0;
-		mc->cqe_QECR = M_QECR_GO;
+		vs_bzero(sh_MCE_IOPB, IOPB_LONG_SIZE);
+		mce_iopb_write(2, WQCF_CMD, CNTR_INIT_WORKQ);
+		mce_iopb_write(2, WQCF_OPTION, 0);
+		mce_iopb_write(1, WQCF_NVCT, sc->sc_nvec);
+		mce_iopb_write(1, WQCF_EVCT, sc->sc_evec);
+		mce_iopb_write(2, WQCF_ILVL, 0 /* sc->sc_ipl */);
+		mce_iopb_write(2, WQCF_WORKQ, i);
+		mce_iopb_write(2, WQCF_WOPT, M_WOPT_FE | M_WOPT_IWQ);
+		mce_iopb_write(2, WQCF_SLOTS, JAGUAR_MAX_Q_SIZ);
+		mce_iopb_write(4, WQCF_CMDTO, 4);	/* 1 second */
+
+		vs_bzero(sh_MCE, CQE_SIZE);
+		mce_write(2, CQE_IOPB_ADDR, sh_MCE_IOPB);
+		mce_write(1, CQE_IOPB_LENGTH, IOPB_LONG_SIZE);
+		mce_write(1, CQE_WORK_QUEUE, 0);
+		mce_write(2, CQE_QECR, M_QECR_GO);
 
 		/* poll for the command to complete */
 		do_vspoll(sc, 0, 1);
@@ -569,13 +536,14 @@ vs_initialize(sc)
 	}
 
 	/* start queue mode */
-	mcsb->mcsb_MCR |= M_MCR_SQM;
+	mcsb_write(2, MCSB_MCR, mcsb_read(2, MCSB_MCR) | M_MCR_SQM);
 
 	do_vspoll(sc, 0, 1);
 	if (CRSW & M_CRSW_ER) {
-		printf("error: status = 0x%x\n", riopb->iopb_STATUS);
+		printf("initialization error, status = 0x%x\n",
+		    vs_read(2, sh_RET_IOPB + IOPB_STATUS));
 		CRB_CLR_DONE;
-		return (1);
+		return 1;
 	}
 	CRB_CLR_DONE;
 
@@ -583,32 +551,29 @@ vs_initialize(sc)
 	vs_reset(sc);
 	/* sync all devices */
 	vs_resync(sc);
-	printf(": target %d\n", sc->sc_link.adapter_target);
-	return (0);
+	printf(": SCSI ID %d\n", sc->sc_link.adapter_target);
+	return 0;
 }
 
 void
-vs_resync(sc)
-	struct vs_softc *sc;
+vs_resync(struct vs_softc *sc)
 {
-	M328_CQE *mc = (M328_CQE*)&sc->sc_vsreg->sh_MCE;
-	M328_DRCF *devreset = (M328_DRCF *)&sc->sc_vsreg->sh_MCE_IOPB;
 	int i;
 
 	for (i = 0; i < 7; i++) {
-		d16_bzero(devreset, sizeof(M328_DRCF));
-		devreset->drcf_CMD = CNTR_DEV_REINIT;
-		devreset->drcf_OPTION = 0x00;	    /* no interrupts yet... */
-		devreset->drcf_NVCT = sc->sc_nvec;
-		devreset->drcf_EVCT = sc->sc_evec;
-		devreset->drcf_ILVL = 0;
-		devreset->drcf_UNIT = i;
-
-		d16_bzero(mc, sizeof(M328_CQE));
-		mc->cqe_IOPB_ADDR = OFF(devreset);
-		mc->cqe_IOPB_LENGTH = sizeof(M328_DRCF);
-		mc->cqe_WORK_QUEUE = 0;
-		mc->cqe_QECR = M_QECR_GO;
+		vs_bzero(sh_MCE_IOPB, IOPB_SHORT_SIZE);
+		mce_iopb_write(2, DRCF_CMD, CNTR_DEV_REINIT);
+		mce_iopb_write(2, DRCF_OPTION, 0); /* no interrupts yet */
+		mce_iopb_write(1, DRCF_NVCT, sc->sc_nvec);
+		mce_iopb_write(1, DRCF_EVCT, sc->sc_evec);
+		mce_iopb_write(2, DRCF_ILVL, 0);
+		mce_iopb_write(2, DRCF_UNIT, i);
+
+		vs_bzero(sh_MCE, CQE_SIZE);
+		mce_write(2, CQE_IOPB_ADDR, sh_MCE_IOPB);
+		mce_write(1, CQE_IOPB_LENGTH, IOPB_SHORT_SIZE);
+		mce_write(1, CQE_WORK_QUEUE, 0);
+		mce_write(2, CQE_QECR, M_QECR_GO);
 
 		/* poll for the command to complete */
 		do_vspoll(sc, 0, 0);
@@ -619,29 +584,25 @@ vs_resync(sc)
 }
 
 void
-vs_reset(sc)
-	struct vs_softc *sc;
+vs_reset(struct vs_softc *sc)
 {
-	u_int s;
-	M328_CQE *mc = (M328_CQE*)&sc->sc_vsreg->sh_MCE;
-	M328_IOPB *riopb = (M328_IOPB *)&sc->sc_vsreg->sh_RET_IOPB;
-	M328_SRCF *reset = (M328_SRCF *)&sc->sc_vsreg->sh_MCE_IOPB;
+	int s;
 
 	s = splbio();
 
-	d16_bzero(reset, sizeof(M328_SRCF));
-	reset->srcf_CMD = IOPB_RESET;
-	reset->srcf_OPTION = 0x00;	 /* no interrupts yet... */
-	reset->srcf_NVCT = sc->sc_nvec;
-	reset->srcf_EVCT = sc->sc_evec;
-	reset->srcf_ILVL = 0;
-	reset->srcf_BUSID = 0;
+	vs_bzero(sh_MCE_IOPB, IOPB_SHORT_SIZE);
+	mce_iopb_write(2, SRCF_CMD, IOPB_RESET);
+	mce_iopb_write(2, SRCF_OPTION, 0);	/* not interrupts yet... */
+	mce_iopb_write(1, SRCF_NVCT, sc->sc_nvec);
+	mce_iopb_write(1, SRCF_EVCT, sc->sc_evec);
+	mce_iopb_write(2, SRCF_ILVL, 0);
+	mce_iopb_write(2, SRCF_BUSID, 0);
 
-	d16_bzero(mc, sizeof(M328_CQE));
-	mc->cqe_IOPB_ADDR = OFF(reset);
-	mc->cqe_IOPB_LENGTH = sizeof(M328_SRCF);
-	mc->cqe_WORK_QUEUE = 0;
-	mc->cqe_QECR = M_QECR_GO;
+	vs_bzero(sh_MCE, CQE_SIZE);
+	mce_write(2, CQE_IOPB_ADDR, sh_MCE_IOPB);
+	mce_write(1, CQE_IOPB_LENGTH, IOPB_SHORT_SIZE);
+	mce_write(1, CQE_WORK_QUEUE, 0);
+	mce_write(2, CQE_QECR, M_QECR_GO);
 
 	/* poll for the command to complete */
 	for (;;) {
@@ -649,16 +610,16 @@ vs_reset(sc)
 		/* ack & clear scsi error condition cause by reset */
 		if (CRSW & M_CRSW_ER) {
 			CRB_CLR_DONE;
-			riopb->iopb_STATUS = 0;
+			vs_write(2, sh_RET_IOPB + IOPB_STATUS, 0);
 			break;
 		}
 		CRB_CLR_DONE;
 	}
 
 	/* thaw all work queues */
-	thaw_queue(sc, 0xFF);
+	thaw_queue(sc, 0xff);
 
-	splx (s);
+	splx(s);
 }
 
 /*
@@ -666,19 +627,14 @@ vs_reset(sc)
  * We'll generally update: xs->{flags,resid,error,sense,status} and
  * occasionally xs->retries.
  */
-
 int
-vs_checkintr(sc, xs, status)
-	struct vs_softc *sc;
-	struct scsi_xfer *xs;
-	int   *status;
+vs_checkintr(struct vs_softc *sc, struct scsi_xfer *xs, int *status)
 {
-	M328_IOPB *riopb = (M328_IOPB *)&sc->sc_vsreg->sh_RET_IOPB;
-	u_long len;
+	u_int32_t len;
 	int error;
 
-	VL(len, riopb->iopb_LENGTH);
-	error = riopb->iopb_STATUS;
+	len = vs_read(4, sh_RET_IOPB + IOPB_LENGTH);
+	error = vs_read(2, sh_RET_IOPB + IOPB_STATUS);
 	*status = error >> 8;
 
 	xs->resid = xs->datalen - len;
@@ -694,35 +650,33 @@ vs_checkintr(sc, xs, status)
 
 /* normal interrupt routine */
 int
-vs_nintr(vsc)
-	void *vsc;
+vs_nintr(void *vsc)
 {
 	struct vs_softc *sc = (struct vs_softc *)vsc;
-	M328_CRB *crb = (M328_CRB *)&sc->sc_vsreg->sh_CRB;
 	M328_CMD *m328_cmd;
 	struct scsi_xfer *xs;
 	int status;
 	int s;
 
 	if ((CRSW & CONTROLLER_ERROR) == CONTROLLER_ERROR)
-		return(vs_eintr(sc));
+		return vs_eintr(sc);
 
 	/* Got a valid interrupt on this device */
 	s = splbio();
 	sc->sc_intrcnt_n.ev_count++;
-	VL((unsigned long)m328_cmd, crb->crb_CTAG);
+	m328_cmd = (void *)crb_read(4, CRB_CTAG);
 
 	/*
 	 * If this is a controller error, there won't be a m328_cmd
-	 * pointer in the CTAG feild.  Bad things happen if you try
-	 * to point to address 0.  Controller error should be handled
-	 * in vsdma.c  I'll change this soon - steve.
+	 * pointer in the CTAG field.  Bad things happen if you try
+	 * to point to address 0.  But then, we should have caught
+	 * the controller error above.
 	 */
 	if (m328_cmd != NULL) {
 		xs = m328_cmd->xs;
-		if (m328_cmd->top_sg_list) {
+		if (m328_cmd->top_sg_list != NULL) {
 			vs_dealloc_scatter_gather(m328_cmd->top_sg_list);
-			m328_cmd->top_sg_list = (M328_SG)0;
+			m328_cmd->top_sg_list = (M328_SG)NULL;
 		}
 		FREE(m328_cmd, M_DEVBUF); /* free the command tag */
 
@@ -739,33 +693,33 @@ vs_nintr(vsc)
 	vs_clear_return_info(sc);
 	splx(s);
 
-	return (1);
+	return 1;
 }
 
+/* error interrupts */
 int
-vs_eintr(vsc)
-	void *vsc;
+vs_eintr(void *vsc)
 {
 	struct vs_softc *sc = (struct vs_softc *)vsc;
-	M328_CEVSB *crb = (M328_CEVSB *)&sc->sc_vsreg->sh_CRB;
 	M328_CMD *m328_cmd;
 	struct scsi_xfer *xs;
-	int crsw = crb->cevsb_CRSW;
-	int ecode = crb->cevsb_ERROR;
+	int crsw, ecode;
 	int s;
 
 	/* Got a valid interrupt on this device */
 	s = splbio();
 	sc->sc_intrcnt_e.ev_count++;
 
-	VL((unsigned long)m328_cmd, crb->cevsb_CTAG);
+	crsw = vs_read(2, sh_CEVSB + CEVSB_CRSW);
+	ecode = vs_read(1, sh_CEVSB + CEVSB_ERROR);
+	m328_cmd = (void *)crb_read(4, CRB_CTAG);
 	xs = m328_cmd != NULL ? m328_cmd->xs : NULL;
 
 	if (crsw & M_CRSW_RST) {
-		printf("%s: bus reset!\n", sc->sc_dev.dv_xname);
+		printf("%s: bus reset\n", sc->sc_dev.dv_xname);
 		vs_clear_return_info(sc);
 		splx(s);
-		return(1);
+		return 1;
 	}
 
 	if (xs == NULL)
@@ -777,7 +731,7 @@ vs_eintr(vsc)
 
 	switch (ecode) {
 	case CEVSB_ERR_TYPE:
-		printf("IOPB Type error\n");
+		printf("IOPB type error\n");
 		break;
 	case CEVSB_ERR_TO:
 		printf("timeout\n");
@@ -812,22 +766,17 @@ vs_eintr(vsc)
 		CRB_CLR_ER;
 	CRB_CLR_DONE;
 
-	thaw_queue(sc, 0xFF);
+	thaw_queue(sc, 0xff);
 	vs_clear_return_info(sc);
 	splx(s);
 
-	return(1);
+	return 1;
 }
 
 static void
-vs_clear_return_info(sc)
-	struct vs_softc *sc;
+vs_clear_return_info(struct vs_softc *sc)
 {
-        M328_IOPB *riopb = (M328_IOPB *)&sc->sc_vsreg->sh_RET_IOPB;
-	M328_CEVSB *crb = (M328_CEVSB *)&sc->sc_vsreg->sh_CRB;
-	d16_bzero(riopb, sizeof(M328_IOPB));
-	/* note that this also partially overrides the sh_RET_IOPB before... */
-	d16_bzero(crb, sizeof(M328_CEVSB));
+	vs_bzero(sh_RET_IOPB, CRB_SIZE + IOPB_LONG_SIZE);
 }
 
 /*
@@ -846,8 +795,7 @@ vs_alloc_scatter_gather(void)
 }
 
 void
-vs_dealloc_scatter_gather(sg)
-	M328_SG sg;
+vs_dealloc_scatter_gather(M328_SG sg)
 {
 	int i;
 
@@ -860,66 +808,63 @@ vs_dealloc_scatter_gather(sg)
 }
 
 void
-vs_link_sg_element(element, phys_add, len)
-	sg_list_element_t *element;
-	vaddr_t phys_add;
-	int len;
+vs_link_sg_element(sg_list_element_t *element, vaddr_t phys_add, int len)
 {
 	element->count.bytes = len;
-	LV(element->address, phys_add);
+	element->addrlo = phys_add;
+	element->addrhi = phys_add >> 16;
 	element->link = 0; /* FALSE */
 	element->transfer_type = NORMAL_TYPE;
 	element->memory_type = LONG_TRANSFER;
-	element->address_modifier = 0xD;
+	element->address_modifier = ADRM_EXT_S_D;
 }
 
 void
-vs_link_sg_list(list, phys_add, elements)
-	sg_list_element_t *list;
-	vaddr_t phys_add;
-	int elements;
+vs_link_sg_list(sg_list_element_t *list, vaddr_t phys_add, int elements)
 {
-
-	list->count.scatter.gather  = elements;
-	LV(list->address, phys_add);
+	list->count.scatter.gather = elements;
+	list->addrlo = phys_add;
+	list->addrhi = phys_add >> 16;
 	list->link = 1;	   /* TRUE */
 	list->transfer_type = NORMAL_TYPE;
 	list->memory_type = LONG_TRANSFER;
-	list->address_modifier = 0xD;
+	list->address_modifier = ADRM_EXT_S_D;
 }
 
 M328_SG
-vs_build_memory_structure(xs, iopb)
-	struct scsi_xfer *xs;
-	M328_IOPB  *iopb;	       /* the iopb */
+vs_build_memory_structure(struct vs_softc *sc, struct scsi_xfer *xs,
+     bus_addr_t iopb)
 {
-	M328_SG   sg;
+	M328_SG sg;
 	vaddr_t starting_point_virt, starting_point_phys, point_virt,
 	point1_phys, point2_phys, virt;
-	unsigned len;
-	int       level;
+	unsigned int len;
+	int level;
 
-	sg = (M328_SG)0;   /* Hopefully we need no scatter/gather list */
+	sg = NULL;	/* Hopefully we need no scatter/gather list */
 
 	/*
 	 * We have the following things:
-	 *	virt			the virtual address of the contiguous virtual memory block
-	 *	len			the length of the contiguous virtual memory block
-	 *	starting_point_virt	the virtual address of the contiguous *physical* memory block
-	 *	starting_point_phys	the *physical* address of the contiguous *physical* memory block
-	 *	point_virt		the pointer to the virtual memory we are checking at the moment
-	 *	point1_phys		the pointer to the *physical* memory we are checking at the moment
-	 *	point2_phys		the pointer to the *physical* memory we are checking at the moment
+	 *	virt			va of the virtual memory block
+	 *	len			length of the virtual memory block
+	 *	starting_point_virt	va of the physical memory block
+	 *	starting_point_phys	pa of the physical memory block
+	 *	point_virt		va of the virtual memory
+	 *				    we are checking at the moment
+	 *	point1_phys		pa of the physical memory
+	 *				    we are checking at the moment
+	 *	point2_phys		pa of another physical memory
+	 *				    we are checking at the moment
 	 */
 
 	level = 0;
 	virt = starting_point_virt = (vaddr_t)xs->data;
 	point1_phys = starting_point_phys = kvtop((vaddr_t)xs->data);
 	len = xs->datalen;
+
 	/*
 	 * Check if we need scatter/gather
 	 */
-
 	if (len > PAGE_SIZE) {
 		for (level = 0, point_virt = round_page(starting_point_virt+1);
 		    /* if we do already scatter/gather we have to stay in the loop and jump */
@@ -931,24 +876,20 @@ vs_build_memory_structure(xs, iopb)
 			if ((point2_phys - trunc_page(point1_phys) - PAGE_SIZE) ||		   /* physical memory is not contiguous */
 			    (point_virt - starting_point_virt >= MAX_SG_BLOCK_SIZE && sg)) {   /* we only can access (1<<16)-1 bytes in scatter/gather_mode */
 				if (point_virt - starting_point_virt >= MAX_SG_BLOCK_SIZE) {	       /* We were walking too far for one scatter/gather block ... */
-					assert( MAX_SG_BLOCK_SIZE > PAGE_SIZE );
 					point_virt = trunc_page(starting_point_virt+MAX_SG_BLOCK_SIZE-1);    /* So go back to the beginning of the last matching page */
 					/* and generate the physical address of
 					 * this location for the next time. */
 					point2_phys = kvtop(point_virt);
 				}
 
-				if (!sg) {
-					/* We allocate our fist scatter/gather list */
+				if (sg == NULL)
 					sg = vs_alloc_scatter_gather();
-				}
-#if 1 /* broken firmware */
 
+#if 1 /* broken firmware */
 				if (sg->elements >= MAX_SG_ELEMENTS) {
 					vs_dealloc_scatter_gather(sg);
 					return (NULL);
 				}
-
 #else /* if the firmware will ever get fixed */
 				while (sg->elements >= MAX_SG_ELEMENTS) {
 					if (!sg->up) { /* If the list full in this layer ? */
@@ -1000,7 +941,7 @@ vs_build_memory_structure(xs, iopb)
 	 * Climb up along the right side of the tree until we reach the top.
 	 */
 
-	if (sg) {
+	if (sg != NULL) {
 		while (sg->up) {
 			/* link this list also in physical memory */
 			vs_link_sg_list(&(sg->up->list[sg->up->elements-1]),
@@ -1009,15 +950,17 @@ vs_build_memory_structure(xs, iopb)
 			sg = sg->up;		       /* Climb up */
 		}
 
-		iopb->iopb_OPTION |= M_OPT_SG;
-		iopb->iopb_ADDR |= M_ADR_SG_LINK;
-		LV(iopb->iopb_BUFF, kvtop((vaddr_t)sg->list));
-		LV(iopb->iopb_LENGTH, sg->elements);
-		LV(iopb->iopb_SGTTL, len);
+		vs_write(2, iopb + IOPB_OPTION,
+		    vs_read(2, iopb + IOPB_OPTION) | M_OPT_SG);
+		vs_write(2, iopb + IOPB_ADDR,
+		    vs_read(2, iopb + IOPB_ADDR) | M_ADR_SG_LINK);
+		vs_write(4, iopb + IOPB_BUFF, kvtop((vaddr_t)sg->list));
+		vs_write(4, iopb + IOPB_LENGTH, sg->elements);
+		vs_write(4, iopb + IOPB_SGTTL, len);
 	} else {
 		/* no scatter/gather necessary */
-		LV(iopb->iopb_BUFF, starting_point_phys);
-		LV(iopb->iopb_LENGTH, len);
+		vs_write(4, iopb + IOPB_BUFF, starting_point_phys);
+		vs_write(4, iopb + IOPB_LENGTH, len);
 	}
-	return (sg);
+	return sg;
 }
diff --git a/sys/arch/mvme88k/dev/vsreg.h b/sys/arch/mvme88k/dev/vsreg.h
index 9d7a9884fec..1c11bc153f7 100644
--- a/sys/arch/mvme88k/dev/vsreg.h
+++ b/sys/arch/mvme88k/dev/vsreg.h
@@ -1,5 +1,6 @@
-/*	$OpenBSD: vsreg.h,v 1.7 2004/05/21 10:24:42 miod Exp $ */
+/*	$OpenBSD: vsreg.h,v 1.8 2004/05/22 19:34:12 miod Exp $	*/
 /*
+ * Copyright (c) 2004, Miodrag Vallat.
  * Copyright (c) 1999 Steve Murphree, Jr.
  * Copyright (c) 1990 The Regents of the University of California.
  * All rights reserved.
@@ -31,646 +32,399 @@
  * SUCH DAMAGE.
  */
 
-#if !defined(_M328REG_H_)
-#define _M328REG_H_
-
-
-typedef struct LONGV
-{
-        u_short  msw;
-        u_short  lsw;
-} LONGV;
-
-#define MSW(x)  ((x).msw)
-#define LSW(x)  ((x).lsw)
-
-/*
- * macro to convert a unsigned long to a LONGV
- */
-
-#define LV( a, b) \
-{ \
-  MSW( a ) = ( (( (unsigned long)(b) ) >> 16) & 0xffff ); \
-  LSW( a ) = ( ( (unsigned long)(b) ) & 0xffff); \
-}
+#ifndef	_MVME328_REG_H_
+#define	_MVME328_REG_H_
 
 /*
- * macro to convert a LONGV to a unsigned long
+ * JAGUAR specific device limits
  */
 
-#define VL( a, b) \
-{ \
-  a = ( (((unsigned long) MSW(b)) << 16 ) | (((unsigned long) LSW(b)) & 0x0ffff) ); \
-}
-
-#define         COUGAR          0x4220  /* board type (config. status area) */
-#define         JAGUAR          0
+#define	JAGUAR_MIN_Q_SIZ		2
+#define	JAGUAR_MAX_Q_SIZ		2
+#define	JAGUAR_MAX_CTLR_CMDS		80	/* Interphase says so */
 
 /*
- *      JAGUAR specific device limits.
+ * COUGAR specific device limits
  */
 
-#define JAGUAR_MIN_Q_SIZ                2       /* got'a have at least one! */
-#define JAGUAR_MAX_Q_SIZ                2       /* can't have more */
-#define JAGUAR_MAX_CTLR_CMDS            80      /* Interphase says so */
-
-/*
- *      COUGAR specific device limits.
- */
-
-#define COUGAR_MIN_Q_SIZ                2       /* got'a have at least one! */
-#define COUGAR_CMDS_PER_256K            42      /* Interphase says so */
+#define	COUGAR_MIN_Q_SIZ		2
+#define	COUGAR_CMDS_PER_256K		42	/* Interphase says so */
 
 /*
  * Structures
  */
 
-#define NUM_CQE                 10
-#define MAX_IOPB                64
-#define NUM_IOPB                NUM_CQE
-
-#define S_IOPB_RES              (MAX_IOPB - sizeof(M328_short_IOPB))
-
-#define S_SHORTIO               2048
-
-#define S_IOPB                  sizeof(M328_IOPB)
-#define S_CIB                   sizeof(M328_CIB)
-#define S_MCSB                  sizeof(M328_MCSB)
-#define S_MCE                   sizeof(M328_CQE)
-#define S_CQE                   (sizeof(M328_CQE) * NUM_CQE)
-#define S_HIOPB                 (sizeof(M328_IOPB) * NUM_IOPB)
-#define S_HSB                   sizeof(M328_HSB)
-#define S_CRB                   sizeof(M328_CRB)
-#define S_CSS                   sizeof(M328_CSB)
-#define S_NOT_HOST              (S_MCSB + S_MCE + S_CQE + S_HIOPB + S_IOPB + \
-                                 S_CIB + S_HSB + S_CRB + S_IOPB + S_CSS)
-#define S_HUS_FREE              (S_SHORTIO - S_NOT_HOST)
-
-#define S_WQCF                  sizeof(M328_WQCF)
-
-
-/****************     Master Control Status Block (MCSB) *******************/
+#define	NUM_CQE			10
+#define	NUM_IOPB		NUM_CQE
 
 /*
- * defines for Master Status Register
+ * Master Control Status Block (MCSB)
  */
 
-#define M_MSR_QFC               0x0004          /* queue flush complete */
-#define M_MSR_BOK               0x0002          /* board OK */
-#define M_MSR_CNA               0x0001          /* controller not available */
+#define	MCSB_MSR		0x000000	/* master status register */
+#define	M_MSR_QFC	0x0004		/* queue flush complete */
+#define	M_MSR_BOK	0x0002		/* board OK */
+#define	M_MSR_CNA	0x0001		/* controller not available */
+#define	MCSB_MCR		0x000002	/* master control register */
+#define	M_MCR_SFEN	0x2000		/* sysfail enable */
+#define	M_MCR_RES	0x1000		/* reset controller */
+#define	M_MCR_FLQ	0x0800		/* flush queue */
+#define	M_MCR_FLQR	0x0004		/* flush queue and report */
+#define	M_MCR_SQM	0x0001		/* start queue mode */
+#define	MCSB_IQAR		0x000004	/* interrupt on queue avail */
+#define	M_IQAR_IQEA	0x8000		/* interrupt on queue entry avail */
+#define	M_IQAR_IQEH	0x4000		/* interrupt on queue half empty */
+#define	M_IQAR_ILVL	0x0700		/* interrupt lvl on queue available */
+#define	M_IQAR_IVCT	0x00ff		/* interrupt vector on queue avail */
+#define	MCSB_QHDP		0x000006	/* queue head pointer */
+#define	MCSB_THAW		0x000008	/* thaw work queue */
+#define	M_THAW_TWQN	0xff00		/* thaw work queue number */
+#define	M_THAW_TWQE	0x0001		/* thaw work queue enable */
+#define	MCSB_SIZE		0x000010
 
 /*
- * defines for Master Control Register
+ * Host Semaphore Block (HSB)
  */
 
-#define M_MCR_SFEN              0x2000          /* sysfail enable */
-#define M_MCR_RES               0x1000          /* reset controller */
-#define M_MCR_FLQ               0x0800          /* flush queue */
-#define M_MCR_FLQR              0x0004          /* flush queue and report */
-#define M_MCR_SQM               0x0001          /* start queue mode */
+#define	HSB_INITQ		0x000000	/* init MCE flag */
+#define	HSB_WORKQ		0x000002	/* work queue number */
+#define	HSB_MAGIC		0x000004	/* magic word */
+#define	HSB_SIZE		0x000008
 
 /*
- * defines for Interrupt on Queue Available Register
+ * Controller Initialization Block (CIB)
  */
 
-#define M_IQAR_IQEA             0x8000  /* interrupt on queue entry avail */
-#define M_IQAR_IQEH             0x4000  /* interrupt on queue half empty */
-#define M_IQAR_ILVL             0x0700  /* interrupt lvl on queue available */
-#define M_IQAR_IVCT             0x00FF  /* interrupt vector on queue avail */
+#define	CIB_NCQE		0x000000	/* number of CQE */
+#define	CIB_BURST		0x000002	/* DMA burst count */
+#define	CIB_NVECT		0x000004	/* normal completion vector */
+#define	CIB_EVECT		0x000006	/* error completion vector */
+#define	M_VECT_ILVL	0x0700		/* Interrupt Level mask */
+#define	M_VECT_IVCT	0x00ff		/* Interrupt Vector mask */
+#define	CIB_PID			0x000008	/* primary scsi bus id */
+#define	CIB_SID			0x00000a	/* secondary scsi bus id */
+#define	M_PSID_DFT	0x0008 		/* default ID enable */
+#define	M_PSID_ID	0x0007		/* primary/secondary SCSI ID */
+#define	CIB_CRBO		0x00000c	/* CRB offset */
+#define	CIB_SELECT		0x00000e	/* selection timeout in ms */
+#define	CIB_WQTIMO		0x000012	/* work queue timeout in 256ms */
+#define	CIB_VMETIMO		0x000016	/* VME timeout in 32ms */
+#define	CIB_OBMT		0x00001e	/* offboard CRB mtype/xfer type/ad mod */
+#define	CIB_OBADDR		0x000020	/* host mem address for offboard CRB */
+#define	CIB_ERR_FLGS		0x000024	/* error recovery flags */
+#define	M_ERRFLGS_FOSR	0x0001		/* Freeze on SCSI bus reset */
+#define	M_ERRFLGS_RIN	0x0002		/* SCSI bus reset interrupt */
+#define	M_ERRFLGS_RSE	0x0004		/* Report COUGAR SCSI errors */
+#define	CIB_SBRIV		0x00002a	/* scsi bus reset interrupt vector */
+#define	CIB_SOF0		0x00002c	/* synchronous offset (bus 0) */
+#define	CIB_SRATE0		0x00002d	/* sync negotiation rate (bus 0) */
+#define	CIB_SOF1		0x00002e	/* synchronous offset (bus 0) */
+#define	CIB_SRATE1		0x00002f	/* sync negotiation rate (bus 0) */
+#define	CIB_SIZE		0x000030
 
 /*
- * defines for Thaw Work Queue Register
+ * Command Queue Entry (CQE)
  */
 
-#define M_THAW_TWQN             0xff00          /* thaw work queue number */
-#define M_THAW_TWQE             0x0001          /* thaw work queue enable */
-
-typedef struct mcsb
-{                                       /* Master control/Status Block */
-    volatile u_short      mcsb_MSR;       /* Master status register */
-    volatile u_short      mcsb_MCR;       /* Master Control register */
-    volatile u_short      mcsb_IQAR;      /* Interrupt on Queue Available Reg */
-    volatile u_short      mcsb_QHDP;      /* Queue head pointer */
-    volatile u_short      mcsb_THAW;      /* Thaw work Queue */
-    volatile u_short      mcsb_RES0;      /* Reserved word 0 */
-    volatile u_short      mcsb_RES1;      /* Reserved word 1 */
-    volatile u_short      mcsb_RES2;      /* Reserved word 2 */
-} M328_MCSB;
-
-/**************** END Master Control Status Block (MCSB) *******************/
-
-/****************     Host Semaphore Block (HSB)         *******************/
-
-typedef struct hsb
-{                                       /* Host Semaphore Block */
-    volatile u_short      hsb_INITQ;      /* Init MCE Flag */
-    volatile u_short      hsb_WORKQ;      /* Work Queue number */
-    volatile u_short      hsb_MAGIC;      /* Magic word */
-    volatile u_short      hsb_RES0;       /* Reserved word */
-} M328_HSB;
-
-/**************** END Host Semaphore Block (HSB)         *******************/
-
-/****************     Perform Diagnostics Command Format *******************/
-
-typedef struct pdcf
-{                                       /* Perform Diagnostics Cmd Format */
-    volatile u_short      pdcf_CMD;       /* Command normally 0x40 */
-    volatile u_short      pdcf_RES0;      /* Reserved word */
-    volatile u_short      pdcf_STATUS;    /* Return Status */
-    volatile u_short      pdcf_RES1;      /* Reserved Word */
-    volatile u_short      pdcf_ROM;       /* ROM Test Results */
-    volatile u_short      pdcf_BUFRAM;    /* Buffer RAM results */
-    volatile u_short      pdcf_EVENT_RAM; /* Event Ram test Results */
-    volatile u_short      pdcf_SCSI_PRI_PORT; /* SCSI Primary Port Reg test */
-    volatile u_short      pdcf_SCSI_SEC_PORT; /* SCSI Secondary Port Reg test */
-} M328_PDCF;
-
-#define PDCF_SUCCESS            0xFFFF
-
-/**************** END Perform Diagnostics Command Format *******************/
-
-/***************      Controller Initialization Block (CIB) *****************/
+#define	CQE_QECR		0x000000	/* queue entry control reg */
+#define	M_QECR_IOPB	0x0f00		/* IOPB type (must be zero) */
+#define	M_QECR_HPC	0x0004		/* High Priority command */
+#define	M_QECR_AA	0x0002		/* abort acknowledge */
+#define	M_QECR_GO	0x0001		/* Go/Busy */
+#define	CQE_IOPB_ADDR		0x000002	/* IOPB address */
+#define	CQE_CTAG		0x000004	/* command tag */
+#define	CQE_IOPB_LENGTH		0x000008	/* IOPB length */
+#define	CQE_WORK_QUEUE		0x000009	/* work queue number */
+#define	CQE_SIZE		0x00000c
 
 /*
- * defines for Interrupt Vectors
+ * Command Response Block (CRB)
  */
 
-#define M_VECT_ILVL             0x0700  /* Interrupt Level */
-#define M_VECT_IVCT             0x00FF  /* Interrupt Vector */
+#define	CRB_CRSW		0x000000	/* status word */
+#define	M_CRSW_SE	0x0800		/* SCSI error (COUGAR) */
+#define	M_CRSW_RST	0x0400		/* SCSI Bus reset (COUGAR) */
+#define	M_CRSW_SC	0x0080		/* status change */
+#define	M_CRSW_CQA	0x0040		/* Command queue entry available */
+#define	M_CRSW_QMS	0x0020		/* queue mode started */
+#define	M_CRSW_AQ	0x0010		/* abort queue */
+#define	M_CRSW_EX	0x0008		/* exception */
+#define	M_CRSW_ER	0x0004		/* error */
+#define	M_CRSW_CC	0x0002		/* command complete */
+#define	M_CRSW_CRBV	0x0001		/* cmd response block valid/clear */
+#define	CRB_CTAG		0x000004	/* command tag */
+#define	CRB_IOPB_LENGTH		0x000008	/* IOPB length */
+#define	CRB_WORK_QUEUE		0x000009	/* work queue number */
+#define	CRB_SIZE		0x00000c
 
 /*
- * defines for SCSI Bus ID Registers
+ * Controller Error Vector Status Block (CEVSB)
+ * This is a variation of the CRB, _but larger_.
  */
 
-#define M_PSID_DFT              0x0008  /* default ID enable */
-#define M_PSID_ID               0x0007  /* Primary/Secondary SCSI ID */
+#define	CONTROLLER_ERROR	0x0085
+#define	NR_SCSI_ERROR		0x0885
+
+#define	CEVSB_CRSW		0x000000	/* status word */
+#define	CEVSB_TYPE		0x000002	/* IOPB type */
+#define	CEVSB_CTAG		0x000004	/* command tag */
+#define	CEVSB_IOPB_LENGTH	0x000008	/* IOPB length */
+#define	CEVSB_WORK_QUEUE	0x000009	/* work queue number */
+#define	CEVSB_ERROR		0x00000d	/* error code */
+#define	CEVSB_ERR_TYPE	0xc0			/* IOPB type error */
+#define	CEVSB_ERR_TO	0xc1			/* IOPB timeout error */
+#define	CEVSB_ERR_TR	0x82			/* Target Reconnect, no IOPB */
+#define	CEVSB_ERR_OF	0x83			/* Overflow */
+#define	CEVSB_ERR_BD	0x84			/* Bad direction */
+#define	CEVSB_ERR_NR	0x86			/* Non-Recoverabl Error */
+#define	CESVB_ERR_PANIC	0xff			/* Board Painc!!! */
+#define	CEVSB_AUXERR		0x00000e	/* cougar error code */
+#define	CEVSB_SIZE		0x000010
 
 /*
- *      Error recovery flags.
+ * Configuration Status Block (CSB)
  */
 
-#define M_ERRFLGS_FOSR          0x0001  /* Freeze on SCSI bus reset */
-#define M_ERRFLGS_RIN           0x0002  /* SCSI bus reset interrupt */
-#define M_ERRFLGS_RSE           0x0004  /* Report COUGAR SCSI errors */
+#define	CSB_TYPE		0x000000	/* jaguar/cougar */
+#define	COUGAR		0x4220
+#define	JAGUAR		0x0000
+#define	CSB_PCODE		0x000003	/* product code */
+#define	CSB_PVAR		0x000009	/* product variation */
+#define	CSB_FREV		0x00000d	/* firmware revision level */
+#define	CSB_FDATE		0x000012	/* firmware release date */
+#define	CSB_SSIZE		0x00001a	/* system memory size in KB */
+#define	CSB_BSIZE		0x00001c	/* buffer memory size in KB */
+#define	CSB_PFECID		0x000020	/* primary bus FEC id */
+#define	CSB_SFECID		0x000021	/* secondary bus FEC id */
+#define	CSB_PID			0x000022	/* primary bus id */
+#define	CSB_SID			0x000023	/* secondary bus id */
+#define	CSB_LPDS		0x000024	/* last primary device selected */
+#define	CSB_LSDS		0x000025	/* last secondary device selected */
+#define	CSB_PPS			0x000026	/* primary phase sense */
+#define	CSB_SPS			0x000027	/* secondary phase sense */
+#define	CSB_DBIB		0x000029	/* daughter board id */
+#define	CSB_SDS			0x00002b	/* software DIP switch */
+#define	CSB_FWQR		0x00002e	/* frozen work queues register */
+#define	CSB_SIZE		0x000078
 
 /*
- * Controller Initialization Block
+ * IOPB Format (IOPB)
  */
 
-typedef struct cib
-{
-    volatile u_short      cib_NCQE;       /* Number of Command Queue Entries */
-    volatile u_short      cib_BURST;      /* DMA Burst count */
-    volatile u_short      cib_NVECT;      /* Normal Completion Vector */
-    volatile u_short      cib_EVECT;      /* Error Completion Vector */
-    volatile u_short      cib_PID;        /* Primary SCSI Bus ID */
-    volatile u_short      cib_SID;        /* Secondary SCSI Bus ID */
-    volatile u_short      cib_CRBO;       /* Command Response Block Offset */
-    volatile u_short      cib_SELECT_msw;/* Selection timeout in milli_second */
-    volatile u_short      cib_SELECT_lsw;/* Selection timeout in milli_second */
-    volatile u_short      cib_WQ0TIMO_msw;/* Work Q - timeout in 256 ms */
-    volatile u_short      cib_WQ0TIMO_lsw;/* Work Q - timeout in 256 ms */
-    volatile u_short      cib_VMETIMO_msw;/* VME Time out in 32 ms */
-    volatile u_short      cib_VMETIMO_lsw;/* VME Time out in 32 ms */
-    volatile u_short      cib_RES0[2];    /* Reserved words */
-    volatile u_short      cib_OBMT;       /* offbrd CRB mtype/xfer type/ad mod */
-    volatile u_short      cib_OBADDR_msw;/* host mem address for offboard CRB */
-    volatile u_short      cib_OBADDR_lsw;/* host mem address for offboard CRB */
-    volatile u_short      cib_ERR_FLGS;   /* error recovery flags */
-    volatile u_short      cib_RES1;       /* reserved word */
-    volatile u_short      cib_RES2;       /* reserved word */
-    volatile u_short      cib_SBRIV;      /* SCSI Bus Reset Interrupt Vector */
-    volatile u_char       cib_SOF0;       /* Synchronous offset (Bus 0) */
-    volatile u_char       cib_SRATE0;     /* Sync negotiation rate (Bus 0) */
-    volatile u_char       cib_SOF1;       /* Synchronous offset (Bus 1) */
-    volatile u_char       cib_SRATE1;     /* Sync negotiation rate (Bus 1) */
-} M328_CIB;
-
-/**************** END Controller Initialization Block (CIB) *****************/
-
-/****************     Command Queue Entry (CQE)          *******************/
+#define	IOPB_CMD		0x000000	/* command code */
+#define	IOPB_OPTION		0x000002	/* option word */
+#define	M_OPT_HEAD_TAG		0x3000	/* head of queue command queue tag */
+#define	M_OPT_ORDERED_TAG	0x2000	/* order command queue tag */
+#define	M_OPT_SIMPLE_TAG	0x1000	/* simple command queue tag */
+#define	M_OPT_GO_WIDE		0x0800	/* use WIDE transfers */
+#define	M_OPT_DIR		0x0100	/* VME direction bit */
+#define	M_OPT_SG_BLOCK		0x0008	/* scatter/gather in 512 byte blocks */
+#define	M_OPT_SS		0x0004	/* Suppress synchronous transfer */
+#define	M_OPT_SG		0x0002	/* scatter/gather bit */
+#define	M_OPT_IE		0x0001	/* Interrupt enable */
+#define	IOPB_STATUS		0x000004	/* return status word */
+#define	IOPB_NVCT		0x000008	/* normal completion vector */
+#define	IOPB_EVCT		0x000009	/* error completion vector */
+#define	IOPB_LEVEL		0x00000a	/* interrupt level */
+#define	IOPB_ADDR		0x00000e	/* address type and modifier */
+#define	M_ADR_TRANS	0x0c00		/* transfer type */
+#define	M_ADR_MEMT	0x0300		/* memory type */
+#define	M_ADR_MOD	0x00ff		/* VME address modifier */
+#define	M_ADR_SG_LINK	0x8000		/* Scatter/Gather Link bit */
+#define	IOPB_BUFF		0x000010	/* buffer address */
+#define	IOPB_LENGTH		0x000014	/* max transfer length */
+#define	IOPB_SGTTL		0x000018	/* S/G total transfer length */
+#define	IOPB_UNIT		0x00001e	/* unit address on scsi bus */
+#define	M_UNIT_EXT_LUN	0xff00		/* Extended Address */
+#define	M_UNIT_EXT	0x0080		/* Extended Address Enable */
+#define	M_UNIT_BUS	0x0040		/* SCSI Bus Selection */
+#define	M_UNIT_LUN	0x0038		/* Logical Unit Number */
+#define	M_UNIT_ID	0x0007		/* SCSI Device ID */
+#define	IOPB_SCSI_DATA		0x000020	/* SCSI words for passthrough */
+#define	IOPB_SHORT_SIZE		0x000020
+#define	IOPB_LONG_SIZE		0x000040
 
 /*
- * defines for Queue Entry Control Register
+ * Initialize Work Queue Command Format (WQCF)
+ * This is a specific case of IOPB.
  */
 
-#define M_QECR_IOPB             0x0F00  /* IOPB type (must be zero) */
-#define M_QECR_HPC              0x0004  /* High Priority command */
-#define M_QECR_AA               0x0002  /* abort acknowledge */
-#define M_QECR_GO               0x0001  /* Go/Busy */
-
-#define CQE_GO(qecr)            ((qecr) |= M_QECR_GO)
-#define CQE_AA_GO(qecr)         ((qecr) |= (M_QECR_GO + M_QECR_AA))
-
-typedef struct cqe
-{                                       /* Command Queue Entry */
-    volatile u_short      cqe_QECR;       /* Queue Entry Control Register */
-    volatile u_short      cqe_IOPB_ADDR;  /* IOPB Address */
-    volatile LONGV        cqe_CTAG;       /* Command Tag */
-    volatile u_char       cqe_IOPB_LENGTH;/* IOPB Length */
-    volatile u_char       cqe_WORK_QUEUE; /* Work Queue Number */
-    volatile u_short      cqe_RES0;       /* Reserved word */
-} M328_CQE;
-
-/**************** END Command Queue Entry (CQE)          *******************/
-
-/****************     Command Response Block (CRB)       *******************/
+#define	WQCF_CMD		0x000000	/* command code */
+#define	M_WOPT_IWQ	0x8000		/* initialize work queue */
+#define	M_WOPT_PE	0x0008		/* parity check enable */
+#define	M_WOPT_FE	0x0004		/* freeze on error enable */
+#define	M_WOPT_TM	0x0002		/* target mode enable */
+#define	M_WOPT_AE	0x0001		/* abort enable */
+#define	WQCF_OPTION		0x000002	/* option word */
+#define	WQCF_STATUS		0x000004	/* return status word */
+#define	WQCF_NVCT		0x000008	/* normal completion vector */
+#define	WQCF_EVCT		0x000009	/* error completion vector */
+#define	WQCF_ILVL		0x00000a	/* interrupt level */
+#define	WQCF_WORKQ		0x00001c	/* work queue number */
+#define	WQCF_WOPT		0x00001e	/* work queue options */
+#define	WQCF_SLOTS		0x000020	/* # of slots in work queues */
+#define	WQCF_CMDTO		0x000024	/* command timeout */
 
 /*
- * defines for Command Response Status Word
+ * SCSI Reset Command Format (SRCF)
+ * This is a specific case of IOPB.
  */
 
-#define M_CRSW_SE               0x0800  /* SCSI error (COUGAR) */
-#define M_CRSW_RST              0x0400  /* SCSI Bus reset (COUGAR) */
-#define M_CRSW_SC               0x0080  /* status change */
-#define M_CRSW_CQA              0x0040  /* Command queue entry available */
-#define M_CRSW_QMS              0x0020  /* queue mode started */
-#define M_CRSW_AQ               0x0010  /* abort queue */
-#define M_CRSW_EX               0x0008  /* exception */
-#define M_CRSW_ER               0x0004  /* error */
-#define M_CRSW_CC               0x0002  /* command complete */
-#define M_CRSW_CRBV             0x0001  /* cmd response block valid/clear */
-
-#define CRB_CLR_DONE		((CRSW) = 0)
-#define CRB_CLR_ER		((CRSW) &= ~M_CRSW_ER)
-
-typedef struct crb
-{                                       /* Command Response Block */
-    volatile u_short    crb_CRSW;       /* Command Response Status Word */
-    volatile u_short    crb_RES0;       /* Reserved word */
-    volatile LONGV      crb_CTAG;       /* Command Tag */
-    volatile u_char     crb_IOPB_LENGTH;/* IOPB Length */
-    volatile u_char     crb_WORK_QUEUE; /* Work Queue Number */
-    volatile u_short    crb_RES1;       /* Reserved word */
-} M328_CRB;
-
-/**************** END Command Response Block (CRB)       *******************/
-
-/***********     Controller Error Vector Status Block (CEVSB) **************/
-#define CONTROLLER_ERROR    0x0085
-#define NR_SCSI_ERROR       0x0885
-typedef struct cevsb {				/* Command Response Block */
-    volatile u_short      cevsb_CRSW;     /* Command Response Status Word */
-    volatile u_char       cevsb_TYPE;     /* IOPB type */
-    volatile u_char       cevsb_RES0;     /* Reserved byte */
-    volatile LONGV        cevsb_CTAG;     /* Command Tag */
-    volatile u_char       cevsb_IOPB_LENGTH;/* IOPB Length */
-    volatile u_char       cevsb_WORK_QUEUE;/* Work Queue Number */
-    volatile u_short      cevsb_RES1;     /* Reserved word */
-    volatile u_char       cevsb_RES2;     /* Reserved byte */
-    volatile u_char       cevsb_ERROR;    /* error code */
-#define CEVSB_ERR_TYPE	0xC0			/* IOPB type error */
-#define CEVSB_ERR_TO	0xC1			/* IOPB timeout error */
-#define CEVSB_ERR_TR	0x82			/* Target Reconnect, no IOPB */
-#define CEVSB_ERR_OF	0x83			/* Overflow */
-#define CEVSB_ERR_BD	0x84			/* Bad direction */
-#define CEVSB_ERR_NR	0x86			/* Non-Recoverabl Error */
-#define CESVB_ERR_PANIC	0xFF			/* Board Painc!!! */
-    volatile u_short      cevsb_AUXERR;   /* COUGAR error code */
-} M328_CEVSB;
-
-/***********  END Controller Error Vector Status Block (CEVSB) **************/
-
-/****************     Configuration Status Block (CSB)   *******************/
-
-typedef struct csb
-{                                       /* Configuration Status Blk */
-    volatile u_short      csb_TYPE;       /* 0x0=JAGUAR, 0x4220=COUGAR */
-    volatile u_char       csb_RES1;       /* Reserved byte */
-    volatile u_char       csb_PCODE[3];   /* Product Code */
-    volatile u_short      csb_RES2;       /* Reserved word */
-    volatile u_char       csb_RES3;       /* Reserved byte */
-    volatile u_char       csb_PVAR;       /* Product Variation */
-    volatile u_short      csb_RES4;       /* Reserved word */
-    volatile u_char       csb_RES5;       /* Reserved byte */
-    volatile u_char       csb_FREV[3];    /* Firmware Revision level */
-    volatile u_short      csb_RES6;       /* Reserved word */
-    volatile u_char       csb_FDATE[8];   /* Firmware Release date */
-    volatile u_short      csb_SSIZE;      /* System memory size in Kbytes */
-    volatile u_short      csb_BSIZE;      /* Buffer memory size in Kbytes */
-    volatile u_short      csb_RES8;       /* Reserved word */
-    volatile u_char       csb_PFECID;     /* Primary Bus FEC ID */
-    volatile u_char       csb_SFECID;     /* Secondard Bus FEC ID */
-    volatile u_char       csb_PID;        /* Primary Bus ID */
-    volatile u_char       csb_SID;        /* Secondary Bus ID */
-    volatile u_char       csb_LPDS;       /* Last Primary Device Selected */
-    volatile u_char       csb_LSDS;       /* Last Secondary Device Selected */
-    volatile u_char       csb_PPS;        /* Primary Phase Sense */
-    volatile u_char       csb_SPS;        /* Secondary Phase Sense */
-    volatile u_char       csb_RES10;      /* Reserved byte */
-    volatile u_char       csb_DBID;       /* Daughter Board ID */
-    volatile u_char       csb_RES11;      /* Reserved byte */
-    volatile u_char       csb_SDS;        /* Software DIP Switch */
-    volatile u_short      csb_RES12;      /* Reserved word */
-    volatile u_short      csb_FWQR;       /* Frozen Work Queues Register */
-    volatile u_char       csb_RES13[72];  /* Reserved bytes */
-} M328_CSB;
-
-/**************** END Configuration Status Block (CSB)   *******************/
-
-/****************     IOPB Format (IOPB)                 *******************/
+#define	SRCF_CMD		0x000000	/* command code */
+#define	SRCF_OPTION		0x000002	/* option word */
+#define	SRCF_STATUS		0x000004	/* return status word */
+#define	SRCF_NVCT		0x000008	/* normal completion vector */
+#define	SRCF_EVCT		0x000009	/* error completion vector */
+#define	SRCF_ILVL		0x00000a	/* interrupt level */
+#define	SRCF_BUSID		0x00001c	/* scsi bus id to reset */
 
 /*
- * defines for IOPB Option Word
+ * Device Reinitialize Command Format (DRCF)
+ * This is a specific case of IOPB.
  */
 
-#define M_OPT_HEAD_TAG          0x3000  /* head of queue command queue tag */
-#define M_OPT_ORDERED_TAG       0x2000  /* order command queue tag */
-#define M_OPT_SIMPLE_TAG        0x1000  /* simple command queue tag */
-#define M_OPT_GO_WIDE           0x0800  /* use WIDE transfers */
-#define M_OPT_DIR               0x0100  /* VME direction bit */
-#define M_OPT_SG_BLOCK          0x0008  /* scatter/gather in 512 byte blocks */
-#define M_OPT_SS                0x0004  /* Suppress synchronous transfer */
-#define M_OPT_SG                0x0002  /* scatter/gather bit */
-#define M_OPT_IE                0x0001  /* Interrupt enable */
+#define	DRCF_CMD		0x000000	/* command code */
+#define	DRCF_OPTION		0x000002	/* option word */
+#define	DRCF_STATUS		0x000004	/* return status word */
+#define	DRCF_NVCT		0x000008	/* normal completion vector */
+#define	DRCF_EVCT		0x000009	/* error completion vector */
+#define	DRCF_ILVL		0x00000a	/* interrupt level */
+#define	DRCF_UNIT		0x00001e	/* unit address */
 
 /*
- * defines for IOPB Address Type and Modifier
+ * Short I/O memory layout
  */
 
-#define M_ADR_TRANS             0x0C00  /* transfer type */
-#define M_ADR_MEMT              0x0300  /* memory type */
-#define M_ADR_MOD               0x00FF  /* VME address modifier */
-#define M_ADR_SG_LINK           0x8000  /* Scatter/Gather Link bit */
+#define	S_SHORTIO		0x000800
 
-/*
- * defines for IOPB Unit Address on SCSI Bus
- */
+#define	sh_MCSB		(0)
+#define	sh_MCE		(sh_MCSB + MCSB_SIZE)
+#define	sh_CQE(x)	(sh_MCE + CQE_SIZE + CQE_SIZE * (x))
+#define	sh_IOPB(x)	(sh_CQE(NUM_CQE) + IOPB_LONG_SIZE * (x))
+#define	sh_MCE_IOPB	(sh_IOPB(NUM_IOPB))
+#define	sh_CIB		(sh_MCE_IOPB + IOPB_LONG_SIZE)
 
-#define M_UNIT_EXT_LUN          0xFF00  /* Extended Address */
-#define M_UNIT_EXT              0x0080  /* Extended Address Enable */
-#define M_UNIT_BUS              0x0040  /* SCSI Bus Selection */
-#define M_UNIT_LUN              0x0038  /* Logical Unit Number */
-#define M_UNIT_ID               0x0007  /* SCSI Device ID */
-
-typedef struct short_iopb
-{
-    volatile u_short      iopb_CMD;       /* IOPB Command code */
-    volatile u_short      iopb_OPTION;    /* IOPB Option word */
-    volatile u_short      iopb_STATUS;    /* IOPB Return Status word */
-    volatile u_short      iopb_RES0;      /* IOPB Reserved word */
-    volatile u_char       iopb_NVCT;      /* IOPB Normal completion Vector */
-    volatile u_char       iopb_EVCT;      /* IOPB Error  completion Vector */
-    volatile u_short      iopb_LEVEL;     /* IOPB Interrupt Level */
-    volatile u_short      iopb_RES1;      /* IOPB Reserved word */
-    volatile u_short      iopb_ADDR;      /* IOPB Address type and modifer */
-    volatile LONGV        iopb_BUFF;      /* IOPB Buffer Address */
-    volatile LONGV        iopb_LENGTH;    /* IOPB Max-Transfer Length */
-    volatile LONGV        iopb_SGTTL;     /* IOPB Scatter/Gather Total Transfer len */
-    volatile u_short      iopb_RES4;      /* IOPB Reserved word */
-    volatile u_short      iopb_UNIT;      /* IOPB Unit address on SCSI bus */
-} M328_short_IOPB;
-
-typedef struct iopb
-{
-    volatile u_short      iopb_CMD;       /* IOPB Command code */
-    volatile u_short      iopb_OPTION;    /* IOPB Option word */
-    volatile u_short      iopb_STATUS;    /* IOPB Return Status word */
-    volatile u_short      iopb_RES0;      /* IOPB Reserved word */
-    volatile u_char       iopb_NVCT;      /* IOPB Normal completion Vector */
-    volatile u_char       iopb_EVCT;      /* IOPB Error  completion Vector */
-    volatile u_short      iopb_LEVEL;     /* IOPB Interrupt Level */
-    volatile u_short      iopb_RES1;      /* IOPB Reserved word */
-    volatile u_short      iopb_ADDR;      /* IOPB Address type and modifer */
-    volatile LONGV        iopb_BUFF;      /* IOPB Buffer Address */
-    volatile LONGV        iopb_LENGTH;    /* IOPB Max-Transfer Length */
-    volatile LONGV        iopb_SGTTL;     /* IOPB Scatter/Gather Total Transfer len */
-    volatile u_short      iopb_RES4;      /* IOPB Reserved word */
-    volatile u_short      iopb_UNIT;      /* IOPB Unit address on SCSI bus */
-    u_short      iopb_SCSI[S_IOPB_RES/2]; /* IOPB SCSI words for pass thru */
-} M328_IOPB;
-
-/**************** END IOPB Format (IOPB)                 *******************/
-
-/****************     Initialize Work Queue Command Format (WQCF) ***********/
-
-#define M_WOPT_IWQ              0x8000          /* initialize work queue */
-#define M_WOPT_PE               0x0008          /* parity check enable */
-#define M_WOPT_FE               0x0004          /* freeze on error enable */
-#define M_WOPT_TM               0x0002          /* target mode enable */
-#define M_WOPT_AE               0x0001          /* abort enable */
-
-typedef struct wqcf
-{                                       /* Initialize Work Queue Cmd Format*/
-    volatile u_short      wqcf_CMD;       /* Command Normally (0x42) */
-    volatile u_short      wqcf_OPTION;    /* Command Options */
-    volatile u_short      wqcf_STATUS;    /* Return Status */
-    volatile u_short      wqcf_RES0;      /* Reserved word */
-    volatile u_char       wqcf_NVCT;      /* Normal Completion Vector */
-    volatile u_char       wqcf_EVCT;      /* Error Completion Vector */
-    volatile u_short      wqcf_ILVL;      /* Interrupt Level */
-    volatile u_short      wqcf_RES1[8];   /* Reserved words */
-    volatile u_short      wqcf_WORKQ;     /* Work Queue Number */
-    volatile u_short      wqcf_WOPT;      /* Work Queue Options */
-    volatile u_short      wqcf_SLOTS;     /* Number of slots in Work Queues */
-    volatile u_short      wqcf_RES2;      /* Reserved word */
-    volatile LONGV        wqcf_CMDTO;     /* Command timeout */
-    volatile u_short      wqcf_RES3;      /* Reserved word */
-} M328_WQCF;
-
-/**************** END Initialize Work Queue Command Format (WQCF) ***********/
-
-/****************     SCSI Reset Command Format (SRCF) ***********/
-
-typedef struct srcf
-{                                       /* SCSI Reset Cmd Format*/
-    volatile u_short      srcf_CMD;       /* Command Normally (0x22) */
-    volatile u_short      srcf_OPTION;    /* Command Options */
-    volatile u_short      srcf_STATUS;    /* Return Status */
-    volatile u_short      srcf_RES0;      /* Reserved word */
-    volatile u_char       srcf_NVCT;      /* Normal Completion Vector */
-    volatile u_char       srcf_EVCT;      /* Error Completion Vector */
-    volatile u_short      srcf_ILVL;      /* Interrupt Level */
-    volatile u_short      srcf_RES1[8];   /* Reserved words */
-    volatile u_short      srcf_BUSID;     /* SCSI bus ID to reset */
-} M328_SRCF;
-
-/**************** END SCSI Reset Command Format (SRCF) ***********/
-
-/****************     Device Reinitialize Command Format (DRCF) ***********/
-
-typedef struct drcf
-{                                       /* Device Reinitialize Cmd Format*/
-    volatile u_short      drcf_CMD;       /* Command Normally (0x4C) */
-    volatile u_short      drcf_OPTION;    /* Command Options */
-    volatile u_short      drcf_STATUS;    /* Return Status */
-    volatile u_short      drcf_RES0;      /* Reserved word */
-    volatile u_char       drcf_NVCT;      /* Normal Completion Vector */
-    volatile u_char       drcf_EVCT;      /* Error Completion Vector */
-    volatile u_short      drcf_ILVL;      /* Interrupt Level */
-    volatile u_short      drcf_RES1[9];   /* Reserved words */
-    volatile u_short      drcf_UNIT;      /* Unit Address */
-} M328_DRCF;
-
-/**************** END SCSI Reset Command Format (SRCF) ***********/
-
-/**************** Host Down Loadable Firmware (HDLF) ***********/
-
-typedef struct hdlf
-{                                       /* Host Down Loadable Firmware cmd */
-    volatile u_short      hdlf_CMD;       /* Command Normally (0x4F) */
-    volatile u_short      hdlf_OPTION;    /* Command Options */
-    volatile u_short      hdlf_STATUS;    /* Return Status */
-    volatile u_short      hdlf_RES0;      /* Reserved word */
-    volatile u_char       hdlf_NVCT;      /* Normal Completion Vector */
-    volatile u_char       hdlf_EVCT;      /* Error Completion Vector */
-    volatile u_short      hdlf_ILVL;      /* Interrupt Level */
-    volatile u_short      hdlf_RES1;      /* Reserved word */
-    volatile u_short      hdlf_ADDR;      /* Address type and modifer */
-    volatile LONGV        hdlf_BUFF;      /* Buffer Address */
-    volatile LONGV        hdlf_LENGTH;    /* Max-Transfer Length */
-    volatile LONGV        hdlf_CSUM;      /* Checksum */
-    volatile u_short      hdlf_RES2;      /* Reserved word */
-    volatile u_short      hdlf_SEQ;       /* Sequence number */
-    volatile u_short      hdlf_RES3[6];   /* Reserved words */
-} M328_HDLF;
-
-#define M328_INITIALIZE_DOWNLOAD        0x0010
-#define M328_TRANSFER_PACKET            0x0020
-#define M328_PROGRAM_FLASH              0x0040
-#define M328_MOTOROLA_S_RECORDS         0x1000
-
-/**************** END SCSI Reset Command Format (SRCF) ***********/
-
-/****************     Short I/O Format                   *******************/
-
-struct vsreg
-{
-    M328_MCSB   sh_MCSB;           /* Master Control / Status Block */
-    M328_CQE    sh_MCE;            /* Master Command Entry */
-    M328_CQE    sh_CQE[NUM_CQE];   /* Command Queue Entry */
-    M328_IOPB   sh_IOPB[NUM_IOPB]; /* Host IOPB   Space */
-    M328_IOPB   sh_MCE_IOPB;       /* Host MCE IOPB Space */
-    M328_CIB    sh_CIB;            /* Controller Initialization Block */
-    volatile u_char sh_HUS[S_HUS_FREE];/* Host Usable Space */
-    M328_HSB    sh_HSB;            /* Host Semaphore Block */
-    M328_CRB    sh_CRB;            /* Command Response Block */
-    M328_IOPB   sh_RET_IOPB;       /* Returned IOPB */
-    M328_CSB    sh_CSS;            /* Controller Specific Space/Block */
-};
-
-#define CRSW		sc->sc_vsreg->sh_CRB.crb_CRSW
-#define THAW_REG	sc->sc_vsreg->sh_MCSB.mcsb_THAW
-#define THAW(x)		THAW_REG = (((x) << 8) | M_THAW_TWQE)
-
-#define SELECTION_TIMEOUT               250     /* milliseconds */
-#define VME_BUS_TIMEOUT                 0xF     /* units of 30ms */
-
-/**************** END Short I/O Format                   *******************/
+#define	sh_CSS		(S_SHORTIO - CSB_SIZE)
+#define	sh_RET_IOPB	(sh_CSS - IOPB_LONG_SIZE)
+#define	sh_CRB		(sh_RET_IOPB - CRB_SIZE)
+#define	sh_CEVSB	sh_CRB
+#define	sh_HSB		(sh_CRB - HSB_SIZE)
 
-/*
- *  SCSI IOPB definitions
- */
+#if (sh_CIB + CIB_SIZE > sh_HSB)
+#error	invalid memory layout
+#endif
 
-#define IOPB_PASS_THRU      0x20    /* SCSI Pass Through commands */
-#define IOPB_PASS_THRU_EXT  0x21    /* SCSI Pass Through Extended commands */
-#define IOPB_RESET          0x22    /* SCSI Reset bus */
+#define	SELECTION_TIMEOUT		250	/* milliseconds */
+#define	VME_BUS_TIMEOUT			15	/* units of 30ms */
+#define	M328_INFINITE_TIMEOUT		0	/* wait forever */
 
 /*
- *  SCSI Control IOPB's
+ * IOPB command codes
  */
 
-#define CNTR_DIAG           0x40        /* Perform Diagnostics */
-#define CNTR_INIT           0x41        /* Initialize Controller */
-#define CNTR_INIT_WORKQ     0x42        /* Initialize Work Queue */
-#define CNTR_DUMP_INIT      0x43        /* Dump Initialization Parameters */
-#define CNTR_DUMP_WORDQ     0x44        /* Dump work Queue Parameters */
-#define CNTR_CANCEL_IOPB    0x48        /* Cancel command tag */
-#define CNTR_FLUSH_WORKQ    0x49        /* Flush Work Queue */
-#define CNTR_DEV_REINIT     0x4C        /* Reinitialize Device */
-#define CNTR_ISSUE_ABORT    0x4E        /* An abort has been issued */
-#define CNTR_DOWNLOAD_FIRMWARE 0x4F     /* Download firmware (COUGAR) */
-
+#define	IOPB_PASSTHROUGH		0x20 /* SCSI passthrough commands */
+#define	IOPB_PASSTHROUGH_EXT		0x21 /* SCSI passthrough extended */
+#define	IOPB_RESET			0x22 /* reset bus */
+
+#define	CNTR_DIAG			0x40 /* perform diagnostics */
+#define	CNTR_INIT			0x41 /* initialize controller */
+#define	CNTR_INIT_WORKQ			0x42 /* initialize work queue */
+#define	CNTR_DUMP_INIT			0x43 /* dump initialization parameters */
+#define	CNTR_DUMP_WORDQ			0x44 /* dump work queue parameters */
+#define	CNTR_CANCEL_IOPB		0x48 /* cancel command tag */
+#define	CNTR_FLUSH_WORKQ		0x49 /* flush work queue */
+#define	CNTR_DEV_REINIT			0x4c /* reinitialize device */
+#define	CNTR_ISSUE_ABORT		0x4e /* abort has been issued */
+#define	CNTR_DOWNLOAD_FIRMWARE		0x4f /* download firmware (COUGAR) */
 
 /*
- *  Memory types
+ * Memory types
  */
 
-#define MEMT_16BIT              1       /* 16 Bit Memory type */
-#define MEMT_32BIT              2       /* 32 Bit Memory type */
-#define MEMT_SHIO               3       /* Short I/O Memory type */
-#define MEMTYPE         MEMT_32BIT      /* do 32-bit transfers */
+#define	MEMT_16BIT	1	/* 16 bit memory type */
+#define	MEMT_32BIT	2	/* 32 bit memory type */
+#define	MEMT_SHIO	3	/* short I/O memory type */
+#define	MEMTYPE		MEMT_32BIT
 
 /*
- *  Transfer types
+ * Transfer types
  */
 
-#define TT_NORMAL               0       /* Normal Mode Tranfers */
-#define TT_BLOCK                1       /* block  Mode Tranfers */
-#define TT_DISABLE_INC_ADDR     2       /* Disable Incrementing Addresses */
-#define TT_D64                  3       /* D64 Mode Transfers */
+#define	TT_NORMAL		0	/* normal mode tranfers */
+#define	TT_BLOCK		1	/* block mode tranfers */
+#define	TT_DISABLE_INC_ADDR	2	/* disable incrementing addresses */
+#define	TT_D64			3	/* D64 mode transfers */
 
 /*
- *      Error codes.
+ * Error codes
  */
 
-#define MACSI_GOOD_STATUS       0x00    /* Good status */
-#define MACSI_QUEUE_FULL        0x01    /* The work queue is full */
-#define MACSI_CMD_CODE_ERR      0x04    /* The IOPB command field is invalid */
-#define MACSI_QUEUE_NUMBER_ERR  0x05    /* Invalid queue number */
-
-#define RESET_BUS_STATUS        0x11    /* SCSI bus reset IOPB forced this */
-#define NO_SECONDARY_PORT       0x12    /* second SCSI bus not available */
-#define SCSI_DEVICE_IS_RESET    0x14    /* device has been reset */
-#define CMD_ABORT_BY_RESET      0x15    /* device has been reset */
-
-#define VME_BUS_ERROR           0x20    /* There was a VME BUS error */
-#define VME_BUS_ACC_TIMEOUT     0x21
-#define VME_BUS_BAD_ADDR        0x23
-#define VME_BUS_BAD_MEM_TYPE    0x24
-#define VME_BUS_BAD_COUNT       0x25
-#define VME_BUS_FETCH_ERROR     0x26
-#define VME_BUS_FETCH_TIMEOUT   0x27
-#define VME_BUS_POST_ERROR      0x28
-#define VME_BUS_POST_TIMEOUT    0x29
-#define VME_BUS_BAD_FETCH_ADDR  0x2A
-#define VME_BUS_BAD_POST_ADDR   0x2B
-#define VME_BUS_SG_FETCH        0x2C
-#define VME_BUS_SG_TIMEOUT      0x2D
-#define VME_BUS_SG_COUNT        0x2E
-
-#define SCSI_SELECTION_TO       0x30    /* select time out */
-#define SCSI_DISCONNECT_TIMEOUT 0x31    /* disconnect timeout */
-#define SCSI_ABNORMAL_SEQ       0x32    /* abnormal sequence */
-#define SCSI_DISCONNECT_ERR     0x33    /* disconnect error */
-#define SCSI_XFER_EXCEPTION     0x34    /* transfer cnt exception */
-#define SCSI_PARITY_ERROR       0x35    /* parity error */
-
-#define DEVICE_NO_IOPB          0x82    /* IOPB no available */
-#define IOPB_CTLR_EHX           0x83    /* IOPB counter exhausted */
-#define IOPB_DIR_ERROR          0x84    /* IOPB direction wrong */
-#define COUGAR_ERROR            0x86    /* COUGAR unrecoverable error */
-#define MACSI_INCORRECT_HARDWARE 0x90    /* Insufficient memory */
-#define MACSI_ILGL_IOPB_VAL     0x92    /* Invalid field in the IOPB */
-#define MACSI_ILLEGAL_IMAGE     0x9C    /* Submitted fails reuested action */
-#define IOPB_TYPE_ERR           0xC0    /* IOPB type not 0 */
-#define IOPB_TIMEOUT            0xC1    /* IOPB timed out */
-
-#define COUGAR_PANIC            0xFF    /* COUGAR paniced */
-
-#define MACSI_INVALID_TIMEOUT   0x843   /* The SCSI byte to byte timer expired */
+#define	MACSI_GOOD_STATUS	0x00
+#define	MACSI_QUEUE_FULL	0x01
+#define	MACSI_CMD_CODE_ERR	0x04
+#define	MACSI_QUEUE_NUMBER_ERR	0x05
+
+#define	RESET_BUS_STATUS	0x11	/* SCSI bus reset IOPB forced this */
+#define	NO_SECONDARY_PORT	0x12	/* second SCSI bus not available */
+#define	SCSI_DEVICE_IS_RESET	0x14
+#define	CMD_ABORT_BY_RESET	0x15
+
+#define	VME_BUS_ERROR		0x20
+#define	VME_BUS_ACC_TIMEOUT	0x21
+#define	VME_BUS_BAD_ADDR	0x23
+#define	VME_BUS_BAD_MEM_TYPE	0x24
+#define	VME_BUS_BAD_COUNT	0x25
+#define	VME_BUS_FETCH_ERROR	0x26
+#define	VME_BUS_FETCH_TIMEOUT	0x27
+#define	VME_BUS_POST_ERROR	0x28
+#define	VME_BUS_POST_TIMEOUT	0x29
+#define	VME_BUS_BAD_FETCH_ADDR	0x2a
+#define	VME_BUS_BAD_POST_ADDR	0x2b
+#define	VME_BUS_SG_FETCH	0x2c
+#define	VME_BUS_SG_TIMEOUT	0x2d
+#define	VME_BUS_SG_COUNT	0x2e
+
+#define	SCSI_SELECTION_TO	0x30
+#define	SCSI_DISCONNECT_TIMEOUT	0x31
+#define	SCSI_ABNORMAL_SEQ	0x32
+#define	SCSI_DISCONNECT_ERR	0x33
+#define	SCSI_XFER_EXCEPTION	0x34
+#define	SCSI_PARITY_ERROR	0x35
+
+#define	DEVICE_NO_IOPB		0x82
+#define	IOPB_CTLR_EXH		0x83
+#define	IOPB_DIR_ERROR		0x84
+#define	COUGAR_ERROR		0x86
+#define	MACSI_INCORRECT_HW	0x90
+#define	MACSI_ILGL_IOPB_VAL	0x92
+#define	MACSI_ILLEGAL_IMAGE	0x9c
+#define	IOPB_TYPE_ERR		0xc0	/* IOPB type not 0 */
+#define	IOPB_TIMEOUT		0xc1
+
+#define	COUGAR_PANIC		0xff
+
+#define	MACSI_INVALID_TIMEOUT	0x843
 
 /*
- *      VME addressing modes
+ * VME addressing modes
  */
 
-#define ADRM_STD_S_P            0x3E    /* Standard Supervisory Program */
-#define ADRM_STD_S_D            0x3D    /* Standard Supervisory Data */
-#define ADRM_STD_N_P            0x3A    /* Standard Normal Program */
-#define ADRM_STD_N_D            0x39    /* Standard Normal Data */
-#define ADRM_SHT_S_IO           0x2D    /* Short Supervisory IO */
-#define ADRM_SHT_N_IO           0x29    /* Short Normal IO */
-#define ADRM_EXT_S_P            0x0E    /* Extended Supervisory Program */
-#define ADRM_EXT_S_D            0x0D    /* Extended Supervisory Data */
-#define ADRM_EXT_N_P            0x0A    /* Extended Normal Program */
-#define ADRM_EXT_N_D            0x09    /* Extended Normal Data */
-#define ADRM_EXT_S_BM           0x0F    /* Extended Supervisory Block Mode */
-#define ADRM_EXT_S_D64          0x0C    /* Extended Supervisory D64 Mode */
-
-#define ADDR_MOD        ( (TT_NORMAL << 10) | (MEMTYPE << 8) | ADRM_EXT_S_D )
-#define BLOCK_MOD       ( (TT_BLOCK << 10) | (MEMTYPE << 8) | ADRM_EXT_S_BM )
-#define D64_MOD         ( (TT_D64 << 10) | (MEMTYPE << 8) | ADRM_EXT_S_D64 )
-#define SHIO_MOD        ( (TT_NORMAL << 10) | (MEMT_SHIO << 8) | ADRM_SHT_N_IO)
-
-#endif /* _M328REG_H_ */
+#define	ADRM_STD_S_P		0x3e	/* standard supervisory program */
+#define	ADRM_STD_S_D		0x3d	/* standard supervisory data */
+#define	ADRM_STD_N_P		0x3a	/* standard normal program */
+#define	ADRM_STD_N_D		0x39	/* standard normal data */
+#define	ADRM_SHT_S_IO		0x2d	/* short supervisory I/O */
+#define	ADRM_SHT_N_IO		0x29	/* short normal I/O */
+#define	ADRM_EXT_S_P		0x0e	/* extended supervisory program */
+#define	ADRM_EXT_S_D		0x0d	/* extended supervisory data */
+#define	ADRM_EXT_N_P		0x0a	/* extended normal program */
+#define	ADRM_EXT_N_D		0x09	/* extended normal data */
+#define	ADRM_EXT_S_BM		0x0f	/* extended supervisory block mode */
+#define	ADRM_EXT_S_D64		0x0c	/* extended supervisory D64 mode */
+
+#define	ADDR_MOD	((TT_NORMAL << 10) | (MEMTYPE << 8) | ADRM_EXT_S_D)
+#define	BLOCK_MOD	((TT_BLOCK << 10) | (MEMTYPE << 8) | ADRM_EXT_S_BM)
+#define	D64_MOD		((TT_D64 << 10) | (MEMTYPE << 8) | ADRM_EXT_S_D64)
+#define	SHIO_MOD	((TT_NORMAL << 10) | (MEMT_SHIO << 8) | ADRM_SHT_N_IO)
+
+#endif	/* _MVME328_REG_H_ */
diff --git a/sys/arch/mvme88k/dev/vsvar.h b/sys/arch/mvme88k/dev/vsvar.h
index 35f3b058914..49ac931fe4a 100644
--- a/sys/arch/mvme88k/dev/vsvar.h
+++ b/sys/arch/mvme88k/dev/vsvar.h
@@ -1,5 +1,6 @@
-/*	$OpenBSD: vsvar.h,v 1.10 2004/05/21 10:24:42 miod Exp $ */
+/*	$OpenBSD: vsvar.h,v 1.11 2004/05/22 19:34:12 miod Exp $	*/
 /*
+ * Copyright (c) 2004, Miodrag Vallat.
  * Copyright (c) 1999 Steve Murphree, Jr.
  * Copyright (c) 1990 The Regents of the University of California.
  * All rights reserved.
@@ -31,8 +32,8 @@
  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  * SUCH DAMAGE.
  */
-#ifndef _VSVAR_H_
-#define _VSVAR_H_
+#ifndef	_VSVAR_H_
+#define	_VSVAR_H_
 
 /*
  * The largest single request will be MAXPHYS bytes which will require
@@ -41,105 +42,90 @@
  * buffer is not page aligned (+1).
  */
 #define	DMAMAXIO	(MAXPHYS/NBPG+1)
-#define  LO(x) (u_short)((unsigned long)x & 0x0000FFFF)
-#define  HI(x) (u_short)((unsigned long)x >> 16)
-#define  OFF(x) (u_short)((vaddr_t)x - (vaddr_t)sc->sc_vsreg)
+#define	OFF(x)	(u_int16_t)(x)
 
-/****************     Scater/Gather Stuff                *******************/
+/*
+ * scatter/gather structures
+ */
 
 typedef struct {
 	union {
 		unsigned short bytes :16;
-   #define MAX_SG_BLOCK_SIZE	(1<<16)	/* the size *has* to be always *smaller* */
+#define	MAX_SG_BLOCK_SIZE	(1<<16)
 		struct {
 			unsigned short :8;
-			unsigned short gather :8;
+			unsigned short gather:8;
 		} scatter;
 	} count;
-	LONGV           address;
-	unsigned short  link :1;
-	unsigned short  :3;
-	unsigned short  transfer_type :2;
-	/* 				0x0 is reserved */
-   #define SHORT_TREANSFER 		0x1
-   #define LONG_TRANSFER			0x2
-   #define SCATTER_GATTER_LIST_IN_SHORT_IO	0x3
-	unsigned short  memory_type :2;
-   #define NORMAL_TYPE			0x0
-   #define BLOCK_MODE			0x1
-	/*				0x2 is reserved */
-	/*				0x3 is reserved */
-	unsigned short  address_modifier :8;
+	u_int16_t addrhi, addrlo;	/* split due to alignment */
+	unsigned short link:1;
+	unsigned short :3;
+	unsigned short transfer_type:2;
+#define	SHORT_TRANSFER			0x1
+#define	LONG_TRANSFER			0x2
+#define	SCATTER_GATTER_LIST_IN_SHORT_IO	0x3
+	unsigned short memory_type:2;
+#define	NORMAL_TYPE	0x0
+#define	BLOCK_MODE	0x1
+	unsigned short address_modifier:8;
 } sg_list_element_t;
 
 typedef sg_list_element_t * scatter_gather_list_t;
 
-#define MAX_SG_ELEMENTS 64
+#define	MAX_SG_ELEMENTS	64
 
 struct m328_sg {
-	struct m328_sg  *up;
-	int                     elements;
-	int                     level;
-	struct m328_sg  *down[MAX_SG_ELEMENTS];
+	struct m328_sg *up;
+	int elements;
+	int level;
+	struct m328_sg *down[MAX_SG_ELEMENTS];
 	sg_list_element_t list[MAX_SG_ELEMENTS];
 };
 
 typedef struct m328_sg *M328_SG;
 
 typedef struct {
-   struct scsi_xfer  *xs;
-   M328_SG           top_sg_list;
+	struct scsi_xfer *xs;
+	M328_SG top_sg_list;
 } M328_CMD;
 
-/**************** END Scater/Gather Stuff                *******************/
-
-struct  vs_softc {
-	struct  device sc_dev;
-	struct  intrhand sc_ih_e;
-	struct  intrhand sc_ih_n;
-	struct  evcnt sc_intrcnt_e;
-	struct  evcnt sc_intrcnt_n;
-	u_short  sc_ipl;
-	u_short  sc_evec;
-	u_short  sc_nvec;
-	struct  scsi_link sc_link;	/* proto for sub devices */
-	struct   vsreg  *sc_vsreg;
+struct vs_softc {
+	struct device		sc_dev;
+	paddr_t			sc_paddr;
+	bus_space_tag_t		sc_iot;
+	bus_space_handle_t	sc_ioh;
+	struct intrhand		sc_ih_e, sc_ih_n;
+	struct evcnt		sc_intrcnt_e, sc_intrcnt_n;
+	int			sc_ipl;
+	int			sc_evec, sc_nvec;
+	struct scsi_link	sc_link;
 };
 
-/* sync states */
-#define SYNC_START	0	/* no sync handshake started */
-#define SYNC_SENT	1	/* we sent sync request, no answer yet */
-#define SYNC_DONE	2	/* target accepted our (or inferior) settings,
-				   or it rejected the request and we stay async */
-
-#define IOPB_SCSI    0x20
-#define IOPB_RESET   0x22
-#define IOPB_INIT    0x41
-#define IOPB_WQINIT  0x42
-#define IOPB_DEV_RESET   0x4D
-
-#define OPT_INTEN    0x0001
-#define OPT_INTDIS   0x0000
-#define OPT_SG       0x0002
-#define OPT_SST      0x0004
-#define OPT_SIT      0x0040
-#define OPT_READ     0x0000
-#define OPT_WRITE    0x0100
-
-#define AM_S32       0x01
-#define AM_S16       0x05
-#define AM_16        0x0100
-#define AM_32        0x0200
-#define AM_SHORT     0x0300
-#define AM_NORMAL    0x0000
-#define AM_BLOCK     0x0400
-#define AM_D64BLOCK  0x0C00
-
-#define WQO_AE             0x0001   /* abort enable bit */
-#define WQO_FOE            0x0004   /* freeze on error */
-#define WQO_PE             0x0008   /* parity enable bit */
-#define WQO_ARE            0x0010   /* autosense recovery enable bit */
-#define WQO_RFWQ           0x0020   /* report frozen work queue bit */
-#define WQO_INIT           0x8000   /* work queue init bit */
+/* Access macros */
+
+#define	vs_read(w,o) \
+	bus_space_read_##w (sc->sc_iot, sc->sc_ioh, (o))
+#define	vs_write(w,o,v) \
+	bus_space_write_##w (sc->sc_iot, sc->sc_ioh, (o), (v))
+#define	vs_bzero(o,s) \
+	bus_space_set_region_2(sc->sc_iot, sc->sc_ioh, (o), 0, (s) / 2)
+
+#define	cib_read(w,o)		vs_read(w, sh_CIB + (o))
+#define	cib_write(w,o,v)	vs_write(w, sh_CIB + (o), (v))
+#define	crb_read(w,o)		vs_read(w, sh_CRB + (o))
+#define	crb_write(w,o,v)	vs_write(w, sh_CRB + (o), (v))
+#define	mce_read(w,o)		vs_read(w, sh_MCE + (o))
+#define	mce_write(w,o,v)	vs_write(w, sh_MCE + (o), (v))
+#define	mce_iopb_read(w,o)	vs_read(w, sh_MCE_IOPB + (o))
+#define	mce_iopb_write(w,o,v)	vs_write(w, sh_MCE_IOPB + (o), (v))
+#define	mcsb_read(w,o)		vs_read(w, sh_MCSB + (o))
+#define	mcsb_write(w,o,v)	vs_write(w, sh_MCSB + (o), (v))
+
+#define	CRSW		crb_read(2, CRB_CRSW)
+#define	CRB_CLR_DONE	crb_write(2, CRB_CRSW, 0)
+#define	CRB_CLR_ER	crb_write(2, CRB_CRSW, CRSW & ~M_CRSW_ER)
+
+#define	THAW_REG	mcsb_read(2, MCSB_THAW)
+#define	THAW(x)		mcsb_write(2, MCSB_THAW, ((x) << 8) | M_THAW_TWQE)
 
 #endif /* _M328VAR_H */