Add detection for Spectre-BHB related CLRBHB, ECBHB and CSV2_3/HCXT

feature bits.

ok kettenis@

2 files changed, 42 insertions, 3 deletions

diff --git a/sys/arch/arm64/arm64/cpu.c b/sys/arch/arm64/arm64/cpu.c
index 5f2e62f1ad1..d35206f097c 100644
--- a/sys/arch/arm64/arm64/cpu.c
+++ b/sys/arch/arm64/arm64/cpu.c
@@ -1,4 +1,4 @@
-/*	$OpenBSD: cpu.c,v 1.74 2022/12/09 20:37:39 patrick Exp $	*/
+/*	$OpenBSD: cpu.c,v 1.75 2022/12/09 21:23:24 patrick Exp $	*/
 
 /*
  * Copyright (c) 2016 Dale Rahn <drahn@dalerahn.com>
@@ -200,6 +200,7 @@ int cpu_node;
 
 uint64_t cpu_id_aa64isar0;
 uint64_t cpu_id_aa64isar1;
+uint64_t cpu_id_aa64isar2;
 uint64_t cpu_id_aa64pfr0;
 uint64_t cpu_id_aa64pfr1;
 
@@ -382,6 +383,10 @@ cpu_identify(struct cpu_info *ci)
 		printf("\n%s: mismatched ID_AA64ISAR1_EL1",
 		    ci->ci_dev->dv_xname);
 	}
+	if (READ_SPECIALREG(id_aa64isar2_el1) != cpu_id_aa64isar2) {
+		printf("\n%s: mismatched ID_AA64ISAR2_EL1",
+		    ci->ci_dev->dv_xname);
+	}
 	if (READ_SPECIALREG(id_aa64pfr0_el1) != cpu_id_aa64pfr0) {
 		printf("\n%s: mismatched ID_AA64PFR0_EL1",
 		    ci->ci_dev->dv_xname);
@@ -547,6 +552,16 @@ cpu_identify(struct cpu_info *ci)
 	}
 
 	/*
+	 * ID_AA64ISAR2
+	 */
+	id = READ_SPECIALREG(id_aa64isar2_el1);
+
+	if (ID_AA64ISAR2_CLRBHB(id) >= ID_AA64ISAR2_CLRBHB_IMPL) {
+		printf("%sCLRBHB", sep);
+		sep = ",";
+	}
+
+	/*
 	 * ID_AA64MMFR0
 	 *
 	 * We only print ASIDBits for now.
@@ -595,6 +610,11 @@ cpu_identify(struct cpu_info *ci)
 	if (ID_AA64MMFR1_HAFDBS(id) >= ID_AA64MMFR1_HAFDBS_AF_DBS)
 		printf("DBS");
 
+	if (ID_AA64MMFR1_ECBHB(id) >= ID_AA64MMFR1_ECBHB_IMPL) {
+		printf("%sECBHB", sep);
+		sep = ",";
+	}
+
 	/*
 	 * ID_AA64PFR0
 	 */
@@ -611,6 +631,8 @@ cpu_identify(struct cpu_info *ci)
 	}
 	if (ID_AA64PFR0_CSV2(id) >= ID_AA64PFR0_CSV2_SCXT)
 		printf("+SCXT");
+	if (ID_AA64PFR0_CSV2(id) >= ID_AA64PFR0_CSV2_HCXT)
+		printf("+HCXT");
 
 	if (ID_AA64PFR0_DIT(id) >= ID_AA64PFR0_DIT_IMPL) {
 		printf("%sDIT", sep);
@@ -630,6 +652,8 @@ cpu_identify(struct cpu_info *ci)
 	printf("\nID_AA64ISAR0_EL1: 0x%016llx", id);
 	id = READ_SPECIALREG(id_aa64isar1_el1);
 	printf("\nID_AA64ISAR1_EL1: 0x%016llx", id);
+	id = READ_SPECIALREG(id_aa64isar2_el1);
+	printf("\nID_AA64ISAR2_EL1: 0x%016llx", id);
 	id = READ_SPECIALREG(id_aa64mmfr0_el1);
 	printf("\nID_AA64MMFR0_EL1: 0x%016llx", id);
 	id = READ_SPECIALREG(id_aa64mmfr1_el1);
@@ -742,6 +766,7 @@ cpu_attach(struct device *parent, struct device *dev, void *aux)
 #endif
 		cpu_id_aa64isar0 = READ_SPECIALREG(id_aa64isar0_el1);
 		cpu_id_aa64isar1 = READ_SPECIALREG(id_aa64isar1_el1);
+		cpu_id_aa64isar2 = READ_SPECIALREG(id_aa64isar2_el1);
 		cpu_id_aa64pfr0 = READ_SPECIALREG(id_aa64pfr0_el1);
 		cpu_id_aa64pfr1 = READ_SPECIALREG(id_aa64pfr1_el1);
 
diff --git a/sys/arch/arm64/include/armreg.h b/sys/arch/arm64/include/armreg.h
index c49789789cc..c8281a2e92a 100644
--- a/sys/arch/arm64/include/armreg.h
+++ b/sys/arch/arm64/include/armreg.h
@@ -1,4 +1,4 @@
-/* $OpenBSD: armreg.h,v 1.24 2022/11/24 14:36:07 kettenis Exp $ */
+/* $OpenBSD: armreg.h,v 1.25 2022/12/09 21:23:24 patrick Exp $ */
 /*-
  * Copyright (c) 2013, 2014 Andrew Turner
  * Copyright (c) 2015 The FreeBSD Foundation
@@ -383,6 +383,14 @@
 #define	 ID_AA64ISAR1_SPECRES_NONE	(0x0ULL << ID_AA64ISAR1_SPECRES_SHIFT)
 #define	 ID_AA64ISAR1_SPECRES_IMPL	(0x1ULL << ID_AA64ISAR1_SPECRES_SHIFT)
 
+/* ID_AA64ISAR2_EL1 */
+#define	ID_AA64ISAR2_MASK		0x00000000f0000000ULL
+#define	ID_AA64ISAR2_CLRBHB_SHIFT	28
+#define	ID_AA64ISAR2_CLRBHB_MASK	(0xfULL << ID_AA64ISAR2_CLRBHB_SHIFT)
+#define	ID_AA64ISAR2_CLRBHB(x)		((x) & ID_AA64ISAR2_CLRBHB_MASK)
+#define	 ID_AA64ISAR2_CLRBHB_NONE	(0x0ULL << ID_AA64ISAR2_CLRBHB_SHIFT)
+#define	 ID_AA64ISAR2_CLRBHB_IMPL	(0x1ULL << ID_AA64ISAR2_CLRBHB_SHIFT)
+
 /* ID_AA64MMFR0_EL1 */
 #define	ID_AA64MMFR0_MASK		0x00000000ffffffffULL
 #define	ID_AA64MMFR0_PA_RANGE_SHIFT	0
@@ -431,7 +439,7 @@
 #define	 ID_AA64MMFR0_TGRAN4_NONE	(0xf << ID_AA64MMFR0_TGRAN4_SHIFT)
 
 /* ID_AA64MMFR1_EL1 */
-#define	ID_AA64MMFR1_MASK		0x00000000ffffffffULL
+#define	ID_AA64MMFR1_MASK		0xf0000000ffffffffULL
 #define	ID_AA64MMFR1_HAFDBS_SHIFT	0
 #define	ID_AA64MMFR1_HAFDBS_MASK	(0xf << ID_AA64MMFR1_HAFDBS_SHIFT)
 #define	ID_AA64MMFR1_HAFDBS(x)		((x) & ID_AA64MMFR1_HAFDBS_MASK)
@@ -474,6 +482,11 @@
 #define	ID_AA64MMFR1_XNX(x)		((x) & ID_AA64MMFR1_XNX_MASK)
 #define	 ID_AA64MMFR1_XNX_NONE		(0x0 << ID_AA64MMFR1_XNX_SHIFT)
 #define	 ID_AA64MMFR1_XNX_IMPL		(0x1 << ID_AA64MMFR1_XNX_SHIFT)
+#define	ID_AA64MMFR1_ECBHB_SHIFT	60
+#define	ID_AA64MMFR1_ECBHB_MASK		(0xfULL << ID_AA64MMFR1_ECBHB_SHIFT)
+#define	ID_AA64MMFR1_ECBHB(x)		((x) & ID_AA64MMFR1_ECBHB_MASK)
+#define	 ID_AA64MMFR1_ECBHB_NONE	(0x0ULL << ID_AA64MMFR1_ECBHB_SHIFT)
+#define	 ID_AA64MMFR1_ECBHB_IMPL	(0x1ULL << ID_AA64MMFR1_ECBHB_SHIFT)
 
 /* ID_AA64PFR0_EL1 */
 #define	ID_AA64PFR0_MASK		0xff0fffffffffffffULL
@@ -552,6 +565,7 @@
 #define	 ID_AA64PFR0_CSV2_UNKNOWN	(0x0ULL << ID_AA64PFR0_CSV2_SHIFT)
 #define	 ID_AA64PFR0_CSV2_IMPL		(0x1ULL << ID_AA64PFR0_CSV2_SHIFT)
 #define	 ID_AA64PFR0_CSV2_SCXT		(0x2ULL << ID_AA64PFR0_CSV2_SHIFT)
+#define	 ID_AA64PFR0_CSV2_HCXT		(0x3ULL << ID_AA64PFR0_CSV2_SHIFT)
 #define	ID_AA64PFR0_CSV3_SHIFT		60
 #define	ID_AA64PFR0_CSV3_MASK		(0xfULL << ID_AA64PFR0_CSV3_SHIFT)
 #define	ID_AA64PFR0_CSV3(x)		((x) & ID_AA64PFR0_CSV3_MASK)