manually inline tlbflushg. it's short and there's only one caller.

ok deraadt

4 files changed, 38 insertions, 51 deletions

diff --git a/sys/arch/amd64/amd64/cpu.c b/sys/arch/amd64/amd64/cpu.c
index 280fde86dc2..57b75f22fe3 100644
--- a/sys/arch/amd64/amd64/cpu.c
+++ b/sys/arch/amd64/amd64/cpu.c
@@ -1,4 +1,4 @@
-/*	$OpenBSD: cpu.c,v 1.103 2017/04/30 16:45:45 mpi Exp $	*/
+/*	$OpenBSD: cpu.c,v 1.104 2017/05/27 12:21:50 tedu Exp $	*/
 /* $NetBSD: cpu.c,v 1.1 2003/04/26 18:39:26 fvdl Exp $ */
 
 /*-
@@ -528,7 +528,14 @@ cpu_init(struct cpu_info *ci)
 
 #ifdef MULTIPROCESSOR
 	ci->ci_flags |= CPUF_RUNNING;
-	tlbflushg();
+	/*
+	 * Big hammer: flush all TLB entries, including ones from PTE's
+	 * with the G bit set.  This should only be necessary if TLB
+	 * shootdown falls far behind.
+	 */
+	cr4 = rcr4();
+	lcr4(cr4 & ~CR4_PGE);
+	lcr4(cr4);
 #endif
 }
 
diff --git a/sys/arch/amd64/include/cpufunc.h b/sys/arch/amd64/include/cpufunc.h
index 516c0af2890..3e3b104c239 100644
--- a/sys/arch/amd64/include/cpufunc.h
+++ b/sys/arch/amd64/include/cpufunc.h
@@ -1,4 +1,4 @@
-/*	$OpenBSD: cpufunc.h,v 1.17 2017/05/27 10:22:50 tedu Exp $	*/
+/*	$OpenBSD: cpufunc.h,v 1.18 2017/05/27 12:21:50 tedu Exp $	*/
 /*	$NetBSD: cpufunc.h,v 1.3 2003/05/08 10:27:43 fvdl Exp $	*/
 
 /*-
@@ -147,19 +147,6 @@ tlbflush(void)
 	__asm volatile("movq %0,%%cr3" : : "r" (val));
 }
 
-static __inline void
-tlbflushg(void)
-{
-	/*
-	 * Big hammer: flush all TLB entries, including ones from PTE's
-	 * with the G bit set.  This should only be necessary if TLB
-	 * shootdown falls far behind.
-	 */
-	u_int cr4 = rcr4();
-	lcr4(cr4 & ~CR4_PGE);
-	lcr4(cr4);
-}
-
 #ifdef notyet
 void	setidt(int idx, /*XXX*/caddr_t func, int typ, int dpl);
 #endif
diff --git a/sys/arch/i386/i386/cpu.c b/sys/arch/i386/i386/cpu.c
index c2d0e72d248..9d4f16fde1b 100644
--- a/sys/arch/i386/i386/cpu.c
+++ b/sys/arch/i386/i386/cpu.c
@@ -1,4 +1,4 @@
-/*	$OpenBSD: cpu.c,v 1.82 2017/04/30 16:45:45 mpi Exp $	*/
+/*	$OpenBSD: cpu.c,v 1.83 2017/05/27 12:21:50 tedu Exp $	*/
 /* $NetBSD: cpu.c,v 1.1.2.7 2000/06/26 02:04:05 sommerfeld Exp $ */
 
 /*-
@@ -410,7 +410,32 @@ cpu_init(struct cpu_info *ci)
 
 #ifdef MULTIPROCESSOR
 	ci->ci_flags |= CPUF_RUNNING;
-	tlbflushg();
+	/*
+	 * Big hammer: flush all TLB entries, including ones from PTE's
+	 * with the G bit set.  This should only be necessary if TLB
+	 * shootdown falls far behind.
+	 *
+	 * Intel Architecture Software Developer's Manual, Volume 3,
+	 *	System Programming, section 9.10, "Invalidating the
+	 * Translation Lookaside Buffers (TLBS)":
+	 * "The following operations invalidate all TLB entries, irrespective
+	 * of the setting of the G flag:
+	 * ...
+	 * "(P6 family processors only): Writing to control register CR4 to
+	 * modify the PSE, PGE, or PAE flag."
+	 *
+	 * (the alternatives not quoted above are not an option here.)
+	 *
+	 * If PGE is not in use, we reload CR3 for the benefit of
+	 * pre-P6-family processors.
+	 */
+
+	if (cpu_feature & CPUID_PGE) {
+		cr4 = rcr4();
+		lcr4(cr4 & ~CR4_PGE);
+		lcr4(cr4);
+	} else
+		tlbflush();
 #endif
 }
 
diff --git a/sys/arch/i386/include/cpufunc.h b/sys/arch/i386/include/cpufunc.h
index 3bcd61ab84f..8ae5382d828 100644
--- a/sys/arch/i386/include/cpufunc.h
+++ b/sys/arch/i386/include/cpufunc.h
@@ -1,4 +1,4 @@
-/*	$OpenBSD: cpufunc.h,v 1.24 2017/04/30 13:04:49 mpi Exp $	*/
+/*	$OpenBSD: cpufunc.h,v 1.25 2017/05/27 12:21:50 tedu Exp $	*/
 /*	$NetBSD: cpufunc.h,v 1.8 1994/10/27 04:15:59 cgd Exp $	*/
 
 /*
@@ -56,7 +56,6 @@ static __inline u_int rcr3(void);
 static __inline void lcr4(u_int);
 static __inline u_int rcr4(void);
 static __inline void tlbflush(void);
-static __inline void tlbflushg(void);
 static __inline void disable_intr(void);
 static __inline void enable_intr(void);
 static __inline u_int read_eflags(void);
@@ -150,37 +149,6 @@ tlbflush(void)
 	__asm volatile("movl %0,%%cr3" : : "r" (val));
 }
 
-static __inline void
-tlbflushg(void)
-{
-	/*
-	 * Big hammer: flush all TLB entries, including ones from PTE's
-	 * with the G bit set.  This should only be necessary if TLB
-	 * shootdown falls far behind.
-	 *
-	 * Intel Architecture Software Developer's Manual, Volume 3,
-	 *	System Programming, section 9.10, "Invalidating the
-	 * Translation Lookaside Buffers (TLBS)":
-	 * "The following operations invalidate all TLB entries, irrespective
-	 * of the setting of the G flag:
-	 * ...
-	 * "(P6 family processors only): Writing to control register CR4 to
-	 * modify the PSE, PGE, or PAE flag."
-	 *
-	 * (the alternatives not quoted above are not an option here.)
-	 *
-	 * If PGE is not in use, we reload CR3 for the benefit of
-	 * pre-P6-family processors.
-	 */
-
-	if (cpu_feature & CPUID_PGE) {
-		u_int cr4 = rcr4();
-		lcr4(cr4 & ~CR4_PGE);
-		lcr4(cr4);
-	} else
-		tlbflush();
-}
-
 #ifdef notyet
 void	setidt(int idx, /*XXX*/caddr_t func, int typ, int dpl);
 #endif