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authorVisa Hankala <visa@cvs.openbsd.org>2018-02-18 14:42:33 +0000
committerVisa Hankala <visa@cvs.openbsd.org>2018-02-18 14:42:33 +0000
commit59d4eaf9c8738de8016fecd5913756987bfee0bf (patch)
treef2b094fc8cc58a411ae2023cbd67c95e6b0cab8a /sys/arch
parent572e72a11ed07a6f88cf2c09d04eac065067a205 (diff)
Replace a full memory barrier with a write-write barrier. The full
barrier is overkill when forcing parameter visibility before IPIs.
Diffstat (limited to 'sys/arch')
-rw-r--r--sys/arch/mips64/mips64/ipifuncs.c6
1 files changed, 4 insertions, 2 deletions
diff --git a/sys/arch/mips64/mips64/ipifuncs.c b/sys/arch/mips64/mips64/ipifuncs.c
index 92aba5f441b..5e1a6c8d094 100644
--- a/sys/arch/mips64/mips64/ipifuncs.c
+++ b/sys/arch/mips64/mips64/ipifuncs.c
@@ -1,4 +1,4 @@
-/* $OpenBSD: ipifuncs.c,v 1.17 2017/05/28 17:12:48 visa Exp $ */
+/* $OpenBSD: ipifuncs.c,v 1.18 2018/02/18 14:42:32 visa Exp $ */
/* $NetBSD: ipifuncs.c,v 1.40 2008/04/28 20:23:10 martin Exp $ */
/*-
@@ -216,7 +216,9 @@ smp_rendezvous_cpus(unsigned long map,
smp_rv_func_arg = arg;
smp_rv_waiters[0] = 0;
smp_rv_waiters[1] = 0;
- mips_sync();
+
+ /* Ensure the parameters are visible to other CPUs. */
+ membar_producer();
/* signal other processors, which will enter the IPI with interrupts off */
mips64_multicast_ipi(map, MIPS64_IPI_RENDEZVOUS);