Pegasos II support, works around new northbridge config oddities

and other artifacts found on pegII.

9 files changed, 426 insertions, 136 deletions

diff --git a/sys/arch/pegasos/include/bus.h b/sys/arch/pegasos/include/bus.h
index 0caa46a3578..302ba5ea65e 100644
--- a/sys/arch/pegasos/include/bus.h
+++ b/sys/arch/pegasos/include/bus.h
@@ -1,4 +1,4 @@
-/*	$OpenBSD: bus.h,v 1.1 2003/10/31 03:54:33 drahn Exp $	*/
+/*	$OpenBSD: bus.h,v 1.2 2004/02/04 20:07:18 drahn Exp $	*/
 
 /*
  * Copyright (c) 1997 Per Fogelstrom.  All rights reserved.
@@ -632,11 +632,22 @@ struct powerpc_bus_dmamap {
 /* This architecture does not support accessing ISA memory/io space
  * via the PCI memory/io descriptors
  * drivers must use these instead.
+ * It is possible for the machine to have two seperate ISA I/O spaces,
+ * one which the kbd/mouse controller uses, and one for
+ * the display, And of course neither of these is in the normal PCI 
+ * spaces.
+ * To allow this flexibility, HAVE seperate MD defines for 'normal'
+ * isa stuff such as keyboard/mouse and one for display for the primary
+ * display. It is perfectly legal for these to reference the same object
+ * or even the same variable.
  */
-#define ISA_SPACE_NOT_ACCESSABLE_WITH_PCI_IOT
 #define MD_ISA_IOT ppc_isa_iobus_space
 #define MD_ISA_MEMT ppc_isa_membus_space
+#define MD_DISPLAY_ISA_IOT ppc_display_isa_iobus_space
+#define MD_DISPLAY_ISA_MEMT ppc_display_isa_membus_space
 extern struct ppc_bus_space *ppc_isa_iobus_space;
 extern struct ppc_bus_space *ppc_isa_membus_space;
+extern struct ppc_bus_space *ppc_display_isa_iobus_space;
+extern struct ppc_bus_space *ppc_display_isa_membus_space;
 
 #endif /* _MACHINE_BUS_H_ */
diff --git a/sys/arch/pegasos/pci/isabr.c b/sys/arch/pegasos/pci/isabr.c
index 812de909ba3..fc02780a89f 100644
--- a/sys/arch/pegasos/pci/isabr.c
+++ b/sys/arch/pegasos/pci/isabr.c
@@ -1,4 +1,4 @@
-/*	$OpenBSD: isabr.c,v 1.3 2004/01/30 22:38:30 miod Exp $	*/
+/*	$OpenBSD: isabr.c,v 1.4 2004/02/04 20:07:18 drahn Exp $	*/
 
 /*-
  * Copyright (c) 1995 Per Fogelstrom
@@ -189,7 +189,6 @@ isabrattach(struct device *parent, struct device *self, void *aux)
 	extern intr_establish_t *intr_establish_func;
 	extern intr_disestablish_t *intr_disestablish_func;
 
-
 	pending_int_f = isa_do_pending_int;
 	intr_establish_func = isabr_intr_establish;
 	intr_disestablish_func = isabr_intr_disestablish;
@@ -486,6 +485,9 @@ isabr_iointr()
 
 	isa_vector &= (ICU_LEN - 1);	/* XXX Better safe than sorry */
 
+	if (isa_vector == 7) /* IRQ 7 == spurious */
+		goto fastout;
+
 	intrcnt[isa_vector]++;
 
 	o_imen = imen;
@@ -519,6 +521,7 @@ isabr_iointr()
 	isa_outb(IO_ICU1 + 1, imen);
 	isa_outb(IO_ICU2 + 1, imen >> 8);
 
+fastout:
 	ppc_intr_enable(1);
 
 	splx(pcpl);	/* Process pendings. */
diff --git a/sys/arch/pegasos/pci/mpcpcibus.c b/sys/arch/pegasos/pci/mpcpcibus.c
index 4cee1d4fd74..2cfd1ae7c66 100644
--- a/sys/arch/pegasos/pci/mpcpcibus.c
+++ b/sys/arch/pegasos/pci/mpcpcibus.c
@@ -1,4 +1,4 @@
-/*	$OpenBSD: mpcpcibus.c,v 1.4 2003/12/20 22:40:27 miod Exp $ */
+/*	$OpenBSD: mpcpcibus.c,v 1.5 2004/02/04 20:07:18 drahn Exp $ */
 
 /*
  * Copyright (c) 1997 Per Fogelstrom
@@ -68,6 +68,8 @@ pcitag_t mpc_make_tag(void *, int, int, int);
 void	mpc_decompose_tag(void *, pcitag_t, int *, int *, int *);
 pcireg_t mpc_conf_read(void *, pcitag_t, int);
 void	mpc_conf_write(void *, pcitag_t, int, pcireg_t);
+pcireg_t peg2_conf_read(void *, pcitag_t, int);
+void	peg2_conf_write(void *, pcitag_t, int, pcireg_t);
 
 int	mpc_intr_map(void *, pcitag_t, int, int, pci_intr_handle_t *);
 const char *mpc_intr_string(void *, pci_intr_handle_t);
@@ -153,6 +155,10 @@ struct ranges_new {
 	u_int32_t size;
 };
 
+extern int pegasos;
+struct ppc_bus_space marvell_io;
+bus_space_handle_t marvell_ioh;
+
 void
 mpcpcibrattach(struct device *parent, struct device *self, void *aux)
 {
@@ -244,48 +250,8 @@ mpcpcibrattach(struct device *parent, struct device *self, void *aux)
 		sc->sc_membus_space.bus_size = size;
 
 	}
-	addr_offset = 0;
-
-	/* XXX? */
-	lcp->config_type = 0;
-	addr_offset=0x00c00cf8;
-	data_offset=0x00e00cfc;
-#ifdef DEBUG_FIXUP
-	printf(" mem base %x sz %x io base %x sz %x\n config addr %x"
-	    " config data %x\n",
-	    sc->sc_membus_space.bus_base,
-	    sc->sc_membus_space.bus_size,
-	    sc->sc_iobus_space.bus_base,
-	    sc->sc_iobus_space.bus_size,
-	    addr_offset, data_offset);
-#endif
-
-	if ( bus_space_map(&(sc->sc_iobus_space), addr_offset,
-	    NBPG, 0, &lcp->ioh_cf8) != 0 )
-		panic("mpcpcibus: unable to map self");
-
-	if ( bus_space_map(&(sc->sc_iobus_space), data_offset,
-	    NBPG, 0, &lcp->ioh_cfc) != 0 )
-		panic("mpcpcibus: unable to map self");
 
 	of_node = ca->ca_node;
-
-	{
-		u_int32_t pci_iack_paddr;
-
-		if ((rangelen = OF_getprop(ca->ca_node,
-		    "8259-interrupt-acknowledge",
-		    &pci_iack_paddr,
-		    sizeof(pci_iack_paddr))) <= 0) {
-			printf( "getprop 8259-interrupt-acknowledge "
-			    "failed\n");
-		}  else {
-			bus_space_map(&(sc->sc_iobus_space), pci_iack_paddr,
-			    NBPG, 0, &(sc->pci_iack_ioh));
-		}
-	}
-
-
 	lcp->node = ca->ca_node;
 	lcp->lc_pc.pc_conf_v = lcp;
 	lcp->lc_pc.pc_attach_hook = mpc_attach_hook;
@@ -305,6 +271,91 @@ mpcpcibrattach(struct device *parent, struct device *self, void *aux)
 	lcp->lc_pc.pc_intr_establish = mpc_intr_establish;
 	lcp->lc_pc.pc_intr_disestablish = mpc_intr_disestablish;
 
+	addr_offset = 0;
+
+	if (pegasos == 2) {
+		marvell_io.bus_base = 0xf1000000;
+		marvell_io.bus_reverse = 1;
+		marvell_io.bus_io = 1;
+
+		/* PegII */
+		if (sc->sc_iobus_space.bus_base == 0xfe000000) {
+		addr_offset=0x00000c78;
+		data_offset=0x00000c7c;
+		} else if (sc->sc_iobus_space.bus_base == 0xf8000000) {
+			addr_offset=0x00000cf8;
+			data_offset=0x00000cfc;
+			lcp->lc_pc.pc_conf_read = peg2_conf_read;
+			lcp->lc_pc.pc_conf_write = peg2_conf_write;
+			bus_space_map (&(marvell_io), 0xF000, PAGE_SIZE, 0,
+			    &marvell_ioh);
+		}
+		if ( bus_space_map(&(marvell_io), addr_offset,
+		    PAGE_SIZE, 0, &lcp->ioh_cf8) != 0 )
+			panic("mpcpcibus: unable to map self");
+
+		if ( bus_space_map(&(marvell_io), data_offset,
+		    PAGE_SIZE, 0, &lcp->ioh_cfc) != 0 )
+			panic("mpcpcibus: unable to map self");
+
+		{
+			u_int32_t pci_iack_paddr;
+
+			if ((rangelen = OF_getprop(ca->ca_node,
+			    "8259-interrupt-acknowledge",
+			    &pci_iack_paddr,
+			    sizeof(pci_iack_paddr))) <= 0) {
+				printf( "getprop 8259-interrupt-acknowledge "
+				    "failed\n");
+			}  else {
+				/* Peg 2 XXX */
+				bus_space_map(&(marvell_io), pci_iack_paddr,
+				    NBPG, 0, &(sc->pci_iack_ioh));
+			}
+		}
+	} else {
+		/* PegI */
+		lcp->config_type = 0;
+		addr_offset=0x00c00cf8;
+		data_offset=0x00e00cfc;
+
+
+#ifdef DEBUG_FIXUP
+		printf(" mem base %x sz %x io base %x sz %x\n config addr %x"
+		    " config data %x\n",
+		    sc->sc_membus_space.bus_base,
+		    sc->sc_membus_space.bus_size,
+		    sc->sc_iobus_space.bus_base,
+		    sc->sc_iobus_space.bus_size,
+		    addr_offset, data_offset);
+#endif
+
+		if ( bus_space_map(&(sc->sc_iobus_space), addr_offset,
+		    NBPG, 0, &lcp->ioh_cf8) != 0 )
+			panic("mpcpcibus: unable to map self");
+
+		if ( bus_space_map(&(sc->sc_iobus_space), data_offset,
+		    NBPG, 0, &lcp->ioh_cfc) != 0 )
+			panic("mpcpcibus: unable to map self");
+
+		{
+			u_int32_t pci_iack_paddr;
+
+			if ((rangelen = OF_getprop(ca->ca_node,
+			    "8259-interrupt-acknowledge",
+			    &pci_iack_paddr,
+			    sizeof(pci_iack_paddr))) <= 0) {
+				printf( "getprop 8259-interrupt-acknowledge "
+				    "failed\n");
+			}  else {
+				bus_space_map(&(sc->sc_iobus_space),
+				    pci_iack_paddr, NBPG, 0,
+				    &(sc->pci_iack_ioh));
+			}
+		}
+	}
+
+
 	printf("\n");
 
 	/*
@@ -619,6 +670,121 @@ mpc_gen_config_reg(void *cpv, pcitag_t tag, int offset)
 	return reg;
 }
 
+int	marvell_data[16] = {
+	0x00000000,	/* 0: is passed on to the device (RO) */
+	0x00000000,	/* 4: is passed on to the device (RO) */
+	0x00000000,	/* 8: is passed on to the device (RO) */
+	0x00000000,	/* c: is passed on to the device (RO) */
+	0x00000000,	/* 10: faked 0 BAR */
+	0x00000000,	/* 14: faked 0 BAR */
+	0x00000000,	/* 18: faked 0 BAR */
+	0x00000000,	/* 1c: faked 0 BAR */
+	0x00000000,	/* 20: faked 0 BAR */
+	0x00000000,	/* 24: faked 0 BAR */
+	0x00000000,	/* 28: faked 0 CIS */
+	0x00000000,	/* 2c: faked 0 Subsystem */
+	0x00000000,	/* 30: faked 0 ROM */
+	0x00000000,	/* 34: faked 0 Res */
+	0x00000000,	/* 28: faked 0 Res */
+	0x00000109	/* 3c: faked 0 Lat/Gnt/pin/line */
+};
+
+pcireg_t
+peg2_conf_read(void *cpv, pcitag_t tag, int offset)
+{
+	struct pcibr_config *cp = cpv;
+	pcireg_t data;
+	u_int32_t reg;
+	int s;
+	int daddr = 0;
+	faultbuf env;
+	void *oldh;
+
+	if (offset & 3 || offset < 0 || offset >= 0x100)
+		return(~0);
+
+	reg = mpc_gen_config_reg(cpv, tag, offset);
+	/* if invalid tag, return -1 */
+	if (reg == 0xffffffff)
+		return(~0);
+
+	if (pegasos == 2 && tag == 0) {
+		if (offset >= 0x40)
+			return (~0);
+
+		if (offset >= 0x10) 
+			return marvell_data[offset / 4];
+
+		/* registers < 0x10 allow read */
+	}
+
+	if ((cp->config_type & 2) && (offset & 0x04))
+		daddr += 4;
+
+	s = ppc_intr_disable();
+
+	oldh = curpcb->pcb_onfault;
+	if (setfault(&env)) {
+		/* we faulted during the read? */
+		curpcb->pcb_onfault = oldh;
+		ppc_intr_enable(s);
+		return 0xffffffff;
+	}
+
+	bus_space_write_4(&marvell_io, marvell_ioh, 0x118, 0x00800000);
+	bus_space_write_4(cp->lc_iot, cp->ioh_cf8, 0, reg);
+	bus_space_read_4(cp->lc_iot, cp->ioh_cf8, 0); /* XXX */
+	data = bus_space_read_4(cp->lc_iot, cp->ioh_cfc, daddr);
+	bus_space_write_4(cp->lc_iot, cp->ioh_cf8, 0, 0); /* disable */
+	bus_space_read_4(cp->lc_iot, cp->ioh_cf8, 0); /* XXX */
+	bus_space_write_4(&marvell_io, marvell_ioh, 0x11c, 0x00800000);
+
+	curpcb->pcb_onfault = oldh;
+
+	ppc_intr_enable(s);
+	return(data);
+}
+void
+peg2_conf_write(void *cpv, pcitag_t tag, int offset, pcireg_t data)
+{
+	struct pcibr_config *cp = cpv;
+	u_int32_t reg;
+	int s;
+	int daddr = 0;
+
+	reg = mpc_gen_config_reg(cpv, tag, offset);
+
+	/* if invalid tag, return ??? */
+	if (reg == 0xffffffff)
+		return;
+
+	if (pegasos == 2 && tag == 0) {
+		switch (offset) {
+		case 0x3c:
+			marvell_data[offset / 4] = data;
+			return;
+		}
+
+		if (offset != 4)
+			return;
+	}
+
+	if ((cp->config_type & 2) && (offset & 0x04))
+		daddr += 4;
+
+	s = splhigh();
+
+	bus_space_write_4(&marvell_io, marvell_ioh, 0x118, 0x00800000);
+	bus_space_write_4(cp->lc_iot, cp->ioh_cf8, 0, reg);
+	bus_space_read_4(cp->lc_iot, cp->ioh_cf8, 0); /* XXX */
+	bus_space_write_4(cp->lc_iot, cp->ioh_cfc, daddr, data);
+	bus_space_write_4(cp->lc_iot, cp->ioh_cf8, 0, 0); /* disable */
+	bus_space_read_4(cp->lc_iot, cp->ioh_cf8, 0); /* XXX */
+	bus_space_write_4(&marvell_io, marvell_ioh, 0x11c, 0x00800000);
+
+	splx(s);
+}
+
 pcireg_t
 mpc_conf_read(void *cpv, pcitag_t tag, int offset)
 {
@@ -638,6 +804,16 @@ mpc_conf_read(void *cpv, pcitag_t tag, int offset)
 	if (reg == 0xffffffff)
 		return(~0);
 
+	if (pegasos == 2 && tag == 0) {
+		if (offset >= 0x40)
+			return (~0);
+
+		if (offset >= 0x10) 
+			return marvell_data[offset / 4];
+
+		/* registers < 0x10 allow read */
+	}
+
 	if ((cp->config_type & 2) && (offset & 0x04))
 		daddr += 4;
 
@@ -661,7 +837,6 @@ mpc_conf_read(void *cpv, pcitag_t tag, int offset)
 	splx(s);
 	return(data);
 }
-
 void
 mpc_conf_write(void *cpv, pcitag_t tag, int offset, pcireg_t data)
 {
@@ -676,6 +851,17 @@ mpc_conf_write(void *cpv, pcitag_t tag, int offset, pcireg_t data)
 	if (reg == 0xffffffff)
 		return;
 
+	if (pegasos == 2 && tag == 0) {
+		switch (offset) {
+		case 0x3c:
+			marvell_data[offset / 4] = data;
+			return;
+		}
+
+		if (offset != 4)
+			return;
+	}
+
 	if ((cp->config_type & 2) && (offset & 0x04))
 		daddr += 4;
 
diff --git a/sys/arch/pegasos/pegasos/cpu.c b/sys/arch/pegasos/pegasos/cpu.c
index 7b3f31f726d..26f1ae5f97c 100644
--- a/sys/arch/pegasos/pegasos/cpu.c
+++ b/sys/arch/pegasos/pegasos/cpu.c
@@ -1,4 +1,4 @@
-/*	$OpenBSD: cpu.c,v 1.2 2004/01/15 05:19:46 drahn Exp $ */
+/*	$OpenBSD: cpu.c,v 1.3 2004/02/04 20:07:18 drahn Exp $ */
 
 /*
  * Copyright (c) 1997 Per Fogelstrom
@@ -55,6 +55,7 @@
 #define MPC7410         0x800c
 #define MPC7450         0x8000
 #define MPC7455         0x8001
+#define MPC7454         0x8002
 
 /* only valid on 603(e,ev) and G3, G4 */
 #define HID0_DOZE	(1 << (31-8))
@@ -67,6 +68,51 @@
 #define HID0_FOLD	(1 << (31-28))
 #define HID0_BHT	(1 << (31-29))
 
+/* L2CR bit definitions */
+#define L2CR_L2E        0x80000000 /* 0: L2 enable */
+#define L2CR_L2PE       0x40000000 /* 1: L2 data parity enable */
+#define L2CR_L2SIZ      0x30000000 /* 2-3: L2 size */
+#define  L2SIZ_RESERVED         0x00000000
+#define  L2SIZ_256K             0x10000000
+#define  L2SIZ_512K             0x20000000
+#define  L2SIZ_1M       0x30000000
+#define L2CR_L2CLK      0x0e000000 /* 4-6: L2 clock ratio */
+#define  L2CLK_DIS              0x00000000 /* disable L2 clock */
+#define  L2CLK_10               0x02000000 /* core clock / 1   */
+#define  L2CLK_15               0x04000000 /*            / 1.5 */
+#define  L2CLK_20               0x08000000 /*            / 2   */
+#define  L2CLK_25               0x0a000000 /*            / 2.5 */
+#define  L2CLK_30               0x0c000000 /*            / 3   */
+#define L2CR_L2RAM      0x01800000 /* 7-8: L2 RAM type */
+#define  L2RAM_FLOWTHRU_BURST   0x00000000
+#define  L2RAM_PIPELINE_BURST   0x01000000
+#define  L2RAM_PIPELINE_LATE    0x01800000
+#define L2CR_L2DO       0x00400000 /* 9: L2 data-only.
+                                      Setting this bit disables instruction
+                                      caching. */
+#define L2CR_L2I        0x00200000 /* 10: L2 global invalidate. */
+#define L2CR_L2CTL      0x00100000 /* 11: L2 RAM control (ZZ enable).
+                                      Enables automatic operation of the
+                                      L2ZZ (low-power mode) signal. */
+#define L2CR_L2WT       0x00080000 /* 12: L2 write-through. */
+#define L2CR_L2TS       0x00040000 /* 13: L2 test support. */
+#define L2CR_L2OH       0x00030000 /* 14-15: L2 output hold. */
+#define L2CR_L2SL       0x00008000 /* 16: L2 DLL slow. */
+#define L2CR_L2DF       0x00004000 /* 17: L2 differential clock. */
+#define L2CR_L2BYP      0x00002000 /* 18: L2 DLL bypass. */
+#define L2CR_L2IP       0x00000001 /* 31: L2 global invalidate in progress
+				       (read only). */
+
+/* L3CR bit definitions */
+#define   L3CR_L3E                0x80000000 /*  0: L3 enable */
+#define   L3CR_L3SIZ              0x10000000 /*  3: L3 size (0=1MB, 1=2MB) */
+
+#ifdef L2CR_CONFIG
+u_int l2cr_config = L2CR_CONFIG;
+#else
+u_int l2cr_config = 0;
+#endif
+
 char cpu_model[80];
 char machine[] = MACHINE;	/* cpu architecture */
 
@@ -157,6 +203,9 @@ cpuattach(struct device *parent, struct device *dev, void *aux)
 		 else
 			snprintf(cpu_model, sizeof(cpu_model), "7451");
 		break;
+	case MPC7454:
+		snprintf(cpu_model, sizeof(cpu_model), "7454");
+		break;
 	case MPC7455:
 		snprintf(cpu_model, sizeof(cpu_model), "7455");
 		break;
@@ -209,6 +258,7 @@ cpuattach(struct device *parent, struct device *dev, void *aux)
 		hid0 |= HID0_DOZE | HID0_DPM;
 		break;
 	case MPC7450:
+	case MPC7454:
 	case MPC7455:
 		/* select NAP mode */
 		hid0 &= ~(HID0_DOZE | HID0_SLEEP);
@@ -225,7 +275,22 @@ cpuattach(struct device *parent, struct device *dev, void *aux)
 
 	/* if processor is G3 or G4, configure l2 cache */
 	if ( (cpu == MPC750) || (cpu == MPC7400) || (cpu == IBM750FX)
-	    || (cpu == MPC7410) || (cpu == MPC7450) || (cpu == MPC7455)) {
+	    || (cpu == MPC7410) || (cpu == MPC7450) || (cpu == MPC7454)
+	    || (cpu == MPC7455)) {
+		/* Pegasos doesn't configure L2 in OF, 
+		 * should enable it's size based on OF values, not
+		 * this G3/G4 switch
+		 */
+		switch (cpu) {
+		case MPC750:
+			l2cr_config = L2CR_L2E|L2SIZ_512K;
+			break;
+		case MPC7454:
+			l2cr_config = L2CR_L2E|L2SIZ_256K;
+			break;
+		default:
+			;
+		}
 		config_l2cr(cpu);
 	}
 	printf("\n");
@@ -233,53 +298,6 @@ cpuattach(struct device *parent, struct device *dev, void *aux)
 
 }
 
-/* L2CR bit definitions */
-#define L2CR_L2E        0x80000000 /* 0: L2 enable */
-#define L2CR_L2PE       0x40000000 /* 1: L2 data parity enable */
-#define L2CR_L2SIZ      0x30000000 /* 2-3: L2 size */
-#define  L2SIZ_RESERVED         0x00000000
-#define  L2SIZ_256K             0x10000000
-#define  L2SIZ_512K             0x20000000
-#define  L2SIZ_1M       0x30000000
-#define L2CR_L2CLK      0x0e000000 /* 4-6: L2 clock ratio */
-#define  L2CLK_DIS              0x00000000 /* disable L2 clock */
-#define  L2CLK_10               0x02000000 /* core clock / 1   */
-#define  L2CLK_15               0x04000000 /*            / 1.5 */
-#define  L2CLK_20               0x08000000 /*            / 2   */
-#define  L2CLK_25               0x0a000000 /*            / 2.5 */
-#define  L2CLK_30               0x0c000000 /*            / 3   */
-#define L2CR_L2RAM      0x01800000 /* 7-8: L2 RAM type */
-#define  L2RAM_FLOWTHRU_BURST   0x00000000
-#define  L2RAM_PIPELINE_BURST   0x01000000
-#define  L2RAM_PIPELINE_LATE    0x01800000
-#define L2CR_L2DO       0x00400000 /* 9: L2 data-only.
-                                      Setting this bit disables instruction
-                                      caching. */
-#define L2CR_L2I        0x00200000 /* 10: L2 global invalidate. */
-#define L2CR_L2CTL      0x00100000 /* 11: L2 RAM control (ZZ enable).
-                                      Enables automatic operation of the
-                                      L2ZZ (low-power mode) signal. */
-#define L2CR_L2WT       0x00080000 /* 12: L2 write-through. */
-#define L2CR_L2TS       0x00040000 /* 13: L2 test support. */
-#define L2CR_L2OH       0x00030000 /* 14-15: L2 output hold. */
-#define L2CR_L2SL       0x00008000 /* 16: L2 DLL slow. */
-#define L2CR_L2DF       0x00004000 /* 17: L2 differential clock. */
-#define L2CR_L2BYP      0x00002000 /* 18: L2 DLL bypass. */
-#define L2CR_L2IP       0x00000001 /* 31: L2 global invalidate in progress
-				       (read only). */
-#ifndef L2CR_CONFIG
-#define L2CR_CONFIG L2CR_L2E|L2SIZ_512K
-#endif
-
-#ifdef L2CR_CONFIG
-u_int l2cr_config = L2CR_CONFIG;
-#else
-u_int l2cr_config = 0;
-#endif
-
-/* L3CR bit definitions */
-#define   L3CR_L3E                0x80000000 /*  0: L3 enable */
-#define   L3CR_L3SIZ              0x10000000 /*  3: L3 size (0=1MB, 1=2MB) */
 
 void
 config_l2cr(int cpu)
@@ -314,7 +332,7 @@ config_l2cr(int cpu)
 	}
 
 	if (l2cr & L2CR_L2E) {
-		if (cpu == MPC7450 || cpu == MPC7455) {
+		if (cpu == MPC7450 || cpu == MPC7454 || cpu == MPC7455) {
 			u_int l3cr;
 
 			printf(": 256KB L2 cache");
diff --git a/sys/arch/pegasos/pegasos/dma.c b/sys/arch/pegasos/pegasos/dma.c
index b607f9ca288..22fc5642fef 100644
--- a/sys/arch/pegasos/pegasos/dma.c
+++ b/sys/arch/pegasos/pegasos/dma.c
@@ -1,4 +1,4 @@
-/*	$OpenBSD: dma.c,v 1.2 2003/12/20 22:40:27 miod Exp $	*/
+/*	$OpenBSD: dma.c,v 1.3 2004/02/04 20:07:18 drahn Exp $	*/
 /*	$NetBSD: machdep.c,v 1.214 1996/11/10 03:16:17 thorpej Exp $	*/
 
 /*-
@@ -388,14 +388,15 @@ bus_size_t len, int op)
 	vaddr_t p;
 	int l;
 	int i;
+	extern int pegasos; /* XXX */
 
 	/* 
-	 * pegasos needs to sync before dma from memory to disk drives
-	 * snooping broken?
+	 * pegasos 1 (april1) needs to sync before dma from memory to
+	 * disk drives snooping broken?
 	 */
 
 	/* only flush before DMA to drive */
-	if ((op & BUS_DMASYNC_PREWRITE) == 0)
+	if ((pegasos != 0) || (op & BUS_DMASYNC_PREWRITE) == 0)
 		return;
 
 	for (i = 0; i < map->dm_nsegs; i++) {
diff --git a/sys/arch/pegasos/pegasos/machdep.c b/sys/arch/pegasos/pegasos/machdep.c
index fa617b05da4..cbc638e032f 100644
--- a/sys/arch/pegasos/pegasos/machdep.c
+++ b/sys/arch/pegasos/pegasos/machdep.c
@@ -1,4 +1,4 @@
-/*	$OpenBSD: machdep.c,v 1.4 2004/01/15 03:26:36 drahn Exp $	*/
+/*	$OpenBSD: machdep.c,v 1.5 2004/02/04 20:07:18 drahn Exp $	*/
 /*	$NetBSD: machdep.c,v 1.4 1996/10/16 19:33:11 ws Exp $	*/
 
 /*
@@ -183,6 +183,8 @@ extern int OF_stdout;
 /* XXX, called from asm */
 void initppc(u_int startkernel, u_int endkernel, char *args);
 
+int pegasos = 0;
+
 void
 initppc(startkernel, endkernel, args)
 	u_int startkernel, endkernel;
@@ -449,6 +451,35 @@ initppc(startkernel, endkernel, args)
 		printf("kernel does not support -c; continuing..\n");
 #endif
 	}
+
+	{
+		char model[32];
+		int node, len;
+
+		node = OF_peer(0);
+		len = OF_getprop(node, "model", model,  sizeof(model));
+		model[len] = 0;
+
+		/*
+		 * Different versions of Pegasos:
+		 * Pegasos I, no April (not supported...)
+		 * Pegasos I, April I		0
+		 * Pegasos I, April II		1 (?)
+		 * Pegasos II			2
+		 *
+		 * However, OF does not distingush between
+		 * April I and April II therefore we must assume it
+		 * has the April I snoop bug...
+		 */
+
+		if (strcmp(model, "Pegasos2") == 0) {
+			pegasos = 2;
+		} else {
+			pegasos = 0; /* Assume PegI April I */
+		}
+
+
+	}
 	/*
 	 * Replace with real console.
 	 */
diff --git a/sys/arch/pegasos/pegasos/mainbus.c b/sys/arch/pegasos/pegasos/mainbus.c
index c85d73490b9..00c9c19e5c3 100644
--- a/sys/arch/pegasos/pegasos/mainbus.c
+++ b/sys/arch/pegasos/pegasos/mainbus.c
@@ -1,4 +1,4 @@
-/*	$OpenBSD: mainbus.c,v 1.1 2003/10/31 03:54:33 drahn Exp $	*/
+/*	$OpenBSD: mainbus.c,v 1.2 2004/02/04 20:07:18 drahn Exp $	*/
 
 /*
  * Copyright (c) 1994, 1995 Carnegie-Mellon University.
@@ -99,14 +99,6 @@ mbattach(struct device *parent, struct device *self, void *aux)
 		config_found(self, &nca, mbprint);
 	}
 
-	/* The following machines have an ISA bus */
-	/* Do ISA first so the interrupt controller is set up! */
-	if (system_type == POWER4e) {
-		nca.ca_name = "isabr";
-		nca.ca_bus = &sc->sc_bus;
-		config_found(self, &nca, mbprint);
-	}
-
 	/* The following machines have a PCI bus */
 	if (system_type == APPL) {
 		char name[32];
diff --git a/sys/arch/pegasos/pegasos/ofw_machdep.c b/sys/arch/pegasos/pegasos/ofw_machdep.c
index dd7f3afd215..4ae397d2f6b 100644
--- a/sys/arch/pegasos/pegasos/ofw_machdep.c
+++ b/sys/arch/pegasos/pegasos/ofw_machdep.c
@@ -1,4 +1,4 @@
- /*	$OpenBSD: ofw_machdep.c,v 1.1 2003/10/31 03:54:33 drahn Exp $	*/
+ /*	$OpenBSD: ofw_machdep.c,v 1.2 2004/02/04 20:07:18 drahn Exp $	*/
 /*	$NetBSD: ofw_machdep.c,v 1.1 1996/09/30 16:34:50 ws Exp $	*/
 
 /*
@@ -460,44 +460,98 @@ struct usb_kbd_ihandles {
 u_int32_t ppc_console_addr;
 struct ppc_bus_space *ppc_isa_iobus_space;
 struct ppc_bus_space *ppc_isa_membus_space;
+struct ppc_bus_space *ppc_display_isa_iobus_space;
+struct ppc_bus_space *ppc_display_isa_membus_space;
+struct ppc_bus_space ppc_agp_isa_iobus_store;
+struct ppc_bus_space ppc_agp_isa_membus_store;
+
+extern int comdefaultrate;
+extern int pegasos;
+int ppc_agpconsole;
 
 void
 ofwconprobe()
 {
 	char type[32];
 	int stdout_node;
+	char path[128];
+	int len;
+	char name[32];
+	int display;
+
+	ppc_agpconsole = 0;
 
 	stdout_node = OF_instance_to_package(OF_stdout);
 
+	ppc_isa_iobus_space = &ppc_isa_io;
+	ppc_isa_iobus_space->bus_base = 0xfe000000;
+	ppc_isa_iobus_space->bus_reverse = 1;
+	ppc_isa_iobus_space->bus_io = 1;
+	ppc_isa_iobus_space->bus_size = 0x01000000;
+	ppc_isa_membus_space = &ppc_isa_mem;
+	ppc_isa_membus_space->bus_base = 0xfd000000;
+	ppc_isa_membus_space->bus_size = 0x01000000;
+	ppc_isa_membus_space->bus_reverse = 1;
+
+
 	/* handle different types of console */
 
 	bzero(type, sizeof(type));
 	if (OF_getprop(stdout_node,  "device_type", type, sizeof(type)) == -1) {
 		return; /* XXX */
 	}
-	{
-		/*
-		 * Initialize the early bus_space values to
-		 * correct values for Pegasos I
-		 */
-		ppc_isa_iobus_space = &ppc_isa_io;
-		ppc_isa_iobus_space->bus_base = 0xfe000000;
-		ppc_isa_iobus_space->bus_reverse = 1;
-		ppc_isa_iobus_space->bus_io = 1;
-		ppc_isa_iobus_space->bus_size = 0x01000000;
-		ppc_isa_membus_space = &ppc_isa_mem;
-		ppc_isa_membus_space->bus_base = 0xfd000000;
-		ppc_isa_membus_space->bus_size = 0x01000000;
-		ppc_isa_membus_space->bus_reverse = 1;
+
+	len = OF_package_to_path(stdout_node, path, sizeof path);
+	path[len] = 0;
+	printf("console path [%s] type [%s]\n", path, type);
+
+	if (strcmp(path, "/failsafe") == 0) {
+		ppc_console_addr = 0x2f8;
+
+		/* failsafe serial console, at firmware dbg speed */
+		comdefaultrate = 115200;
+		return;
 	}
 	if (strcmp(type, "serial") == 0) {
 		/* XXX */
-		extern int     comdefaultrate;
 		ppc_console_addr = 0x2f8;
 		comdefaultrate = 9600;
+		return;
+	}
+
+	len = OF_getprop(stdout_node, "name", name, 20);
+	name[len] = 0;   
+	printf("console out [%s]\n", name);
+
+	display = OF_finddevice("/display");
+	if (display != -1 && display != 0) {
+		len = OF_package_to_path(display, path, sizeof path);
+		path[len] = 0;
+		printf("display path [%s]\n", path);
+		if (strncmp(path, "/pci@C0000000", 12) == 0)
+			ppc_agpconsole = 1;
+	}
+
+	/*
+	 * Initialize the early bus_space values to
+	 * correct values for Pegasos I
+	 */
+	if (pegasos == 2 && ppc_agpconsole) {
+		ppc_display_isa_iobus_space = &ppc_agp_isa_iobus_store;
+		ppc_display_isa_membus_space = &ppc_agp_isa_membus_store;
+
+		ppc_display_isa_iobus_space->bus_base = 0xf8000000;
+		ppc_display_isa_iobus_space->bus_reverse = 1;
+		ppc_display_isa_iobus_space->bus_io = 1;
+		ppc_display_isa_iobus_space->bus_size = 0x01000000;
+		ppc_display_isa_membus_space->bus_base = 0xf9000000;
+		ppc_display_isa_membus_space->bus_size = 0x01000000;
+		ppc_display_isa_membus_space->bus_reverse = 1;
+	} else {
+		ppc_display_isa_iobus_space = &ppc_isa_io;
+		ppc_display_isa_membus_space = &ppc_isa_mem;
 	}
 	if (strcmp(type, "bootconsole") == 0) {
-		extern int     comdefaultrate;
 		/* pegasos unknown console, */
 		/* which is set up already */
 
diff --git a/sys/arch/pegasos/pegasos/wscons_machdep.c b/sys/arch/pegasos/pegasos/wscons_machdep.c
index 4af0f522b4b..04e57aa11d6 100644
--- a/sys/arch/pegasos/pegasos/wscons_machdep.c
+++ b/sys/arch/pegasos/pegasos/wscons_machdep.c
@@ -1,4 +1,4 @@
-/*	$OpenBSD: wscons_machdep.c,v 1.1 2003/10/31 03:54:33 drahn Exp $ */
+/*	$OpenBSD: wscons_machdep.c,v 1.2 2004/02/04 20:07:18 drahn Exp $ */
 
 /*
  * Copyright (c) 2001 Aaron Campbell
@@ -100,14 +100,8 @@ wscninit(struct consdev *cp)
 
 
 #if (NVGA_PCI > 0)
-	/* NOTE!!!!
-	 *
-	 * ic/vga expects to be able to access vga registers
-	 * using pci  iot/ioh memt/memh, however that is not possible
-	 * on Pegasos, ISA handles must be passed.
-	 */
-	if (!vga_pci_cnattach(MD_ISA_IOT, MD_ISA_MEMT,
-	    NULL, 1, 0, 0))
+	if (!vga_pci_cnattach(MD_DISPLAY_ISA_IOT, MD_DISPLAY_ISA_MEMT,
+	    NULL, 1, 0, 0));
 #endif
 #if (NPCKBC > 0)
 	if (!pckbc_cnattach(MD_ISA_IOT, IO_KBD, KBCMDP, PCKBC_KBD_SLOT))