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authorPatrick Wildt <patrick@cvs.openbsd.org>2013-10-29 12:10:03 +0000
committerPatrick Wildt <patrick@cvs.openbsd.org>2013-10-29 12:10:03 +0000
commitad296e9426bc87d16a6009374fc465f9309ded7c (patch)
treec817c884999ab6150153cb930d87d5e3127d0293 /sys/arch
parente496b0ffd02d2c0b3d2ece1b090c4d8290cd3236 (diff)
The cache mask for ARMv7 is a little bit different from the one inited by
the generic function. While there, also set the cache bits manually. ok aalm@
Diffstat (limited to 'sys/arch')
-rw-r--r--sys/arch/arm/arm/pmap7.c15
1 files changed, 14 insertions, 1 deletions
diff --git a/sys/arch/arm/arm/pmap7.c b/sys/arch/arm/arm/pmap7.c
index b3062e32ee2..679fc17dc4e 100644
--- a/sys/arch/arm/arm/pmap7.c
+++ b/sys/arch/arm/arm/pmap7.c
@@ -1,4 +1,4 @@
-/* $OpenBSD: pmap7.c,v 1.10 2013/10/22 15:18:06 patrick Exp $ */
+/* $OpenBSD: pmap7.c,v 1.11 2013/10/29 12:10:02 patrick Exp $ */
/* $NetBSD: pmap.c,v 1.147 2004/01/18 13:03:50 scw Exp $ */
/*
@@ -3521,6 +3521,19 @@ pmap_pte_init_armv7(void)
*/
pmap_pte_init_generic();
+ /* write-allocate should be tested */
+ pte_l1_s_cache_mode = L1_S_C|L1_S_B;
+ pte_l2_l_cache_mode = L2_C|L2_B;
+ pte_l2_s_cache_mode = L2_C|L2_B;
+
+ pte_l1_s_cache_mode_pt = L1_S_C;
+ pte_l2_l_cache_mode_pt = L2_C;
+ pte_l2_s_cache_mode_pt = L2_C;
+
+ pte_l1_s_cache_mask = L1_S_CACHE_MASK_v7;
+ pte_l2_l_cache_mask = L2_L_CACHE_MASK_v7;
+ pte_l2_s_cache_mask = L2_S_CACHE_MASK_v7;
+
pte_l1_s_coherent = L1_S_COHERENT_v7;
pte_l2_l_coherent = L2_L_COHERENT_v7;
pte_l2_s_coherent = L2_S_COHERENT_v7;