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authorJonathan Gray <jsg@cvs.openbsd.org>2020-05-27 05:08:55 +0000
committerJonathan Gray <jsg@cvs.openbsd.org>2020-05-27 05:08:55 +0000
commitc0dcaa8320c05398821426c561cf380faa6b9f2e (patch)
tree88bdcdb4e06321c5c7ceba6155901d8020da1ed6 /sys/arch
parentc0812dafa60c5dca2e09569275910da4498ccc60 (diff)
don't limit clflush to Intel CPUs
discussed with deraadt@
Diffstat (limited to 'sys/arch')
-rw-r--r--sys/arch/amd64/amd64/identcpu.c7
-rw-r--r--sys/arch/i386/i386/machdep.c22
2 files changed, 16 insertions, 13 deletions
diff --git a/sys/arch/amd64/amd64/identcpu.c b/sys/arch/amd64/amd64/identcpu.c
index 000886abb47..de4b7c3050b 100644
--- a/sys/arch/amd64/amd64/identcpu.c
+++ b/sys/arch/amd64/amd64/identcpu.c
@@ -1,4 +1,4 @@
-/* $OpenBSD: identcpu.c,v 1.114 2020/03/17 03:09:04 dlg Exp $ */
+/* $OpenBSD: identcpu.c,v 1.115 2020/05/27 05:08:53 jsg Exp $ */
/* $NetBSD: identcpu.c,v 1.1 2003/04/26 18:39:28 fvdl Exp $ */
/*
@@ -716,8 +716,8 @@ identifycpu(struct cpu_info *ci)
if (ci->ci_feature_sefflags_ebx & SEFF0EBX_SMAP)
replacesmap();
}
-#ifndef SMALL_KERNEL
- if (!strncmp(mycpu_model, "Intel", 5)) {
+
+ if (ci->ci_feature_flags & CPUID_CFLUSH) {
u_int32_t cflushsz;
CPUID(0x01, dummy, cflushsz, dummy, dummy);
@@ -725,6 +725,7 @@ identifycpu(struct cpu_info *ci)
ci->ci_cflushsz = ((cflushsz >> 8) & 0xff) * 8;
}
+#ifndef SMALL_KERNEL
if (CPU_IS_PRIMARY(ci) && (ci->ci_feature_tpmflags & TPM_SENSOR)) {
strlcpy(ci->ci_sensordev.xname, ci->ci_dev->dv_xname,
sizeof(ci->ci_sensordev.xname));
diff --git a/sys/arch/i386/i386/machdep.c b/sys/arch/i386/i386/machdep.c
index a6f059d7802..5c7fdb19c0b 100644
--- a/sys/arch/i386/i386/machdep.c
+++ b/sys/arch/i386/i386/machdep.c
@@ -1,4 +1,4 @@
-/* $OpenBSD: machdep.c,v 1.633 2020/05/16 14:44:44 kettenis Exp $ */
+/* $OpenBSD: machdep.c,v 1.634 2020/05/27 05:08:54 jsg Exp $ */
/* $NetBSD: machdep.c,v 1.214 1996/11/10 03:16:17 thorpej Exp $ */
/*-
@@ -1847,6 +1847,17 @@ identifycpu(struct cpu_info *ci)
}
}
+ if (ci->ci_feature_flags & CPUID_CFLUSH) {
+ u_int regs[4];
+
+ /* to get the cacheline size you must do cpuid
+ * with eax 0x01
+ */
+
+ cpuid(0x01, regs);
+ ci->ci_cflushsz = ((regs[1] >> 8) & 0xff) * 8;
+ }
+
if (vendor == CPUVENDOR_INTEL) {
u_int regs[4];
/*
@@ -1860,15 +1871,6 @@ identifycpu(struct cpu_info *ci)
if (ci->ci_family == 6 && ci->ci_model < 15)
ci->ci_feature_flags &= ~CPUID_PAT;
- if (ci->ci_feature_flags & CPUID_CFLUSH) {
- /* to get the cacheline size you must do cpuid
- * with eax 0x01
- */
-
- cpuid(0x01, regs);
- ci->ci_cflushsz = ((regs[1] >> 8) & 0xff) * 8;
- }
-
if (cpuid_level >= 0x1) {
cpuid(0x80000000, regs);
if (regs[0] >= 0x80000006)