Change wdc_reset_channel() to take a `no wait' argument. Pass in turn this

argument to wdcreset(), to have it skip waiting until active channels see
their BUSY bit clear in the status register.

Use this feature in the resume path, during the first reset operation. The
first reset is supposed to only wake up the controller, and the disks don't
come back until the second reset is issued, therefore waiting for them to
report themselves as ready after the first reset, but before the second, is
moot - and as a matter of fact some controllers, such as the AMD 754 and
clones/offspring (e.g. Geode) keep the BUSY bit asserted after the first
reset.

Last, but not least, make sure wd@ata invokes wd_get_params() again before
returning from the resume code, as we will still be using polled transfers
for a short while.

This causes the Lemote Yeelong to resume within less than one second, instead
of the lousy 30 seconds wait between the two resets; and the wd_get_params()
voodoo prevents it from getting spurious ide interrupts afterwards.

wd_get_params() magic from dlg; rest of the work by yours truly after enough
prodding by dlg@ and pirofti@, among others. ok deraadt@ dlg@

1 files changed, 2 insertions, 2 deletions

diff --git a/sys/dev/ata/atavar.h b/sys/dev/ata/atavar.h
index 8214bc07358..9a57392b8ac 100644
--- a/sys/dev/ata/atavar.h
+++ b/sys/dev/ata/atavar.h
@@ -1,4 +1,4 @@
-/*	$OpenBSD: atavar.h,v 1.19 2010/07/23 07:47:13 jsg Exp $	*/
+/*	$OpenBSD: atavar.h,v 1.20 2011/04/15 20:53:28 miod Exp $	*/
 /*	$NetBSD: atavar.h,v 1.13 1999/03/10 13:11:43 bouyer Exp $	*/
 
 /*
@@ -164,7 +164,7 @@ void wdc_probe_caps(struct ata_drive_datas*, struct ataparams *);
 void wdc_print_caps(struct ata_drive_datas*);
 int  wdc_downgrade_mode(struct ata_drive_datas*);
 
-void wdc_reset_channel(struct ata_drive_datas *);
+void wdc_reset_channel(struct ata_drive_datas *, int);
 
 int wdc_ata_addref(struct ata_drive_datas *);
 void wdc_ata_delref(struct ata_drive_datas *);