Add SPI clocks for other 64-bit Rockchip SoCs.

ok jsg@, deraadt@

1 files changed, 66 insertions, 1 deletions

diff --git a/sys/dev/fdt/rkclock.c b/sys/dev/fdt/rkclock.c
index 653c164dca8..e7ee863951c 100644
--- a/sys/dev/fdt/rkclock.c
+++ b/sys/dev/fdt/rkclock.c
@@ -1,4 +1,4 @@
-/*	$OpenBSD: rkclock.c,v 1.86 2024/03/02 19:48:13 kettenis Exp $	*/
+/*	$OpenBSD: rkclock.c,v 1.87 2024/03/06 14:55:22 kettenis Exp $	*/
 /*
  * Copyright (c) 2017, 2018 Mark Kettenis <kettenis@openbsd.org>
  *
@@ -1044,6 +1044,21 @@ const struct rkclock rk3308_clocks[] = {
 		{ RK3308_PLL_DPLL, RK3308_PLL_VPLL0, RK3308_XIN24M }
 	},
 	{
+		RK3308_CLK_SPI0, RK3308_CRU_CLKSEL_CON(30),
+		SEL(15, 14), DIV(6, 0),
+		{ RK3308_PLL_DPLL, RK3308_PLL_VPLL0, RK3308_XIN24M }
+	},
+	{
+		RK3308_CLK_SPI1, RK3308_CRU_CLKSEL_CON(31),
+		SEL(15, 14), DIV(6, 0),
+		{ RK3308_PLL_DPLL, RK3308_PLL_VPLL0, RK3308_XIN24M }
+	},
+	{
+		RK3308_CLK_SPI2, RK3308_CRU_CLKSEL_CON(32),
+		SEL(15, 14), DIV(6, 0),
+		{ RK3308_PLL_DPLL, RK3308_PLL_VPLL0, RK3308_XIN24M }
+	},
+	{
 		RK3308_CLK_TSADC, RK3308_CRU_CLKSEL_CON(33),
 		0, DIV(10, 0),
 		{ RK3308_XIN24M }
@@ -1532,6 +1547,11 @@ const struct rkclock rk3328_clocks[] = {
 		{ RK3328_PLL_CPLL, RK3328_PLL_GPLL, RK3328_XIN24M }
 	},
 	{
+		RK3328_CLK_SPI, RK3328_CRU_CLKSEL_CON(24),
+		SEL(7, 7), DIV(6, 0),
+		{ RK3328_PLL_CPLL, RK3328_PLL_GPLL }
+	},
+	{
 		RK3328_CLK_SDMMC, RK3328_CRU_CLKSEL_CON(30),
 		SEL(9, 8), DIV(7, 0),
 		{ RK3328_PLL_CPLL, RK3328_PLL_GPLL, RK3328_XIN24M,
@@ -2257,6 +2277,31 @@ const struct rkclock rk3399_clocks[] = {
 		{ RK3399_PLL_CPLL, RK3399_PLL_GPLL }
 	},
 	{
+		RK3399_CLK_SPI0, RK3399_CRU_CLKSEL_CON(59),
+		SEL(7, 7), DIV(6, 0),
+		{ RK3399_PLL_CPLL, RK3399_PLL_GPLL }
+	},
+	{
+		RK3399_CLK_SPI1, RK3399_CRU_CLKSEL_CON(59),
+		SEL(15, 15), DIV(14, 8),
+		{ RK3399_PLL_CPLL, RK3399_PLL_GPLL }
+	},
+	{
+		RK3399_CLK_SPI2, RK3399_CRU_CLKSEL_CON(60),
+		SEL(7, 7), DIV(6, 0),
+		{ RK3399_PLL_CPLL, RK3399_PLL_GPLL }
+	},
+	{
+		RK3399_CLK_SPI4, RK3399_CRU_CLKSEL_CON(60),
+		SEL(15, 15), DIV(14, 8),
+		{ RK3399_PLL_CPLL, RK3399_PLL_GPLL }
+	},
+	{
+		RK3399_CLK_SPI5, RK3399_CRU_CLKSEL_CON(58),
+		SEL(15, 15), DIV(14, 8),
+		{ RK3399_PLL_CPLL, RK3399_PLL_GPLL }
+	},
+	{
 		RK3399_CLK_SDMMC, RK3399_CRU_CLKSEL_CON(16),
 		SEL(10, 8), DIV(6, 0),
 		{ RK3399_PLL_CPLL, RK3399_PLL_GPLL, RK3399_PLL_NPLL,
@@ -3285,6 +3330,26 @@ const struct rkclock rk3568_clocks[] = {
 		{ RK3568_CLK_I2C }
 	},
 	{
+		RK3568_CLK_SPI0, RK3568_CRU_CLKSEL_CON(72),
+		SEL(1, 0), 0,
+		{ RK3568_GPLL_200M, RK3568_XIN24M, RK3568_CPLL_100M }
+	},
+	{
+		RK3568_CLK_SPI1, RK3568_CRU_CLKSEL_CON(72),
+		SEL(3, 2), 0,
+		{ RK3568_GPLL_200M, RK3568_XIN24M, RK3568_CPLL_100M }
+	},
+	{
+		RK3568_CLK_SPI2, RK3568_CRU_CLKSEL_CON(72),
+		SEL(5, 4), 0,
+		{ RK3568_GPLL_200M, RK3568_XIN24M, RK3568_CPLL_100M }
+	},
+	{
+		RK3568_CLK_SPI3, RK3568_CRU_CLKSEL_CON(72),
+		SEL(7, 6), 0,
+		{ RK3568_GPLL_200M, RK3568_XIN24M, RK3568_CPLL_100M }
+	},
+	{
 		RK3568_SCLK_GMAC0, RK3568_CRU_CLKSEL_CON(31),
 		SEL(2, 2), 0,
 		{ RK3568_CLK_MAC0_2TOP, RK3568_GMAC0_CLKIN }