diff options
| author | Thorsten Lockert <tholo@cvs.openbsd.org> | 2001-07-27 15:30:43 +0000 |
|---|---|---|
| committer | Thorsten Lockert <tholo@cvs.openbsd.org> | 2001-07-27 15:30:43 +0000 |
| commit | 94e300c7c1502fce5abee5638ced501881fa0d9c (patch) | |
| tree | 6cd259576e968fdd5606f4251c1ad321fce54c45 /sys/dev/ic/am7990.c | |
| parent | cd5540251c4d2dfb8583e9b9246c29f7c8ff5a4e (diff) | |
Change how interrupts are acknowledged -- this is how the specification say
they should be acknowledged, and makes things work under VMware without the
timeout problems. miod@ ok
Diffstat (limited to 'sys/dev/ic/am7990.c')
| -rw-r--r-- | sys/dev/ic/am7990.c | 17 |
1 files changed, 6 insertions, 11 deletions
diff --git a/sys/dev/ic/am7990.c b/sys/dev/ic/am7990.c index 85a4a579819..6633700cf5f 100644 --- a/sys/dev/ic/am7990.c +++ b/sys/dev/ic/am7990.c @@ -1,4 +1,4 @@ -/* $OpenBSD: am7990.c,v 1.26 2001/06/27 06:34:39 kjc Exp $ */ +/* $OpenBSD: am7990.c,v 1.27 2001/07/27 15:30:42 tholo Exp $ */ /* $NetBSD: am7990.c,v 1.22 1996/10/13 01:37:19 christos Exp $ */ /*- @@ -674,19 +674,14 @@ am7990_intr(arg) if ((isr & LE_C0_INTR) == 0) return (0); -#ifdef __vax__ /* - * DEC needs this write order to the registers, don't know - * the results on other arch's. Ragge 991029 + * After receiving an interrupt, we need to toggle the interrupt + * enable bit in order to keep receiving them (some chips works + * without this, some do not) */ - isr &= ~LE_C0_INEA; - (*sc->sc_wrcsr)(sc, LE_CSR0, isr); + (*sc->sc_wrcsr)(sc, LE_CSR0, isr & ~LE_C0_INEA); (*sc->sc_wrcsr)(sc, LE_CSR0, LE_C0_INEA); -#else - (*sc->sc_wrcsr)(sc, LE_CSR0, - isr & (LE_C0_INEA | LE_C0_BABL | LE_C0_CERR | LE_C0_MISS | LE_C0_MERR | - LE_C0_RINT | LE_C0_TINT | LE_C0_IDON)); -#endif + if (isr & LE_C0_ERR) { if (isr & LE_C0_BABL) { #ifdef LEDEBUG |