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authorFederico G. Schwindt <fgsch@cvs.openbsd.org>1998-09-22 06:41:14 +0000
committerFederico G. Schwindt <fgsch@cvs.openbsd.org>1998-09-22 06:41:14 +0000
commitb5409cddfc0b0492cb65d50f3bf783cfae00c3b1 (patch)
tree0505c87d8117afa72ce2a35711d28b5525d182ca /sys/dev/ic/dp8390reg.h
parent1570dd0e22fd84039cf86fc9d726df05ef399077 (diff)
New DS8390/WD83C690 device driver used by ec, ne and we from NetBSD.
Diffstat (limited to 'sys/dev/ic/dp8390reg.h')
-rw-r--r--sys/dev/ic/dp8390reg.h38
1 files changed, 26 insertions, 12 deletions
diff --git a/sys/dev/ic/dp8390reg.h b/sys/dev/ic/dp8390reg.h
index 71e205f6f91..5de88e44770 100644
--- a/sys/dev/ic/dp8390reg.h
+++ b/sys/dev/ic/dp8390reg.h
@@ -1,5 +1,5 @@
-/* $OpenBSD: dp8390reg.h,v 1.4 1997/04/14 07:03:22 millert Exp $ */
-/* $NetBSD: dp8390reg.h,v 1.2 1995/04/12 16:12:42 mycroft Exp $ */
+/* $OpenBSD: dp8390reg.h,v 1.5 1998/09/22 06:41:13 fgsch Exp $ */
+/* $NetBSD: dp8390reg.h,v 1.3 1997/04/29 04:32:08 scottr Exp $ */
/*
* National Semiconductor DS8390 NIC register definitions.
@@ -318,10 +318,8 @@
#define ED_DCR_FT1 0x40
/*
- * QTS: Quad-word Transfer Select. QTS establishes 32-bit word transfers
- * for both remote and local DMA transfers. (XXX - correct name?)
+ * bit 7 (0x80) is unused/reserved
*/
-#define ED_DCR_QTS 0x80
/*
* Transmit Configuration Register (TCR) definitions
@@ -521,7 +519,7 @@
#define ED_RSR_DFR 0x80
/*
- * receive ring discriptor
+ * receive ring descriptor
*
* The National Semiconductor DS8390 Network interface controller uses the
* following receive ring headers. The way this works is that the memory on
@@ -530,12 +528,28 @@
* end block #'s in the NIC. For each packet that is put into the receive
* ring, one of these headers (4 bytes each) is tacked onto the front. The
* first byte is a copy of the receiver status register at the time the packet
- * was received. The following constants are offsets into the headers.
- */
-#define ED_RING_RSR 0 /* receiver status */
-#define ED_RING_NEXT_PACKET 1 /* pointer to next packet */
-#define ED_RING_COUNT 2 /* bytes in packet (length + 4) */
-#define ED_RING_HDRSZ 4 /* Header size */
+ * was received.
+ */
+struct dp8390_ring {
+ u_int8_t rsr; /* receiver status */
+ u_int8_t next_packet; /* pointer to next packet */
+ u_int16_t count; /* bytes in packet (length + 4) */
+};
+
+/*
+ * XXX For compatibility only! This needs to die when all drivers have
+ * been converted to be front ends to the MI driver.
+ */
+struct ed_ring {
+#if BYTE_ORDER == BIG_ENDIAN
+ u_char next_packet; /* pointer to next packet */
+ u_char rsr; /* receiver status */
+#else
+ u_char rsr; /* receiver status */
+ u_char next_packet; /* pointer to next packet */
+#endif
+ u_short count; /* bytes in packet (length + 4) */
+};
/*
* Common constants