Revert to previous (non hacked =) version now that the iommu is handled

correctly and it doesn't crash

1 files changed, 86 insertions, 40 deletions

diff --git a/sys/dev/ic/gemvar.h b/sys/dev/ic/gemvar.h
index 76b10e65cb6..beba25108b5 100644
--- a/sys/dev/ic/gemvar.h
+++ b/sys/dev/ic/gemvar.h
@@ -1,5 +1,5 @@
-/*	$OpenBSD: gemvar.h,v 1.5 2002/01/28 01:04:02 jason Exp $	*/
-/*	$NetBSD: gemvar.h,v 1.4 2001/10/18 15:09:15 thorpej Exp $ */
+/*	$OpenBSD: gemvar.h,v 1.6 2002/02/22 20:15:28 jason Exp $	*/
+/*	$NetBSD: gemvar.h,v 1.1 2001/09/16 00:11:43 eeh Exp $ */
 
 /*
  * 
@@ -33,14 +33,9 @@
 #ifndef	_IF_GEMVAR_H
 #define	_IF_GEMVAR_H
 
-
 #include <sys/queue.h>
 #include <sys/timeout.h>
 
-#if NRND > 0
-#include <sys/rnd.h>
-#endif
-
 /*
  * Misc. definitions for the Sun ``Gem'' Ethernet controller family driver.  
  */
@@ -52,11 +47,16 @@
  */
 #define	GEM_NTXSEGS		16
 
-#define	GEM_TXQUEUELEN		8
+#define	GEM_TXQUEUELEN		64
 #define	GEM_NTXDESC		(GEM_TXQUEUELEN * GEM_NTXSEGS)
 #define	GEM_NTXDESC_MASK	(GEM_NTXDESC - 1)
 #define	GEM_NEXTTX(x)		((x + 1) & GEM_NTXDESC_MASK)
 
+struct gem_sxd {
+	struct mbuf *sd_mbuf;
+	bus_dmamap_t sd_map;
+};
+
 /*
  * Receive descriptor list size.  We have one Rx buffer per incoming
  * packet, so this logic is a little simpler.
@@ -80,8 +80,6 @@ struct gem_control_data {
 	 * The receive descriptors.
 	 */
 	struct gem_desc gcd_rxdescs[GEM_NRXDESC];
-
-	u_int8_t gcd_txbufs[GEM_NTXDESC][MCLBYTES];
 };
 
 #define	GEM_CDOFF(x)		offsetof(struct gem_control_data, x)
@@ -89,25 +87,32 @@ struct gem_control_data {
 #define	GEM_CDRXOFF(x)		GEM_CDOFF(gcd_rxdescs[(x)])
 
 /*
- * Software state for transmit jobs.
+ * Software state for receive jobs.
  */
-struct gem_txsoft {
-	struct mbuf *txs_mbuf;		/* head of our mbuf chain */
-	bus_dmamap_t txs_dmamap;	/* our DMA map */
-	int txs_firstdesc;		/* first descriptor in packet */
-	int txs_lastdesc;		/* last descriptor in packet */
-	int txs_ndescs;			/* number of descriptors */
-	SIMPLEQ_ENTRY(gem_txsoft) txs_q;
+struct gem_rxsoft {
+	struct mbuf *rxs_mbuf;		/* head of our mbuf chain */
+	bus_dmamap_t rxs_dmamap;	/* our DMA map */
 };
 
-SIMPLEQ_HEAD(gem_txsq, gem_txsoft);
 
 /*
- * Software state for receive jobs.
+ * Table which describes the transmit threshold mode.  We generally
+ * start at index 0.  Whenever we get a transmit underrun, we increment
+ * our index, falling back if we encounter the NULL terminator.
  */
-struct gem_rxsoft {
-	struct mbuf *rxs_mbuf;		/* head of our mbuf chain */
-	bus_dmamap_t rxs_dmamap;	/* our DMA map */
+struct gem_txthresh_tab {
+	u_int32_t txth_opmode;		/* OPMODE bits */
+	const char *txth_name;		/* name of mode */
+};
+
+/*
+ * Some misc. statics, useful for debugging.
+ */
+struct gem_stats {
+	u_long		ts_tx_uf;	/* transmit underflow errors */
+	u_long		ts_tx_to;	/* transmit jabber timeouts */
+	u_long		ts_tx_ec;	/* excessve collision count */
+	u_long		ts_tx_lc;	/* late collision count */
 };
 
 /*
@@ -115,7 +120,7 @@ struct gem_rxsoft {
  */
 struct gem_softc {
 	struct device	sc_dev;		/* generic device information */
-	struct arpcom sc_arpcom;	/* ethernet common data */
+	struct arpcom	sc_arpcom;	/* ethernet common data */
 	struct mii_data	sc_mii;		/* MII media control */
 #define sc_media	sc_mii.mii_media/* shorthand */
 	struct timeout	sc_tick_ch;	/* tick callout */
@@ -125,7 +130,15 @@ struct gem_softc {
 	bus_dma_tag_t	sc_dmatag;	/* bus dma tag */
 	bus_dmamap_t	sc_dmamap;	/* bus dma handle */
 	bus_space_handle_t sc_h;	/* bus space handle for all regs */
-
+#if 0
+	/* The following may be needed for SBus */
+	bus_space_handle_t sc_seb;	/* HME Global registers */
+	bus_space_handle_t sc_erx;	/* HME ERX registers */
+	bus_space_handle_t sc_etx;	/* HME ETX registers */
+	bus_space_handle_t sc_mac;	/* HME MAC registers */
+	bus_space_handle_t sc_mif;	/* HME MIF registers */
+#endif
+	int		sc_burst;	/* DVMA burst size in effect */
 	int		sc_phys[2];	/* MII instance -> PHY map */
 
 	int		sc_mif_config;	/* Selected MII reg setting */
@@ -135,6 +148,8 @@ struct gem_softc {
 	void *sc_sdhook;		/* shutdown hook */
 	void *sc_powerhook;		/* power management hook */
 
+	struct gem_stats sc_stats;	/* debugging stats */
+
 	/*
 	 * Ring buffer DMA stuff.
 	 */
@@ -146,10 +161,10 @@ struct gem_softc {
 	/*
 	 * Software state for transmit and receive descriptors.
 	 */
-	struct gem_txsoft sc_txsoft[GEM_TXQUEUELEN];
-	struct gem_rxsoft sc_rxsoft[GEM_NRXDESC];
+	struct gem_sxd sc_txd[GEM_NTXDESC];
+	u_int32_t sc_tx_cnt, sc_tx_prod, sc_tx_cons;
 
-	u_int32_t	sc_tx_prod, sc_tx_cons, sc_tx_cnt;
+	struct gem_rxsoft sc_rxsoft[GEM_NRXDESC];
 
 	/*
 	 * Control data structures.
@@ -158,26 +173,45 @@ struct gem_softc {
 #define	sc_txdescs	sc_control_data->gcd_txdescs
 #define	sc_rxdescs	sc_control_data->gcd_rxdescs
 
-	int		sc_rxptr;	/* next ready RX descriptor/descsoft */
+	int			sc_txfree;		/* number of free Tx descriptors */
+	int			sc_txnext;		/* next ready Tx descriptor */
+
+	u_int32_t		sc_tdctl_ch;		/* conditional desc chaining */
+	u_int32_t		sc_tdctl_er;		/* conditional desc end-of-ring */
+
+	u_int32_t		sc_setup_fsls;	/* FS|LS on setup descriptor */
+
+	int			sc_rxptr;		/* next ready RX descriptor/descsoft */
 
 	/* ========== */
-	int		sc_inited;
-	int		sc_debug;
-	void		*sc_sh;		/* shutdownhook cookie */
+	int			sc_inited;
+	int			sc_debug;
+	void			*sc_sh;		/* shutdownhook cookie */
+	u_int8_t		sc_enaddr[ETHER_ADDR_LEN]; /* MAC address */
 
 	/* Special hardware hooks */
 	void	(*sc_hwreset) __P((struct gem_softc *));
 	void	(*sc_hwinit) __P((struct gem_softc *));
-
-#if NRND > 0
-	rndsource_element_t	rnd_source;
-#endif
 };
 
-
 #define	GEM_DMA_READ(sc, v)	(((sc)->sc_pci) ? letoh64(v) : betoh64(v))
 #define	GEM_DMA_WRITE(sc, v)	(((sc)->sc_pci) ? htole64(v) : htobe64(v))
 
+/*
+ * This macro returns the current media entry for *non-MII* media.
+ */
+#define	GEM_CURRENT_MEDIA(sc)						\
+	(IFM_SUBTYPE((sc)->sc_mii.mii_media.ifm_cur->ifm_media) != IFM_AUTO ? \
+	 (sc)->sc_mii.mii_media.ifm_cur : (sc)->sc_nway_active)
+
+/*
+ * This macro determines if a change to media-related OPMODE bits requires
+ * a chip reset.
+ */
+#define	GEM_MEDIA_NEEDSRESET(sc, newbits)				\
+	(((sc)->sc_opmode & OPMODE_MEDIA_BITS) !=			\
+	 ((newbits) & OPMODE_MEDIA_BITS))
+
 #define	GEM_CDTXADDR(sc, x)	((sc)->sc_cddma + GEM_CDTXOFF((x)))
 #define	GEM_CDRXADDR(sc, x)	((sc)->sc_cddma + GEM_CDRXOFF((x)))
 
@@ -223,16 +257,28 @@ do {									\
 	    GEM_DMA_WRITE((sc), __rxs->rxs_dmamap->dm_segs[0].ds_addr);	\
 	__rxd->gd_flags =						\
 	    GEM_DMA_WRITE((sc),						\
-			(((__m->m_ext.ext_size)<<GEM_RD_BUFSHIFT)	\
-				& GEM_RD_BUFSIZE) | GEM_RD_OWN);	\
+		(((__m->m_ext.ext_size)<<GEM_RD_BUFSHIFT)		\
+	    & GEM_RD_BUFSIZE) | GEM_RD_OWN);				\
 	GEM_CDRXSYNC((sc), (x), BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); \
 } while (0)
 
 #ifdef _KERNEL
-void	gem_attach __P((struct gem_softc *, uint8_t *));
+void	gem_attach __P((struct gem_softc *, const u_int8_t *));
+int	gem_activate __P((struct device *, enum devact));
+int	gem_detach __P((struct gem_softc *));
 int	gem_intr __P((void *));
+int	gem_read_srom __P((struct gem_softc *));
+int	gem_srom_crcok __P((const u_int8_t *));
+int	gem_isv_srom __P((const u_int8_t *));
+int	gem_isv_srom_enaddr __P((struct gem_softc *, u_int8_t *));
+int	gem_parse_old_srom __P((struct gem_softc *, u_int8_t *));
 
+int	gem_mediachange __P((struct ifnet *));
+void	gem_mediastatus __P((struct ifnet *, struct ifmediareq *));
+
+void	gem_config __P((struct gem_softc *));
 void	gem_reset __P((struct gem_softc *));
+int	gem_intr __P((void *));
 #endif /* _KERNEL */