diff options
| author | Federico G. Schwindt <fgsch@cvs.openbsd.org> | 2002-06-21 03:02:01 +0000 |
|---|---|---|
| committer | Federico G. Schwindt <fgsch@cvs.openbsd.org> | 2002-06-21 03:02:01 +0000 |
| commit | e96803101c250568a4db3bd6dedecd34a2680d14 (patch) | |
| tree | 59a2b33da48b12f10656b791598afc7b3dd6842f /sys/dev/ic/if_wireg.h | |
| parent | b65f17cad5cd5c3e59274e3676ee62c8b5987c2c (diff) | |
ugly kludge to deal correctly with endianess in sparc and sparc64.
millert@ ok.
Diffstat (limited to 'sys/dev/ic/if_wireg.h')
| -rw-r--r-- | sys/dev/ic/if_wireg.h | 35 |
1 files changed, 31 insertions, 4 deletions
diff --git a/sys/dev/ic/if_wireg.h b/sys/dev/ic/if_wireg.h index b0e379534f2..447ee535091 100644 --- a/sys/dev/ic/if_wireg.h +++ b/sys/dev/ic/if_wireg.h @@ -1,4 +1,4 @@ -/* $OpenBSD: if_wireg.h,v 1.19 2002/05/01 04:31:07 millert Exp $ */ +/* $OpenBSD: if_wireg.h,v 1.20 2002/06/21 03:02:00 fgsch Exp $ */ /* * Copyright (c) 1997, 1998, 1999 @@ -81,15 +81,40 @@ /* * register space access macros */ + +#if defined(__sparc__) + #define CSR_WRITE_4(sc, reg, val) \ bus_space_write_4(sc->wi_btag, sc->wi_bhandle, \ - (sc->sc_pci? reg * 2: reg) , val) + (sc->sc_pci? reg * 2: reg), htole32(val)) #define CSR_WRITE_2(sc, reg, val) \ bus_space_write_2(sc->wi_btag, sc->wi_bhandle, \ - (sc->sc_pci? reg * 2: reg) , val) + (sc->sc_pci? reg * 2: reg), htole16(val)) #define CSR_WRITE_1(sc, reg, val) \ bus_space_write_1(sc->wi_btag, sc->wi_bhandle, \ - (sc->sc_pci? reg * 2: reg) , val) + (sc->sc_pci? reg * 2: reg), val) + +#define CSR_READ_4(sc, reg) \ + letoh32(bus_space_read_4(sc->wi_btag, sc->wi_bhandle, \ + (sc->sc_pci? reg * 2: reg))) +#define CSR_READ_2(sc, reg) \ + letoh16(bus_space_read_2(sc->wi_btag, sc->wi_bhandle, \ + (sc->sc_pci? reg * 2: reg))) +#define CSR_READ_1(sc, reg) \ + bus_space_read_1(sc->wi_btag, sc->wi_bhandle, \ + (sc->sc_pci? reg * 2: reg)) + +#else + +#define CSR_WRITE_4(sc, reg, val) \ + bus_space_write_4(sc->wi_btag, sc->wi_bhandle, \ + (sc->sc_pci? reg * 2: reg), val) +#define CSR_WRITE_2(sc, reg, val) \ + bus_space_write_2(sc->wi_btag, sc->wi_bhandle, \ + (sc->sc_pci? reg * 2: reg), val) +#define CSR_WRITE_1(sc, reg, val) \ + bus_space_write_1(sc->wi_btag, sc->wi_bhandle, \ + (sc->sc_pci? reg * 2: reg), val) #define CSR_READ_4(sc, reg) \ bus_space_read_4(sc->wi_btag, sc->wi_bhandle, \ @@ -101,6 +126,8 @@ bus_space_read_1(sc->wi_btag, sc->wi_bhandle, \ (sc->sc_pci? reg * 2: reg)) +#endif + #define CSR_READ_RAW_2(sc, ba, dst, sz) \ bus_space_read_raw_multi_2((sc)->wi_btag, (sc)->wi_bhandle, \ (sc->sc_pci? ba * 2: ba), (dst), (sz)) |