if_ep splitup

3 files changed, 1415 insertions, 0 deletions

diff --git a/sys/dev/ic/elink3.c b/sys/dev/ic/elink3.c
new file mode 100644
index 00000000000..783ad4b1f39
--- /dev/null
+++ b/sys/dev/ic/elink3.c
@@ -0,0 +1,1016 @@
+/*	$NetBSD: elink3.c,v 1.1 1996/04/25 02:17:34 thorpej Exp $	*/
+
+/*
+ * Copyright (c) 1994 Herb Peyerl <hpeyerl@novatel.ca>
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. All advertising materials mentioning features or use of this software
+ *    must display the following acknowledgement:
+ *      This product includes software developed by Herb Peyerl.
+ * 4. The name of Herb Peyerl may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "bpfilter.h"
+
+#include <sys/param.h>
+#include <sys/mbuf.h>
+#include <sys/socket.h>
+#include <sys/ioctl.h>
+#include <sys/errno.h>
+#include <sys/syslog.h>
+#include <sys/select.h>
+#include <sys/device.h>
+
+#include <net/if.h>
+#include <net/netisr.h>
+#include <net/if_dl.h>
+#include <net/if_types.h>
+#include <net/netisr.h>
+
+#ifdef INET
+#include <netinet/in.h>
+#include <netinet/in_systm.h>
+#include <netinet/in_var.h>
+#include <netinet/ip.h>
+#include <netinet/if_ether.h>
+#endif
+
+#ifdef NS
+#include <netns/ns.h>
+#include <netns/ns_if.h>
+#endif
+
+#if NBPFILTER > 0
+#include <net/bpf.h>
+#include <net/bpfdesc.h>
+#endif
+
+#include <machine/cpu.h>
+#include <machine/pio.h>
+
+#include <dev/ic/elink3var.h>
+#include <dev/ic/elink3reg.h>
+
+#define ETHER_MIN_LEN	64
+#define ETHER_MAX_LEN   1518
+#define ETHER_ADDR_LEN  6
+
+struct cfdriver ep_cd = {
+	NULL, "ep", DV_IFNET
+};
+
+static void epxstat __P((struct ep_softc *));
+static int epstatus __P((struct ep_softc *));
+void epinit __P((struct ep_softc *));
+int epioctl __P((struct ifnet *, u_long, caddr_t));
+void epstart __P((struct ifnet *));
+void epwatchdog __P((int));
+void epreset __P((struct ep_softc *));
+void epread __P((struct ep_softc *));
+struct mbuf *epget __P((struct ep_softc *, int));
+void epmbuffill __P((struct ep_softc *));
+void epmbufempty __P((struct ep_softc *));
+void epstop __P((struct ep_softc *));
+void epsetfilter __P((struct ep_softc *));
+void epsetlink __P((struct ep_softc *));
+u_short epreadeeprom __P((int id_port, int offset));
+
+static int epbusyeeprom __P((struct ep_softc *));
+
+void
+epconfig(sc, conn)
+	struct ep_softc *sc;
+	u_int conn;
+{
+	u_short i;
+
+	struct ifnet *ifp = &sc->sc_arpcom.ac_if;
+
+	sc->ep_connectors = 0;
+	printf("%s: ", sc->sc_dev.dv_xname);
+	if (conn & IS_AUI) {
+		printf("aui");
+		sc->ep_connectors |= AUI;
+	}
+	if (conn & IS_BNC) {
+		if (sc->ep_connectors)
+			printf("/");
+		printf("bnc");
+		sc->ep_connectors |= BNC;
+	}
+	if (conn & IS_UTP) {
+		if (sc->ep_connectors)
+			printf("/");
+		printf("utp");
+		sc->ep_connectors |= UTP;
+	}
+	if (!sc->ep_connectors)
+		printf("no connectors!");
+
+	/*
+	 * Read the station address from the eeprom
+	 */
+	for (i = 0; i < 3; i++) {
+		u_short x;
+		if (epbusyeeprom(sc))
+			return;
+		outw(BASE + EP_W0_EEPROM_COMMAND, READ_EEPROM | i);
+		if (epbusyeeprom(sc))
+			return;
+		x = inw(BASE + EP_W0_EEPROM_DATA);
+		sc->sc_arpcom.ac_enaddr[(i << 1)] = x >> 8;
+		sc->sc_arpcom.ac_enaddr[(i << 1) + 1] = x;
+	}
+
+	printf(" address %s\n", ether_sprintf(sc->sc_arpcom.ac_enaddr));
+
+	ifp->if_unit = sc->sc_dev.dv_unit;
+	ifp->if_name = ep_cd.cd_name;
+	ifp->if_start = epstart;
+	ifp->if_ioctl = epioctl;
+	ifp->if_watchdog = epwatchdog;
+	ifp->if_flags =
+	    IFF_BROADCAST | IFF_SIMPLEX | IFF_NOTRAILERS | IFF_MULTICAST;
+
+	if_attach(ifp);
+	ether_ifattach(ifp);
+
+#if NBPFILTER > 0
+	bpfattach(&sc->sc_arpcom.ac_if.if_bpf, ifp, DLT_EN10MB,
+		  sizeof(struct ether_header));
+#endif
+
+	sc->tx_start_thresh = 20;	/* probably a good starting point. */
+}
+
+/*
+ * The order in here seems important. Otherwise we may not receive
+ * interrupts. ?!
+ */
+void
+epinit(sc)
+	register struct ep_softc *sc;
+{
+	register struct ifnet *ifp = &sc->sc_arpcom.ac_if;
+	int i;
+
+	while (inw(BASE + EP_STATUS) & S_COMMAND_IN_PROGRESS)
+		;
+
+	if (sc->bustype != EP_BUS_PCI) {
+		GO_WINDOW(0);
+		outw(BASE + EP_W0_CONFIG_CTRL, 0);
+		outw(BASE + EP_W0_CONFIG_CTRL, ENABLE_DRQ_IRQ);
+	}
+
+	if (sc->bustype == EP_BUS_PCMCIA) {
+#ifdef EP_COAX_DEFAULT
+		outw(BASE + EP_W0_ADDRESS_CFG,3<<14);
+#else
+		outw(BASE + EP_W0_ADDRESS_CFG,0<<14);
+#endif
+		outw(BASE + EP_W0_RESOURCE_CFG, 0x3f00);
+	}
+
+	GO_WINDOW(2);
+	for (i = 0; i < 6; i++)	/* Reload the ether_addr. */
+		outb(BASE + EP_W2_ADDR_0 + i, sc->sc_arpcom.ac_enaddr[i]);
+
+	outw(BASE + EP_COMMAND, RX_RESET);
+	outw(BASE + EP_COMMAND, TX_RESET);
+
+	GO_WINDOW(1);		/* Window 1 is operating window */
+	for (i = 0; i < 31; i++)
+		inb(BASE + EP_W1_TX_STATUS);
+
+	outw(BASE + EP_COMMAND, SET_RD_0_MASK | S_CARD_FAILURE | 
+				S_RX_COMPLETE | S_TX_COMPLETE | S_TX_AVAIL);
+	outw(BASE + EP_COMMAND, SET_INTR_MASK | S_CARD_FAILURE |
+				S_RX_COMPLETE | S_TX_COMPLETE | S_TX_AVAIL);
+
+	/*
+	 * Attempt to get rid of any stray interrupts that occured during
+	 * configuration.  On the i386 this isn't possible because one may
+	 * already be queued.  However, a single stray interrupt is
+	 * unimportant.
+	 */
+	outw(BASE + EP_COMMAND, ACK_INTR | 0xff);
+
+	epsetfilter(sc);
+	epsetlink(sc);
+
+	outw(BASE + EP_COMMAND, RX_ENABLE);
+	outw(BASE + EP_COMMAND, TX_ENABLE);
+
+	epmbuffill(sc);
+
+	/* Interface is now `running', with no output active. */
+	ifp->if_flags |= IFF_RUNNING;
+	ifp->if_flags &= ~IFF_OACTIVE;
+
+	/* Attempt to start output, if any. */
+	epstart(ifp);
+}
+
+void
+epsetfilter(sc)
+	register struct ep_softc *sc;
+{
+	register struct ifnet *ifp = &sc->sc_arpcom.ac_if;
+
+	GO_WINDOW(1);		/* Window 1 is operating window */
+	outw(BASE + EP_COMMAND, SET_RX_FILTER |
+	    FIL_INDIVIDUAL | FIL_BRDCST |
+	    ((ifp->if_flags & IFF_MULTICAST) ? FIL_MULTICAST : 0 ) |
+	    ((ifp->if_flags & IFF_PROMISC) ? FIL_PROMISC : 0 ));
+}
+
+void
+epsetlink(sc)
+	register struct ep_softc *sc;
+{
+	register struct ifnet *ifp = &sc->sc_arpcom.ac_if;
+
+	/*
+	 * you can `ifconfig (link0|-link0) ep0' to get the following
+	 * behaviour:
+	 *	-link0	disable AUI/UTP. enable BNC.
+	 *	link0	disable BNC. enable AUI.
+	 *	link1	if the card has a UTP connector, and link0 is
+	 *		set too, then you get the UTP port.
+	 */
+	GO_WINDOW(4);
+	outw(BASE + EP_W4_MEDIA_TYPE, DISABLE_UTP);
+	if (!(ifp->if_flags & IFF_LINK0) && (sc->ep_connectors & BNC)) {
+		if (sc->bustype == EP_BUS_PCMCIA) {
+			GO_WINDOW(0);
+			outw(BASE + EP_W0_ADDRESS_CFG,3<<14);
+			GO_WINDOW(1);
+		}
+		outw(BASE + EP_COMMAND, START_TRANSCEIVER);
+		delay(1000);
+	}
+	if (ifp->if_flags & IFF_LINK0) {
+		outw(BASE + EP_COMMAND, STOP_TRANSCEIVER);
+		delay(1000);
+		if ((ifp->if_flags & IFF_LINK1) && (sc->ep_connectors & UTP)) {
+			if (sc->bustype == EP_BUS_PCMCIA) {
+				GO_WINDOW(0);
+				outw(BASE + EP_W0_ADDRESS_CFG,0<<14);
+				GO_WINDOW(4);
+			}
+			outw(BASE + EP_W4_MEDIA_TYPE, ENABLE_UTP);
+		}
+	}
+	GO_WINDOW(1);
+}
+
+/*
+ * Start outputting on the interface.
+ * Always called as splnet().
+ */
+void
+epstart(ifp)
+	struct ifnet *ifp;
+{
+	register struct ep_softc *sc = ep_cd.cd_devs[ifp->if_unit];
+	struct mbuf *m, *m0;
+	int sh, len, pad;
+
+	/* Don't transmit if interface is busy or not running */
+	if ((ifp->if_flags & (IFF_RUNNING|IFF_OACTIVE)) != IFF_RUNNING)
+		return;
+
+startagain:
+	/* Sneak a peek at the next packet */
+	m0 = ifp->if_snd.ifq_head;
+	if (m0 == 0)
+		return;
+
+	/* We need to use m->m_pkthdr.len, so require the header */
+	if ((m0->m_flags & M_PKTHDR) == 0)
+		panic("epstart: no header mbuf");
+	len = m0->m_pkthdr.len;
+
+	pad = (4 - len) & 3;
+
+	/*
+	 * The 3c509 automatically pads short packets to minimum ethernet
+	 * length, but we drop packets that are too large. Perhaps we should
+	 * truncate them instead?
+	 */
+	if (len + pad > ETHER_MAX_LEN) {
+		/* packet is obviously too large: toss it */
+		++ifp->if_oerrors;
+		IF_DEQUEUE(&ifp->if_snd, m0);
+		m_freem(m0);
+		goto readcheck;
+	}
+
+	if (inw(BASE + EP_W1_FREE_TX) < len + pad + 4) {
+		outw(BASE + EP_COMMAND, SET_TX_AVAIL_THRESH | (len + pad + 4));
+		/* not enough room in FIFO */
+		ifp->if_flags |= IFF_OACTIVE;
+		return;
+	} else {
+		outw(BASE + EP_COMMAND, SET_TX_AVAIL_THRESH | 2044);
+	}
+
+	IF_DEQUEUE(&ifp->if_snd, m0);
+	if (m0 == 0)		/* not really needed */
+		return;
+
+	outw(BASE + EP_COMMAND, SET_TX_START_THRESH |
+	    (len / 4 + sc->tx_start_thresh));
+
+#if NBPFILTER > 0
+	if (ifp->if_bpf)
+		bpf_mtap(ifp->if_bpf, m0);
+#endif
+
+	/*
+	 * Do the output at splhigh() so that an interrupt from another device
+	 * won't cause a FIFO underrun.
+	 */
+	sh = splhigh();
+
+	outw(BASE + EP_W1_TX_PIO_WR_1, len);
+	outw(BASE + EP_W1_TX_PIO_WR_1, 0xffff);	/* Second dword meaningless */
+	if (EP_IS_BUS_32(sc->bustype)) {
+		for (m = m0; m; ) {
+			if (m->m_len > 3)
+				outsl(BASE + EP_W1_TX_PIO_WR_1,
+				      mtod(m, caddr_t), m->m_len / 4);
+			if (m->m_len & 3)
+				outsb(BASE + EP_W1_TX_PIO_WR_1,
+				      mtod(m, caddr_t) + (m->m_len & ~3),
+				      m->m_len & 3);
+			MFREE(m, m0);
+			m = m0;
+		}
+	} else {
+		for (m = m0; m; ) {
+			if (m->m_len > 1)
+				outsw(BASE + EP_W1_TX_PIO_WR_1,
+				      mtod(m, caddr_t), m->m_len / 2);
+			if (m->m_len & 1)
+				outb(BASE + EP_W1_TX_PIO_WR_1,
+				     *(mtod(m, caddr_t) + m->m_len - 1));
+			MFREE(m, m0);
+			m = m0;
+		}
+	}
+	while (pad--)
+		outb(BASE + EP_W1_TX_PIO_WR_1, 0);
+
+	splx(sh);
+
+	++ifp->if_opackets;
+
+readcheck:
+	if ((inw(BASE + EP_W1_RX_STATUS) & ERR_INCOMPLETE) == 0) {
+		/* We received a complete packet. */
+		u_short status = inw(BASE + EP_STATUS);
+
+		if ((status & S_INTR_LATCH) == 0) {
+			/*
+			 * No interrupt, read the packet and continue
+			 * Is  this supposed to happen? Is my motherboard 
+			 * completely busted?
+			 */
+			epread(sc);
+		}
+		else
+			/* Got an interrupt, return so that it gets serviced. */
+			return;
+	}
+	else {
+		/* Check if we are stuck and reset [see XXX comment] */
+		if (epstatus(sc)) {
+			if (ifp->if_flags & IFF_DEBUG)
+				printf("%s: adapter reset\n",
+				       sc->sc_dev.dv_xname);
+			epreset(sc);
+		}
+	}
+
+	goto startagain;
+}
+
+
+/*
+ * XXX: The 3c509 card can get in a mode where both the fifo status bit
+ *	FIFOS_RX_OVERRUN and the status bit ERR_INCOMPLETE are set
+ *	We detect this situation and we reset the adapter.
+ *	It happens at times when there is a lot of broadcast traffic
+ *	on the cable (once in a blue moon).
+ */
+static int
+epstatus(sc)
+	register struct ep_softc *sc;
+{
+	u_short fifost;
+
+	/*
+	 * Check the FIFO status and act accordingly
+	 */
+	GO_WINDOW(4);
+	fifost = inw(BASE + EP_W4_FIFO_DIAG);
+	GO_WINDOW(1);
+
+	if (fifost & FIFOS_RX_UNDERRUN) {
+		if (sc->sc_arpcom.ac_if.if_flags & IFF_DEBUG)
+			printf("%s: RX underrun\n", sc->sc_dev.dv_xname);
+		epreset(sc);
+		return 0;
+	}
+
+	if (fifost & FIFOS_RX_STATUS_OVERRUN) {
+		if (sc->sc_arpcom.ac_if.if_flags & IFF_DEBUG)
+			printf("%s: RX Status overrun\n", sc->sc_dev.dv_xname);
+		return 1;
+	}
+
+	if (fifost & FIFOS_RX_OVERRUN) {
+		if (sc->sc_arpcom.ac_if.if_flags & IFF_DEBUG)
+			printf("%s: RX overrun\n", sc->sc_dev.dv_xname);
+		return 1;
+	}
+
+	if (fifost & FIFOS_TX_OVERRUN) {
+		if (sc->sc_arpcom.ac_if.if_flags & IFF_DEBUG)
+			printf("%s: TX overrun\n", sc->sc_dev.dv_xname);
+		epreset(sc);
+		return 0;
+	}
+
+	return 0;
+}
+
+
+static void
+eptxstat(sc)
+	register struct ep_softc *sc;
+{
+	int i;
+
+	/*
+	 * We need to read+write TX_STATUS until we get a 0 status
+	 * in order to turn off the interrupt flag.
+	 */
+	while ((i = inb(BASE + EP_W1_TX_STATUS)) & TXS_COMPLETE) {
+		outb(BASE + EP_W1_TX_STATUS, 0x0);
+
+		if (i & TXS_JABBER) {
+			++sc->sc_arpcom.ac_if.if_oerrors;
+			if (sc->sc_arpcom.ac_if.if_flags & IFF_DEBUG)
+				printf("%s: jabber (%x)\n",
+				       sc->sc_dev.dv_xname, i);
+			epreset(sc);
+		} else if (i & TXS_UNDERRUN) {
+			++sc->sc_arpcom.ac_if.if_oerrors;
+			if (sc->sc_arpcom.ac_if.if_flags & IFF_DEBUG)
+				printf("%s: fifo underrun (%x) @%d\n",
+				       sc->sc_dev.dv_xname, i,
+				       sc->tx_start_thresh);
+			if (sc->tx_succ_ok < 100)
+				    sc->tx_start_thresh = min(ETHER_MAX_LEN,
+					    sc->tx_start_thresh + 20);
+			sc->tx_succ_ok = 0;
+			epreset(sc);
+		} else if (i & TXS_MAX_COLLISION) {
+			++sc->sc_arpcom.ac_if.if_collisions;
+			outw(BASE + EP_COMMAND, TX_ENABLE);
+			sc->sc_arpcom.ac_if.if_flags &= ~IFF_OACTIVE;
+		} else
+			sc->tx_succ_ok = (sc->tx_succ_ok+1) & 127;
+			
+	}
+}
+
+int
+epintr(arg)
+	void *arg;
+{
+	register struct ep_softc *sc = arg;
+	struct ifnet *ifp = &sc->sc_arpcom.ac_if;
+	u_short status;
+	int ret = 0;
+
+	for (;;) {
+		outw(BASE + EP_COMMAND, C_INTR_LATCH);
+
+		status = inw(BASE + EP_STATUS);
+
+		if ((status & (S_TX_COMPLETE | S_TX_AVAIL |
+			       S_RX_COMPLETE | S_CARD_FAILURE)) == 0)
+			break;
+
+		ret = 1;
+
+		/*
+		 * Acknowledge any interrupts.  It's important that we do this
+		 * first, since there would otherwise be a race condition.
+		 * Due to the i386 interrupt queueing, we may get spurious
+		 * interrupts occasionally.
+		 */
+		outw(BASE + EP_COMMAND, ACK_INTR | status);
+
+		if (status & S_RX_COMPLETE)
+			epread(sc);
+		if (status & S_TX_AVAIL) {
+			sc->sc_arpcom.ac_if.if_flags &= ~IFF_OACTIVE;
+			epstart(&sc->sc_arpcom.ac_if);
+		}
+		if (status & S_CARD_FAILURE) {
+			printf("%s: adapter failure (%x)\n",
+			       sc->sc_dev.dv_xname, status);
+			epreset(sc);
+			return (1);
+		}
+		if (status & S_TX_COMPLETE) {
+			eptxstat(sc);
+			epstart(ifp);
+		}
+	}	
+
+	/* no more interrupts */
+	return (ret);
+}
+
+void
+epread(sc)
+	register struct ep_softc *sc;
+{
+	struct ifnet *ifp = &sc->sc_arpcom.ac_if;
+	struct mbuf *m;
+	struct ether_header *eh;
+	int len;
+
+	len = inw(BASE + EP_W1_RX_STATUS);
+
+again:
+	if (ifp->if_flags & IFF_DEBUG) {
+		int err = len & ERR_MASK;
+		char *s = NULL;
+
+		if (len & ERR_INCOMPLETE)
+			s = "incomplete packet";
+		else if (err == ERR_OVERRUN)
+			s = "packet overrun";
+		else if (err == ERR_RUNT)
+			s = "runt packet";
+		else if (err == ERR_ALIGNMENT)
+			s = "bad alignment";
+		else if (err == ERR_CRC)
+			s = "bad crc";
+		else if (err == ERR_OVERSIZE)
+			s = "oversized packet";
+		else if (err == ERR_DRIBBLE)
+			s = "dribble bits";
+
+		if (s)
+			printf("%s: %s\n", sc->sc_dev.dv_xname, s);
+	}
+
+	if (len & ERR_INCOMPLETE)
+		return;
+
+	if (len & ERR_RX) {
+		++ifp->if_ierrors;
+		goto abort;
+	}
+
+	len &= RX_BYTES_MASK;	/* Lower 11 bits = RX bytes. */
+
+	/* Pull packet off interface. */
+	m = epget(sc, len);
+	if (m == 0) {
+		ifp->if_ierrors++;
+		goto abort;
+	}
+
+	++ifp->if_ipackets;
+
+	/* We assume the header fit entirely in one mbuf. */
+	eh = mtod(m, struct ether_header *);
+
+#if NBPFILTER > 0
+	/*
+	 * Check if there's a BPF listener on this interface.
+	 * If so, hand off the raw packet to BPF.
+	 */
+	if (ifp->if_bpf) {
+		bpf_mtap(ifp->if_bpf, m);
+
+		/*
+		 * Note that the interface cannot be in promiscuous mode if
+		 * there are no BPF listeners.  And if we are in promiscuous
+		 * mode, we have to check if this packet is really ours.
+		 */
+		if ((ifp->if_flags & IFF_PROMISC) &&
+		    (eh->ether_dhost[0] & 1) == 0 && /* !mcast and !bcast */
+		    bcmp(eh->ether_dhost, sc->sc_arpcom.ac_enaddr,
+			    sizeof(eh->ether_dhost)) != 0) {
+			m_freem(m);
+			return;
+		}
+	}
+#endif
+
+	/* We assume the header fit entirely in one mbuf. */
+	m_adj(m, sizeof(struct ether_header));
+	ether_input(ifp, eh, m);
+
+	/*
+	 * In periods of high traffic we can actually receive enough
+	 * packets so that the fifo overrun bit will be set at this point,
+	 * even though we just read a packet. In this case we
+	 * are not going to receive any more interrupts. We check for
+	 * this condition and read again until the fifo is not full.
+	 * We could simplify this test by not using epstatus(), but
+	 * rechecking the RX_STATUS register directly. This test could
+	 * result in unnecessary looping in cases where there is a new
+	 * packet but the fifo is not full, but it will not fix the
+	 * stuck behavior.
+	 *
+	 * Even with this improvement, we still get packet overrun errors
+	 * which are hurting performance. Maybe when I get some more time
+	 * I'll modify epread() so that it can handle RX_EARLY interrupts.
+	 */
+	if (epstatus(sc)) {
+		len = inw(BASE + EP_W1_RX_STATUS);
+		/* Check if we are stuck and reset [see XXX comment] */
+		if (len & ERR_INCOMPLETE) {
+			if (ifp->if_flags & IFF_DEBUG)
+				printf("%s: adapter reset\n",
+				       sc->sc_dev.dv_xname);
+			epreset(sc);
+			return;
+		}
+		goto again;
+	}
+
+	return;
+
+abort:
+	outw(BASE + EP_COMMAND, RX_DISCARD_TOP_PACK);
+	while (inw(BASE + EP_STATUS) & S_COMMAND_IN_PROGRESS)
+		;
+}
+
+struct mbuf *
+epget(sc, totlen)
+	struct ep_softc *sc;
+	int totlen;
+{
+	struct ifnet *ifp = &sc->sc_arpcom.ac_if;
+	struct mbuf *top, **mp, *m;
+	int len;
+	int sh;
+
+	m = sc->mb[sc->next_mb];
+	sc->mb[sc->next_mb] = 0;
+	if (m == 0) {
+		MGETHDR(m, M_DONTWAIT, MT_DATA);
+		if (m == 0)
+			return 0;
+	} else {
+		/* If the queue is no longer full, refill. */
+		if (sc->last_mb == sc->next_mb)
+			timeout(epmbuffill, sc, 1);
+		/* Convert one of our saved mbuf's. */
+		sc->next_mb = (sc->next_mb + 1) % MAX_MBS;
+		m->m_data = m->m_pktdat;
+		m->m_flags = M_PKTHDR;
+	}
+	m->m_pkthdr.rcvif = ifp;
+	m->m_pkthdr.len = totlen;
+	len = MHLEN;
+	top = 0;
+	mp = &top;
+
+	/*
+	 * We read the packet at splhigh() so that an interrupt from another
+	 * device doesn't cause the card's buffer to overflow while we're
+	 * reading it.  We may still lose packets at other times.
+	 */
+	sh = splhigh();
+
+	while (totlen > 0) {
+		if (top) {
+			m = sc->mb[sc->next_mb];
+			sc->mb[sc->next_mb] = 0;
+			if (m == 0) {
+				MGET(m, M_DONTWAIT, MT_DATA);
+				if (m == 0) {
+					splx(sh);
+					m_freem(top);
+					return 0;
+				}
+			} else {
+				sc->next_mb = (sc->next_mb + 1) % MAX_MBS;
+			}
+			len = MLEN;
+		}
+		if (totlen >= MINCLSIZE) {
+			MCLGET(m, M_DONTWAIT);
+			if (m->m_flags & M_EXT)
+				len = MCLBYTES;
+		}
+		len = min(totlen, len);
+		if (EP_IS_BUS_32(sc->bustype)) {
+			if (len > 3) {
+				len &= ~3;
+				insl(BASE + EP_W1_RX_PIO_RD_1,
+				     mtod(m, caddr_t), len / 4);
+			} else
+				insb(BASE + EP_W1_RX_PIO_RD_1,
+				     mtod(m, caddr_t), len);
+		} else {
+			if (len > 1) {
+				len &= ~1;
+				insw(BASE + EP_W1_RX_PIO_RD_1,
+				     mtod(m, caddr_t), len / 2);
+			} else
+				*(mtod(m, caddr_t)) =
+				    inb(BASE + EP_W1_RX_PIO_RD_1);
+		}
+		m->m_len = len;
+		totlen -= len;
+		*mp = m;
+		mp = &m->m_next;
+	}
+
+	outw(BASE + EP_COMMAND, RX_DISCARD_TOP_PACK);
+	while (inw(BASE + EP_STATUS) & S_COMMAND_IN_PROGRESS)
+		;
+
+	splx(sh);
+
+	return top;
+}
+
+int
+epioctl(ifp, cmd, data)
+	register struct ifnet *ifp;
+	u_long cmd;
+	caddr_t data;
+{
+	struct ep_softc *sc = ep_cd.cd_devs[ifp->if_unit];
+	struct ifaddr *ifa = (struct ifaddr *)data;
+	struct ifreq *ifr = (struct ifreq *)data;
+	int s, error = 0;
+
+	s = splnet();
+
+	switch (cmd) {
+
+	case SIOCSIFADDR:
+		ifp->if_flags |= IFF_UP;
+
+		switch (ifa->ifa_addr->sa_family) {
+#ifdef INET
+		case AF_INET:
+			epinit(sc);
+			arp_ifinit(&sc->sc_arpcom, ifa);
+			break;
+#endif
+#ifdef NS
+		case AF_NS:
+		    {
+			register struct ns_addr *ina = &IA_SNS(ifa)->sns_addr;
+
+			if (ns_nullhost(*ina))
+				ina->x_host =
+				    *(union ns_host *)(sc->sc_arpcom.ac_enaddr);
+			else
+				bcopy(ina->x_host.c_host,
+				    sc->sc_arpcom.ac_enaddr,
+				    sizeof(sc->sc_arpcom.ac_enaddr));
+			/* Set new address. */
+			epinit(sc);
+			break;
+		    }
+#endif
+		default:
+			epinit(sc);
+			break;
+		}
+		break;
+
+	case SIOCSIFFLAGS:
+		if ((ifp->if_flags & IFF_UP) == 0 &&
+		    (ifp->if_flags & IFF_RUNNING) != 0) {
+			/*
+			 * If interface is marked down and it is running, then
+			 * stop it.
+			 */
+			epstop(sc);
+			ifp->if_flags &= ~IFF_RUNNING;
+		} else if ((ifp->if_flags & IFF_UP) != 0 &&
+			   (ifp->if_flags & IFF_RUNNING) == 0) {
+			/*
+			 * If interface is marked up and it is stopped, then
+			 * start it.
+			 */
+			epinit(sc);
+		} else {
+			/*
+			 * deal with flags changes:
+			 * IFF_MULTICAST, IFF_PROMISC,
+			 * IFF_LINK0, IFF_LINK1,
+			 */
+			epsetfilter(sc);
+			epsetlink(sc);
+		}
+		break;
+
+	case SIOCADDMULTI:
+	case SIOCDELMULTI:
+		error = (cmd == SIOCADDMULTI) ?
+		    ether_addmulti(ifr, &sc->sc_arpcom) :
+		    ether_delmulti(ifr, &sc->sc_arpcom);
+
+		if (error == ENETRESET) {
+			/*
+			 * Multicast list has changed; set the hardware filter
+			 * accordingly.
+			 */
+			epreset(sc);
+			error = 0;
+		}
+		break;
+
+	default:
+		error = EINVAL;
+		break;
+	}
+
+	splx(s);
+	return (error);
+}
+
+void
+epreset(sc)
+	struct ep_softc *sc;
+{
+	int s;
+
+	s = splnet();
+	epstop(sc);
+	epinit(sc);
+	splx(s);
+}
+
+void
+epwatchdog(unit)
+	int unit;
+{
+	struct ep_softc *sc = ep_cd.cd_devs[unit];
+
+	log(LOG_ERR, "%s: device timeout\n", sc->sc_dev.dv_xname);
+	++sc->sc_arpcom.ac_if.if_oerrors;
+
+	epreset(sc);
+}
+
+void
+epstop(sc)
+	register struct ep_softc *sc;
+{
+
+	outw(BASE + EP_COMMAND, RX_DISABLE);
+	outw(BASE + EP_COMMAND, RX_DISCARD_TOP_PACK);
+	while (inw(BASE + EP_STATUS) & S_COMMAND_IN_PROGRESS)
+		;
+	outw(BASE + EP_COMMAND, TX_DISABLE);
+	outw(BASE + EP_COMMAND, STOP_TRANSCEIVER);
+	outw(BASE + EP_COMMAND, RX_RESET);
+	outw(BASE + EP_COMMAND, TX_RESET);
+	outw(BASE + EP_COMMAND, C_INTR_LATCH);
+	outw(BASE + EP_COMMAND, SET_RD_0_MASK);
+	outw(BASE + EP_COMMAND, SET_INTR_MASK);
+	outw(BASE + EP_COMMAND, SET_RX_FILTER);
+
+	epmbufempty(sc);
+}
+
+/*
+ * We get eeprom data from the id_port given an offset into the
+ * eeprom.  Basically; after the ID_sequence is sent to all of
+ * the cards; they enter the ID_CMD state where they will accept
+ * command requests. 0x80-0xbf loads the eeprom data.  We then
+ * read the port 16 times and with every read; the cards check
+ * for contention (ie: if one card writes a 0 bit and another
+ * writes a 1 bit then the host sees a 0. At the end of the cycle;
+ * each card compares the data on the bus; if there is a difference
+ * then that card goes into ID_WAIT state again). In the meantime;
+ * one bit of data is returned in the AX register which is conveniently
+ * returned to us by inb().  Hence; we read 16 times getting one
+ * bit of data with each read.
+ */
+u_short
+epreadeeprom(id_port, offset)
+	int     id_port;
+	int     offset;
+{
+	int i, data = 0;
+
+	outb(id_port, 0x80 + offset);
+	delay(1000);
+	for (i = 0; i < 16; i++)
+		data = (data << 1) | (inw(id_port) & 1);
+	return (data);
+}
+
+static int
+epbusyeeprom(sc)
+	struct ep_softc *sc;
+{
+	int i = 100, j;
+
+	if (sc->bustype == EP_BUS_PCMCIA) {
+		delay(1000);
+		return 0;
+	}
+
+	while (i--) {
+		j = inw(BASE + EP_W0_EEPROM_COMMAND);
+		if (j & EEPROM_BUSY)
+			delay(100);
+		else
+			break;
+	}
+	if (!i) {
+		printf("\n%s: eeprom failed to come ready\n",
+		    sc->sc_dev.dv_xname);
+		return (1);
+	}
+	if (j & EEPROM_TST_MODE) {
+		printf("\n%s: erase pencil mark, or disable plug-n-play mode!\n",
+		    sc->sc_dev.dv_xname);
+		return (1);
+	}
+	return (0);
+}
+
+void
+epmbuffill(sc)
+	struct ep_softc *sc;
+{
+	int s, i;
+
+	s = splnet();
+	i = sc->last_mb;
+	do {
+		if (sc->mb[i] == NULL)
+			MGET(sc->mb[i], M_DONTWAIT, MT_DATA);
+		if (sc->mb[i] == NULL)
+			break;
+		i = (i + 1) % MAX_MBS;
+	} while (i != sc->next_mb);
+	sc->last_mb = i;
+	/* If the queue was not filled, try again. */
+	if (sc->last_mb != sc->next_mb)
+		timeout(epmbuffill, sc, 1);
+	splx(s);
+}
+
+void
+epmbufempty(sc)
+	struct ep_softc *sc;
+{
+	int s, i;
+
+	s = splnet();
+	for (i = 0; i<MAX_MBS; i++) {
+		if (sc->mb[i]) {
+			m_freem(sc->mb[i]);
+			sc->mb[i] = NULL;
+		}
+	}
+	sc->last_mb = sc->next_mb = 0;
+	untimeout(epmbuffill, sc);
+	splx(s);
+}
diff --git a/sys/dev/ic/elink3reg.h b/sys/dev/ic/elink3reg.h
new file mode 100644
index 00000000000..a125013030e
--- /dev/null
+++ b/sys/dev/ic/elink3reg.h
@@ -0,0 +1,338 @@
+/*	$NetBSD: elink3reg.h,v 1.1 1996/04/25 02:17:35 thorpej Exp $	*/
+
+/*
+ * Copyright (c) 1995 Herb Peyerl <hpeyerl@novatel.ca>
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. All advertising materials mentioning features or use of this software
+ *    must display the following acknowledgement:
+ *      This product includes software developed by Herb Peyerl.
+ * 4. The name of Herb Peyerl may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+/*
+ * These define the EEPROM data structure.  They are used in the probe
+ * function to verify the existance of the adapter after having sent
+ * the ID_Sequence.
+ *
+ * There are others but only the ones we use are defined here.
+ */
+#define EEPROM_NODE_ADDR_0	0x0	/* Word */
+#define EEPROM_NODE_ADDR_1	0x1	/* Word */
+#define EEPROM_NODE_ADDR_2	0x2	/* Word */
+#define EEPROM_PROD_ID		0x3	/* 0x9[0-f]50 */
+#define EEPROM_MFG_ID		0x7	/* 0x6d50 */
+#define EEPROM_ADDR_CFG		0x8	/* Base addr */
+#define EEPROM_RESOURCE_CFG	0x9     /* IRQ. Bits 12-15 */
+
+/*
+ * These are the registers for the 3Com 3c509 and their bit patterns when
+ * applicable.  They have been taken out the the "EtherLink III Parallel
+ * Tasking EISA and ISA Technical Reference" "Beta Draft 10/30/92" manual
+ * from 3com.
+ */
+#define EP_COMMAND		0x0e    /* Write. BASE+0x0e is always a command reg. */
+#define EP_STATUS		0x0e    /* Read. BASE+0x0e is always status reg. */
+#define EP_WINDOW		0x0f    /* Read. BASE+0x0f is always window reg. */
+
+/*
+ * Window 0 registers. Setup.
+ */
+	/* Write */
+#define EP_W0_EEPROM_DATA	0x0c
+#define EP_W0_EEPROM_COMMAND	0x0a
+#define EP_W0_RESOURCE_CFG	0x08
+#define EP_W0_ADDRESS_CFG	0x06
+#define EP_W0_CONFIG_CTRL	0x04
+	/* Read */
+#define EP_W0_PRODUCT_ID	0x02
+#define EP_W0_MFG_ID		0x00
+
+/*
+ * Window 1 registers. Operating Set.
+ */
+	/* Write */
+#define EP_W1_TX_PIO_WR_2	0x02
+#define EP_W1_TX_PIO_WR_1	0x00
+	/* Read */
+#define EP_W1_FREE_TX		0x0c
+#define EP_W1_TX_STATUS		0x0b    /* byte */
+#define EP_W1_TIMER		0x0a    /* byte */
+#define EP_W1_RX_STATUS		0x08
+#define EP_W1_RX_PIO_RD_2	0x02
+#define EP_W1_RX_PIO_RD_1	0x00
+
+/*
+ * Window 2 registers. Station Address Setup/Read
+ */
+	/* Read/Write */
+#define EP_W2_ADDR_5		0x05
+#define EP_W2_ADDR_4		0x04
+#define EP_W2_ADDR_3		0x03
+#define EP_W2_ADDR_2		0x02
+#define EP_W2_ADDR_1		0x01
+#define EP_W2_ADDR_0		0x00
+
+/* 
+ * Window 3 registers.  FIFO Management.
+ */
+	/* Read */
+#define EP_W3_FREE_TX		0x0c
+#define EP_W3_FREE_RX		0x0a
+
+/*
+ * Window 4 registers. Diagnostics.
+ */
+	/* Read/Write */
+#define EP_W4_MEDIA_TYPE	0x0a
+#define EP_W4_CTRLR_STATUS	0x08
+#define EP_W4_NET_DIAG		0x06
+#define EP_W4_FIFO_DIAG		0x04
+#define EP_W4_HOST_DIAG		0x02
+#define EP_W4_TX_DIAG		0x00
+
+/*
+ * Window 5 Registers.  Results and Internal status.
+ */
+	/* Read */
+#define EP_W5_READ_0_MASK	0x0c
+#define EP_W5_INTR_MASK		0x0a
+#define EP_W5_RX_FILTER		0x08
+#define EP_W5_RX_EARLY_THRESH	0x06
+#define EP_W5_TX_AVAIL_THRESH	0x02
+#define EP_W5_TX_START_THRESH	0x00
+
+/*
+ * Window 6 registers. Statistics.
+ */
+	/* Read/Write */
+#define TX_TOTAL_OK		0x0c
+#define RX_TOTAL_OK		0x0a
+#define TX_DEFERRALS		0x08
+#define RX_FRAMES_OK		0x07
+#define TX_FRAMES_OK		0x06
+#define RX_OVERRUNS		0x05
+#define TX_COLLISIONS		0x04
+#define TX_AFTER_1_COLLISION	0x03
+#define TX_AFTER_X_COLLISIONS	0x02
+#define TX_NO_SQE		0x01
+#define TX_CD_LOST		0x00
+
+/*
+ * Register definitions.
+ */
+
+/*
+ * Command register. All windows.
+ *
+ * 16 bit register.
+ *     15-11:  5-bit code for command to be executed.
+ *     10-0:   11-bit arg if any. For commands with no args;
+ *	      this can be set to anything.
+ */
+#define GLOBAL_RESET		(u_short) 0x0000   /* Wait at least 1ms after issuing */
+#define WINDOW_SELECT		(u_short) (0x1<<11)
+#define START_TRANSCEIVER	(u_short) (0x2<<11) /* Read ADDR_CFG reg to determine
+						      whether this is needed. If so;
+						      wait 800 uSec before using trans-
+						      ceiver. */
+#define RX_DISABLE		(u_short) (0x3<<11) /* state disabled on power-up */
+#define RX_ENABLE		(u_short) (0x4<<11)
+#define RX_RESET		(u_short) (0x5<<11)
+#define RX_DISCARD_TOP_PACK	(u_short) (0x8<<11)
+#define TX_ENABLE		(u_short) (0x9<<11)
+#define TX_DISABLE		(u_short) (0xa<<11)
+#define TX_RESET		(u_short) (0xb<<11)
+#define REQ_INTR		(u_short) (0xc<<11)
+
+/*
+ * The following C_* acknowledge the various interrupts.
+ * Some of them don't do anything.  See the manual.
+ */
+#define ACK_INTR		(u_short) (0x6800)
+#      define C_INTR_LATCH	(u_short) (ACK_INTR|0x01)
+#      define C_CARD_FAILURE	(u_short) (ACK_INTR|0x02)
+#      define C_TX_COMPLETE	(u_short) (ACK_INTR|0x04)
+#      define C_TX_AVAIL	(u_short) (ACK_INTR|0x08)
+#      define C_RX_COMPLETE	(u_short) (ACK_INTR|0x10)
+#      define C_RX_EARLY	(u_short) (ACK_INTR|0x20)
+#      define C_INT_RQD		(u_short) (ACK_INTR|0x40)
+#      define C_UPD_STATS	(u_short) (ACK_INTR|0x80)
+#define SET_INTR_MASK		(u_short) (0x0e<<11)
+#define SET_RD_0_MASK		(u_short) (0x0f<<11)
+#define SET_RX_FILTER		(u_short) (0x10<<11)
+#      define FIL_INDIVIDUAL	(u_short) (0x01)
+#      define FIL_MULTICAST	(u_short) (0x02)
+#      define FIL_BRDCST	(u_short) (0x04)
+#      define FIL_PROMISC	(u_short) (0x08)
+#define SET_RX_EARLY_THRESH	(u_short) (0x11<<11)
+#define SET_TX_AVAIL_THRESH	(u_short) (0x12<<11)
+#define SET_TX_START_THRESH	(u_short) (0x13<<11)
+#define STATS_ENABLE		(u_short) (0x15<<11)
+#define STATS_DISABLE		(u_short) (0x16<<11)
+#define STOP_TRANSCEIVER	(u_short) (0x17<<11)
+
+/*
+ * Status register. All windows.
+ *
+ *     15-13:  Window number(0-7).
+ *     12:     Command_in_progress.
+ *     11:     reserved.
+ *     10:     reserved.
+ *     9:      reserved.
+ *     8:      reserved.
+ *     7:      Update Statistics.
+ *     6:      Interrupt Requested.
+ *     5:      RX Early.
+ *     4:      RX Complete.
+ *     3:      TX Available.
+ *     2:      TX Complete.
+ *     1:      Adapter Failure.
+ *     0:      Interrupt Latch.
+ */
+#define S_INTR_LATCH		(u_short) (0x0001)
+#define S_CARD_FAILURE		(u_short) (0x0002)
+#define S_TX_COMPLETE		(u_short) (0x0004)
+#define S_TX_AVAIL		(u_short) (0x0008)
+#define S_RX_COMPLETE		(u_short) (0x0010)
+#define S_RX_EARLY		(u_short) (0x0020)
+#define S_INT_RQD		(u_short) (0x0040)
+#define S_UPD_STATS		(u_short) (0x0080)
+#define S_COMMAND_IN_PROGRESS	(u_short) (0x1000)
+
+/*
+ * FIFO Registers.  RX Status.
+ *
+ *     15:     Incomplete or FIFO empty.
+ *     14:     1: Error in RX Packet   0: Incomplete or no error.
+ *     14-11:  Type of error. [14-11]
+ *	      1000 = Overrun.
+ *	      1011 = Run Packet Error.
+ *	      1100 = Alignment Error.
+ *	      1101 = CRC Error.
+ *	      1001 = Oversize Packet Error (>1514 bytes)
+ *	      0010 = Dribble Bits.
+ *	      (all other error codes, no errors.)
+ *
+ *     10-0:   RX Bytes (0-1514)
+ */
+#define ERR_INCOMPLETE  (u_short) (0x8000)
+#define ERR_RX		(u_short) (0x4000)
+#define ERR_MASK	(u_short) (0x7800)
+#define ERR_OVERRUN	(u_short) (0x4000)
+#define ERR_RUNT	(u_short) (0x5800)
+#define ERR_ALIGNMENT	(u_short) (0x6000)
+#define ERR_CRC		(u_short) (0x6800)
+#define ERR_OVERSIZE	(u_short) (0x4800)
+#define ERR_DRIBBLE	(u_short) (0x1000)
+
+/*
+ * TX Status
+ *
+ *   Reports the transmit status of a completed transmission. Writing this
+ *   register pops the transmit completion stack.
+ *
+ *   Window 1/Port 0x0b.
+ *
+ *     7:      Complete
+ *     6:      Interrupt on successful transmission requested.
+ *     5:      Jabber Error (TP Only, TX Reset required. )
+ *     4:      Underrun (TX Reset required. )
+ *     3:      Maximum Collisions.
+ *     2:      TX Status Overflow.
+ *     1-0:    Undefined.
+ *
+ */
+#define TXS_COMPLETE		0x80
+#define TXS_INTR_REQ		0x40
+#define TXS_JABBER		0x20
+#define TXS_UNDERRUN		0x10
+#define TXS_MAX_COLLISION	0x08
+#define TXS_STATUS_OVERFLOW	0x04
+
+/*
+ * FIFO Status (Window 4)
+ *
+ *   Supports FIFO diagnostics
+ *
+ *   Window 4/Port 0x04.1
+ *
+ *     15:	1=RX receiving (RO). Set when a packet is being received
+ *		into the RX FIFO.
+ *     14:	Reserved
+ *     13:	1=RX underrun (RO). Generates Adapter Failure interrupt.
+ *		Requires RX Reset or Global Reset command to recover.
+ *		It is generated when you read past the end of a packet -
+ *		reading past what has been received so far will give bad
+ *		data.
+ *     12:	1=RX status overrun (RO). Set when there are already 8
+ *		packets in the RX FIFO. While this bit is set, no additional
+ *		packets are received. Requires no action on the part of
+ *		the host. The condition is cleared once a packet has been
+ *		read out of the RX FIFO.
+ *     11:	1=RX overrun (RO). Set when the RX FIFO is full (there
+ *		may not be an overrun packet yet). While this bit is set,
+ *		no additional packets will be received (some additional
+ *		bytes can still be pending between the wire and the RX
+ *		FIFO). Requires no action on the part of the host. The
+ *		condition is cleared once a few bytes have been read out
+ *		from the RX FIFO.
+ *     10:	1=TX overrun (RO). Generates adapter failure interrupt.
+ *		Requires TX Reset or Global Reset command to recover.
+ *		Disables Transmitter.
+ *     9-8:	Unassigned.
+ *     7-0:	Built in self test bits for the RX and TX FIFO's.
+ */
+#define	FIFOS_RX_RECEIVING	(u_short) 0x8000
+#define	FIFOS_RX_UNDERRUN	(u_short) 0x2000
+#define	FIFOS_RX_STATUS_OVERRUN	(u_short) 0x1000
+#define	FIFOS_RX_OVERRUN	(u_short) 0x0800
+#define	FIFOS_TX_OVERRUN	(u_short) 0x0400
+
+/*
+ * Misc defines for various things.
+ */
+#define TAG_ADAPTER 			0xd0
+#define ACTIVATE_ADAPTER_TO_CONFIG 	0xff
+#define ENABLE_DRQ_IRQ			0x0001
+#define MFG_ID				0x506d	/* `TCM' */
+#define PROD_ID				0x5090
+#define BASE 				sc->ep_iobase
+#define GO_WINDOW(x) 			outw(BASE+EP_COMMAND, WINDOW_SELECT|x)
+#define AUI 				0x1
+#define BNC 				0x2
+#define UTP 				0x4
+#define IS_AUI 				(1<<13)
+#define IS_BNC 				(1<<12)
+#define IS_UTP 				(1<<9)
+#define EEPROM_BUSY			(1<<15)
+#define EEPROM_TST_MODE			(1<<14)
+#define READ_EEPROM			(1<<7)
+#define ENABLE_UTP			0xc0
+#define DISABLE_UTP			0x0
+#define RX_BYTES_MASK			(u_short) (0x07ff)
+
+#define IS_PCI_AUI 			(1<<5)
+#define IS_PCI_BNC 			(1<<4)
+#define IS_PCI_UTP 			(1<<3)
diff --git a/sys/dev/ic/elink3var.h b/sys/dev/ic/elink3var.h
new file mode 100644
index 00000000000..c87e412e061
--- /dev/null
+++ b/sys/dev/ic/elink3var.h
@@ -0,0 +1,61 @@
+/*	$NetBSD: elink3var.h,v 1.1 1996/04/25 02:17:36 thorpej Exp $	*/
+
+/*
+ * Copyright (c) 1994 Herb Peyerl <hpeyerl@novatel.ca>
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. All advertising materials mentioning features or use of this software
+ *    must display the following acknowledgement:
+ *      This product includes software developed by Herb Peyerl.
+ * 4. The name of Herb Peyerl may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/*
+ * Ethernet software status per interface.
+ */
+struct ep_softc {
+	struct device sc_dev;
+	void *sc_ih;
+
+	struct arpcom sc_arpcom;	/* Ethernet common part		*/
+	int	ep_iobase;		/* i/o bus address		*/
+	char    ep_connectors;		/* Connectors on this card.	*/
+#define MAX_MBS	8			/* # of mbufs we keep around	*/
+	struct mbuf *mb[MAX_MBS];	/* spare mbuf storage.		*/
+	int	next_mb;		/* Which mbuf to use next. 	*/
+	int	last_mb;		/* Last mbuf.			*/
+	int	tx_start_thresh;	/* Current TX_start_thresh.	*/
+	int	tx_succ_ok;		/* # packets sent in sequence   */
+					/* w/o underrun			*/
+	u_char	bustype;
+#define EP_BUS_ISA	  	0x0
+#define	EP_BUS_PCMCIA	  	0x1
+#define	EP_BUS_EISA	  	0x2
+#define EP_BUS_PCI	  	0x3
+
+#define EP_IS_BUS_32(a)	((a) & 0x2)
+};
+
+u_short	epreadeeprom __P((int id_port, int offset));
+void	epconfig __P((struct ep_softc *, u_int));
+int	epintr __P((void *));