Remove the IEEE80211_NO_HT macro. Reduces ifdef spaghetti, enables 11n mode

in bsd.rd, and might uncover some bugs. Suggested by tedu@ and deraadt@.
ok sthen@ jasper@ deraadt@

15 files changed, 20 insertions, 133 deletions

diff --git a/sys/dev/ic/ar5008.c b/sys/dev/ic/ar5008.c
index 6818e4421e6..d3ad6c9f298 100644
--- a/sys/dev/ic/ar5008.c
+++ b/sys/dev/ic/ar5008.c
@@ -1,4 +1,4 @@
-/*	$OpenBSD: ar5008.c,v 1.34 2015/11/25 03:09:58 dlg Exp $	*/
+/*	$OpenBSD: ar5008.c,v 1.35 2016/01/05 18:41:15 stsp Exp $	*/
 
 /*-
  * Copyright (c) 2009 Damien Bergamini <damien.bergamini@free.fr>
@@ -1521,7 +1521,6 @@ ar5008_tx(struct athn_softc *sc, struct mbuf *m, struct ieee80211_node *ni,
 	    SM(AR_TXC7_CHAIN_SEL2, sc->txchainmask) |
 	    SM(AR_TXC7_CHAIN_SEL3, sc->txchainmask);
 #ifdef notyet
-#ifndef IEEE80211_NO_HT
 	/* Use the same short GI setting for all tries. */
 	if (ic->ic_flags & IEEE80211_F_SHGI)
 		ds->ds_ctl7 |= AR_TXC7_GI0123;
@@ -1529,7 +1528,6 @@ ar5008_tx(struct athn_softc *sc, struct mbuf *m, struct ieee80211_node *ni,
 	if (ic->ic_flags & IEEE80211_F_CBW40)
 		ds->ds_ctl7 |= AR_TXC7_2040_0123;
 #endif
-#endif
 
 	if (ds->ds_ctl0 & (AR_TXC0_RTS_ENABLE | AR_TXC0_CTS_ENABLE)) {
 		uint8_t protridx, hwrate;
@@ -1671,13 +1669,11 @@ ar5008_set_phy(struct athn_softc *sc, struct ieee80211_channel *c,
 		phy = 0;
 	phy |= AR_PHY_FC_HT_EN | AR_PHY_FC_SHORT_GI_40 |
 	    AR_PHY_FC_SINGLE_HT_LTF1 | AR_PHY_FC_WALSH;
-#ifndef IEEE80211_NO_HT
 	if (extc != NULL) {
 		phy |= AR_PHY_FC_DYN2040_EN;
 		if (extc > c)	/* XXX */
 			phy |= AR_PHY_FC_DYN2040_PRI_CH;
 	}
-#endif
 	AR_WRITE(sc, AR_PHY_TURBO, phy);
 
 	AR_WRITE(sc, AR_2040_MODE,
@@ -2129,7 +2125,6 @@ ar5008_write_txpower(struct athn_softc *sc, int16_t power[ATHN_POWER_COUNT])
 	    (power[ATHN_POWER_CCK11_LP] & 0x3f) << 16 |
 	    (power[ATHN_POWER_CCK55_SP] & 0x3f) <<  8 |
 	    (power[ATHN_POWER_CCK55_LP] & 0x3f));
-#ifndef IEEE80211_NO_HT
 	AR_WRITE(sc, AR_PHY_POWER_TX_RATE5,
 	    (power[ATHN_POWER_HT20(3) ] & 0x3f) << 24 |
 	    (power[ATHN_POWER_HT20(2) ] & 0x3f) << 16 |
@@ -2155,7 +2150,6 @@ ar5008_write_txpower(struct athn_softc *sc, int16_t power[ATHN_POWER_COUNT])
 	    (power[ATHN_POWER_CCK_EXT ] & 0x3f) << 16 |
 	    (power[ATHN_POWER_OFDM_DUP] & 0x3f) <<  8 |
 	    (power[ATHN_POWER_CCK_DUP ] & 0x3f));
-#endif
 	AR_WRITE_BARRIER(sc);
 }
 
@@ -2281,15 +2275,12 @@ ar5008_hw_init(struct athn_softc *sc, struct ieee80211_channel *c,
 	AR_WRITE(sc, AR_PHY_ADC_SERIAL_CTL, AR_PHY_SEL_INTERNAL_ADDAC);
 
 	/* First initialization step (depends on channel band/bandwidth). */
-#ifndef IEEE80211_NO_HT
 	if (extc != NULL) {
 		if (IEEE80211_IS_CHAN_2GHZ(c))
 			pvals = ini->vals_2g40;
 		else
 			pvals = ini->vals_5g40;
-	} else
-#endif
-	{
+	} else {
 		if (IEEE80211_IS_CHAN_2GHZ(c))
 			pvals = ini->vals_2g20;
 		else
@@ -2343,11 +2334,9 @@ ar5008_hw_init(struct athn_softc *sc, struct ieee80211_channel *c,
 	if (IEEE80211_IS_CHAN_5GHZ(c) &&
 	    (sc->flags & ATHN_FLAG_FAST_PLL_CLOCK)) {
 		/* Update modal values for fast PLL clock. */
-#ifndef IEEE80211_NO_HT
 		if (extc != NULL)
 			pvals = ini->fastvals_5g40;
 		else
-#endif
 			pvals = ini->fastvals_5g20;
 		DPRINTFN(4, ("writing fast pll clock init vals\n"));
 		for (i = 0; i < ini->nfastregs; i++) {
@@ -2564,7 +2553,6 @@ ar5008_get_lg_tpow(struct athn_softc *sc, struct ieee80211_channel *c,
 	/* XXX Apply conformance testing limit. */
 }
 
-#ifndef IEEE80211_NO_HT
 void
 ar5008_get_ht_tpow(struct athn_softc *sc, struct ieee80211_channel *c,
     uint8_t ctl, const struct ar_cal_target_power_ht *tgt, int nchans,
@@ -2595,7 +2583,6 @@ ar5008_get_ht_tpow(struct athn_softc *sc, struct ieee80211_channel *c,
 	}
 	/* XXX Apply conformance testing limit. */
 }
-#endif
 
 /*
  * Adaptive noise immunity.
diff --git a/sys/dev/ic/ar5416.c b/sys/dev/ic/ar5416.c
index 58fd39a804d..de79dd917f5 100644
--- a/sys/dev/ic/ar5416.c
+++ b/sys/dev/ic/ar5416.c
@@ -1,4 +1,4 @@
-/*	$OpenBSD: ar5416.c,v 1.18 2015/11/24 17:11:39 mpi Exp $	*/
+/*	$OpenBSD: ar5416.c,v 1.19 2016/01/05 18:41:15 stsp Exp $	*/
 
 /*-
  * Copyright (c) 2009 Damien Bergamini <damien.bergamini@free.fr>
@@ -319,14 +319,12 @@ ar5416_init_from_rom(struct athn_softc *sc, struct ieee80211_channel *c,
 		reg = RW(reg, AR_PHY_TX_END_PA_ON, modal->txFrameToPaOn);
 		AR_WRITE(sc, AR_PHY_RF_CTL2, reg);
 	}
-#ifndef IEEE80211_NO_HT
 	if (sc->eep_rev >= AR_EEP_MINOR_VER_3 && extc != NULL) {
 		/* Overwrite switch settling with HT-40 value. */
 		reg = AR_READ(sc, AR_PHY_SETTLING);
 		reg = RW(reg, AR_PHY_SETTLING_SWITCH, modal->swSettleHt40);
 		AR_WRITE(sc, AR_PHY_SETTLING, reg);
 	}
-#endif
 }
 
 int
@@ -527,11 +525,9 @@ ar5416_set_txpower(struct athn_softc *sc, struct ieee80211_channel *c,
 	const struct ar5416_eeprom *eep = sc->eep;
 	const struct ar5416_modal_eep_header *modal;
 	uint8_t tpow_cck[4], tpow_ofdm[4];
-#ifndef IEEE80211_NO_HT
 	uint8_t tpow_cck_ext[4], tpow_ofdm_ext[4];
 	uint8_t tpow_ht20[8], tpow_ht40[8];
 	uint8_t ht40inc;
-#endif
 	int16_t pwr = 0, pwroff, max_ant_gain, power[ATHN_POWER_COUNT];
 	uint8_t cckinc;
 	int i;
@@ -565,7 +561,6 @@ ar5416_set_txpower(struct athn_softc *sc, struct ieee80211_channel *c,
 		ar5008_get_lg_tpow(sc, c, AR_CTL_11G, eep->calTargetPower2G,
 		    AR5416_NUM_2G_20_TARGET_POWERS, tpow_ofdm);
 
-#ifndef IEEE80211_NO_HT
 		/* Get HT-20 target powers. */
 		ar5008_get_ht_tpow(sc, c, AR_CTL_2GHT20,
 		    eep->calTargetPower2GHT20, AR5416_NUM_2G_20_TARGET_POWERS,
@@ -587,13 +582,11 @@ ar5416_set_txpower(struct athn_softc *sc, struct ieee80211_channel *c,
 			    eep->calTargetPower2G,
 			    AR5416_NUM_2G_20_TARGET_POWERS, tpow_ofdm_ext);
 		}
-#endif
 	} else {
 		/* Get OFDM target powers. */
 		ar5008_get_lg_tpow(sc, c, AR_CTL_11A, eep->calTargetPower5G,
 		    AR5416_NUM_5G_20_TARGET_POWERS, tpow_ofdm);
 
-#ifndef IEEE80211_NO_HT
 		/* Get HT-20 target powers. */
 		ar5008_get_ht_tpow(sc, c, AR_CTL_5GHT20,
 		    eep->calTargetPower5GHT20, AR5416_NUM_5G_20_TARGET_POWERS,
@@ -610,7 +603,6 @@ ar5416_set_txpower(struct athn_softc *sc, struct ieee80211_channel *c,
 			    eep->calTargetPower5G,
 			    AR5416_NUM_5G_20_TARGET_POWERS, tpow_ofdm_ext);
 		}
-#endif
 	}
 
 	/* Compute CCK/OFDM delta. */
@@ -636,7 +628,6 @@ ar5416_set_txpower(struct athn_softc *sc, struct ieee80211_channel *c,
 		power[ATHN_POWER_CCK11_LP] =
 		power[ATHN_POWER_CCK11_SP] = tpow_cck[3] + cckinc;
 	}
-#ifndef IEEE80211_NO_HT
 	for (i = 0; i < nitems(tpow_ht20); i++)
 		power[ATHN_POWER_HT20(i)] = tpow_ht20[i];
 	if (extc != NULL) {
@@ -653,7 +644,6 @@ ar5416_set_txpower(struct athn_softc *sc, struct ieee80211_channel *c,
 		if (IEEE80211_IS_CHAN_2GHZ(c))
 			power[ATHN_POWER_CCK_EXT] = tpow_cck_ext[0] + cckinc;
 	}
-#endif
 
 	if (AR_SREV_9280_10_OR_LATER(sc)) {
 		if (sc->eep_rev >= AR_EEP_MINOR_VER_21)
diff --git a/sys/dev/ic/ar5416reg.h b/sys/dev/ic/ar5416reg.h
index e4b4b383d6f..826d8078f34 100644
--- a/sys/dev/ic/ar5416reg.h
+++ b/sys/dev/ic/ar5416reg.h
@@ -1,4 +1,4 @@
-/*	$OpenBSD: ar5416reg.h,v 1.5 2012/10/20 09:54:20 stsp Exp $	*/
+/*	$OpenBSD: ar5416reg.h,v 1.6 2016/01/05 18:41:15 stsp Exp $	*/
 
 /*-
  * Copyright (c) 2009 Damien Bergamini <damien.bergamini@free.fr>
@@ -206,7 +206,6 @@ static const uint32_t ar5416_vals_5g20[] = {
 	0x00000000, 0x00000000, 0x00000000
 };
 
-#ifndef IEEE80211_NO_HT
 static const uint32_t ar5416_vals_5g40[] = {
 	0x00000460, 0x000002d0, 0x00001cc0, 0x00014000, 0x07d007d0,
 	0x128d93cf, 0x08f04800, 0x00003210, 0x000003c4, 0x02020200,
@@ -238,7 +237,6 @@ static const uint32_t ar5416_vals_2g40[] = {
 	0x950f8ccf, 0xa5cf9b4f, 0xbddfaf1f, 0xd1ffc93f, 0x00000000,
 	0x00000000, 0x00000000, 0x00000000
 };
-#endif
 
 static const uint32_t ar5416_vals_2g20[] = {
 	0x00000160, 0x0000018c, 0x00003e38, 0x0000b000, 0x08400b00,
@@ -416,10 +414,8 @@ static const struct athn_ini ar5416_ini = {
 	nitems(ar5416_regs),
 	ar5416_regs,
 	ar5416_vals_5g20,
-#ifndef IEEE80211_NO_HT
 	ar5416_vals_5g40,
 	ar5416_vals_2g40,
-#endif
 	ar5416_vals_2g20,
 	nitems(ar5416_cm_regs),
 	ar5416_cm_regs,
@@ -461,7 +457,6 @@ static const uint32_t ar9160_vals_5g20[] = {
 	0x0000d7bf, 0x00000000, 0x00000000, 0x00000000
 };
 
-#ifndef IEEE80211_NO_HT
 static const uint32_t ar9160_vals_5g40[] = {
 	0x00000460, 0x000002d0, 0x00001cc0, 0x00014000, 0x07d007d0,
 	0x128d93cf, 0x08f04800, 0x00003210, 0x000003c4, 0x02020200,
@@ -493,7 +488,6 @@ static const uint32_t ar9160_vals_2g40[] = {
 	0x845b7a5a, 0x950f8ccf, 0xa5cf9b4f, 0xbddfaf1f, 0xd1ffc93f,
 	0x00000000, 0x00000000, 0x00000000, 0x00000000
 };
-#endif
 
 static const uint32_t ar9160_vals_2g20[] = {
 	0x00000160, 0x0000018c, 0x00003e38, 0x0000b000, 0x08400b00,
@@ -671,10 +665,8 @@ static const struct athn_ini ar9160_ini = {
 	nitems(ar9160_regs),
 	ar9160_regs,
 	ar9160_vals_5g20,
-#ifndef IEEE80211_NO_HT
 	ar9160_vals_5g40,
 	ar9160_vals_2g40,
-#endif
 	ar9160_vals_2g20,
 	nitems(ar9160_cm_regs),
 	ar9160_cm_regs,
diff --git a/sys/dev/ic/ar9003.c b/sys/dev/ic/ar9003.c
index d987c8dee44..8a1965ef39c 100644
--- a/sys/dev/ic/ar9003.c
+++ b/sys/dev/ic/ar9003.c
@@ -1,4 +1,4 @@
-/*	$OpenBSD: ar9003.c,v 1.38 2015/11/25 03:09:58 dlg Exp $	*/
+/*	$OpenBSD: ar9003.c,v 1.39 2016/01/05 18:41:15 stsp Exp $	*/
 
 /*-
  * Copyright (c) 2010 Damien Bergamini <damien.bergamini@free.fr>
@@ -1689,7 +1689,6 @@ ar9003_tx(struct athn_softc *sc, struct mbuf *m, struct ieee80211_node *ni,
 		    SM(AR_TXC18_CHAIN_SEL3, sc->txchainmask);
 	}
 #ifdef notyet
-#ifndef IEEE80211_NO_HT
 	/* Use the same short GI setting for all tries. */
 	if (ic->ic_flags & IEEE80211_F_SHGI)
 		ds->ds_ctl18 |= AR_TXC18_GI0123;
@@ -1697,7 +1696,6 @@ ar9003_tx(struct athn_softc *sc, struct mbuf *m, struct ieee80211_node *ni,
 	if (ic->ic_flags & IEEE80211_F_CBW40)
 		ds->ds_ctl18 |= AR_TXC18_2040_0123;
 #endif
-#endif
 
 	if (ds->ds_ctl11 & (AR_TXC11_RTS_ENABLE | AR_TXC11_CTS_ENABLE)) {
 		uint8_t protridx, hwrate;
@@ -1831,13 +1829,11 @@ ar9003_set_phy(struct athn_softc *sc, struct ieee80211_channel *c,
 	phy = AR_READ(sc, AR_PHY_GEN_CTRL);
 	phy |= AR_PHY_GC_HT_EN | AR_PHY_GC_SHORT_GI_40 |
 	    AR_PHY_GC_SINGLE_HT_LTF1 | AR_PHY_GC_WALSH;
-#ifndef IEEE80211_NO_HT
 	if (extc != NULL) {
 		phy |= AR_PHY_GC_DYN2040_EN;
 		if (extc > c)	/* XXX */
 			phy |= AR_PHY_GC_DYN2040_PRI_CH;
 	}
-#endif
 	/* Turn off Green Field detection for now. */
 	phy &= ~AR_PHY_GC_GF_DETECT_EN;
 	AR_WRITE(sc, AR_PHY_GEN_CTRL, phy);
@@ -3025,7 +3021,6 @@ ar9003_write_txpower(struct athn_softc *sc, int16_t power[ATHN_POWER_COUNT])
 	    (power[ATHN_POWER_HT20( 4)] & 0x3f) << 16 |
 	    (power[ATHN_POWER_HT20( 1)] & 0x3f) <<  8 |
 	    (power[ATHN_POWER_HT20( 0)] & 0x3f));
-#ifndef IEEE80211_NO_HT
 	AR_WRITE(sc, AR_PHY_PWRTX_RATE6,
 	    (power[ATHN_POWER_HT20(13)] & 0x3f) << 24 |
 	    (power[ATHN_POWER_HT20(12)] & 0x3f) << 16 |
@@ -3056,7 +3051,6 @@ ar9003_write_txpower(struct athn_softc *sc, int16_t power[ATHN_POWER_COUNT])
 	    (power[ATHN_POWER_HT40(20)] & 0x3f) << 16 |
 	    (power[ATHN_POWER_HT40(15)] & 0x3f) <<  8 |
 	    (power[ATHN_POWER_HT40(14)] & 0x3f));
-#endif
 	AR_WRITE_BARRIER(sc);
 }
 
@@ -3124,15 +3118,12 @@ ar9003_hw_init(struct athn_softc *sc, struct ieee80211_channel *c,
 	 * The modal init values include the post phase for the SoC, MAC,
 	 * BB and Radio subsystems.
 	 */
-#ifndef IEEE80211_NO_HT
 	if (extc != NULL) {
 		if (IEEE80211_IS_CHAN_2GHZ(c))
 			pvals = ini->vals_2g40;
 		else
 			pvals = ini->vals_5g40;
-	} else
-#endif
-	{
+	} else {
 		if (IEEE80211_IS_CHAN_2GHZ(c))
 			pvals = ini->vals_2g20;
 		else
@@ -3155,11 +3146,9 @@ ar9003_hw_init(struct athn_softc *sc, struct ieee80211_channel *c,
 	if (IEEE80211_IS_CHAN_5GHZ(c) &&
 	    (sc->flags & ATHN_FLAG_FAST_PLL_CLOCK)) {
 		/* Update modal values for fast PLL clock. */
-#ifndef IEEE80211_NO_HT
 		if (extc != NULL)
 			pvals = ini->fastvals_5g40;
 		else
-#endif
 			pvals = ini->fastvals_5g20;
 		DPRINTFN(4, ("writing fast pll clock init vals\n"));
 		for (i = 0; i < ini->nfastregs; i++) {
diff --git a/sys/dev/ic/ar9280.c b/sys/dev/ic/ar9280.c
index ca5fda95413..55366961bff 100644
--- a/sys/dev/ic/ar9280.c
+++ b/sys/dev/ic/ar9280.c
@@ -1,4 +1,4 @@
-/*	$OpenBSD: ar9280.c,v 1.24 2015/11/24 17:11:39 mpi Exp $	*/
+/*	$OpenBSD: ar9280.c,v 1.25 2016/01/05 18:41:15 stsp Exp $	*/
 
 /*-
  * Copyright (c) 2009 Damien Bergamini <damien.bergamini@free.fr>
@@ -373,14 +373,12 @@ ar9280_init_from_rom(struct athn_softc *sc, struct ieee80211_channel *c,
 		reg = RW(reg, AR_PHY_TX_END_PA_ON, modal->txFrameToPaOn);
 		AR_WRITE(sc, AR_PHY_RF_CTL2, reg);
 	}
-#ifndef IEEE80211_NO_HT
 	if (sc->eep_rev >= AR_EEP_MINOR_VER_3 && extc != NULL) {
 		/* Overwrite switch settling with HT-40 value. */
 		reg = AR_READ(sc, AR_PHY_SETTLING);
 		reg = RW(reg, AR_PHY_SETTLING_SWITCH, modal->swSettleHt40);
 		AR_WRITE(sc, AR_PHY_SETTLING, reg);
 	}
-#endif
 	if (sc->eep_rev >= AR_EEP_MINOR_VER_19) {
 		reg = AR_READ(sc, AR_PHY_CCK_TX_CTRL);
 		reg = RW(reg, AR_PHY_CCK_TX_CTRL_TX_DAC_SCALE_CCK,
@@ -504,7 +502,6 @@ ar9280_spur_mitigate(struct athn_softc *sc, struct ieee80211_channel *c,
 	    AR_PHY_SPUR_REG_ENABLE_VIT_SPUR_RSSI |
 	    SM(AR_PHY_SPUR_REG_SPUR_RSSI_THRESH, AR_SPUR_RSSI_THRESH));
 
-#ifndef IEEE80211_NO_HT
 	if (extc != NULL) {
 		spur_delta_phase = (spur * 262144) / 10;
 		if (spur < 0) {
@@ -514,9 +511,7 @@ ar9280_spur_mitigate(struct athn_softc *sc, struct ieee80211_channel *c,
 			spur_subchannel_sd = 0;
 			spur_off = spur - 10;
 		}
-	} else
-#endif
-	{
+	} else {
 		spur_delta_phase = (spur * 524288) / 10;
 		spur_subchannel_sd = 0;
 		spur_off = spur;
diff --git a/sys/dev/ic/ar9280reg.h b/sys/dev/ic/ar9280reg.h
index 6bb15d6ca9f..a7753ad5dc0 100644
--- a/sys/dev/ic/ar9280reg.h
+++ b/sys/dev/ic/ar9280reg.h
@@ -1,4 +1,4 @@
-/*	$OpenBSD: ar9280reg.h,v 1.6 2012/10/20 09:54:20 stsp Exp $	*/
+/*	$OpenBSD: ar9280reg.h,v 1.7 2016/01/05 18:41:15 stsp Exp $	*/
 
 /*-
  * Copyright (c) 2009 Damien Bergamini <damien.bergamini@free.fr>
@@ -66,7 +66,6 @@ static const uint32_t ar9280_2_0_vals_5g20[] = {
 	0x5a508000
 };
 
-#ifndef IEEE80211_NO_HT
 static const uint32_t ar9280_2_0_vals_5g40[] = {
 	0x00000460, 0x000002d0, 0x00001cc0, 0x00000000, 0x07d007d0,
 	0x128d804f, 0x08f04800, 0x00003210, 0x00007d00, 0x000003c4,
@@ -92,7 +91,6 @@ static const uint32_t ar9280_2_0_vals_2g40[] = {
 	0x13c88001, 0x0004a000, 0x7999aa0e, 0x08000000, 0x00000000,
 	0x5a508000
 };
-#endif
 
 static const uint32_t ar9280_2_0_vals_2g20[] = {
 	0x00000160, 0x0000018c, 0x00003e38, 0x00000000, 0x08400b00,
@@ -261,22 +259,18 @@ static const uint32_t ar9280_2_0_fast_clock_vals_5g20[] = {
 	0x03721821, 0x00000898, 0x0000000b
 };
 
-#ifndef IEEE80211_NO_HT
 static const uint32_t ar9280_2_0_fast_clock_vals_5g40[] = {
 	0x000004d0, 0x00000318, 0x00001fa0, 0x08980898, 0x148ec057,
 	0x00008980, 0x02020200, 0x01000f0f, 0x0b020001, 0x00000f0f,
 	0x03721821, 0x00001130, 0x00000016
 };
-#endif
 
 static const struct athn_ini ar9280_2_0_ini = {
 	nitems(ar9280_2_0_regs),
 	ar9280_2_0_regs,
 	ar9280_2_0_vals_5g20,
-#ifndef IEEE80211_NO_HT
 	ar9280_2_0_vals_5g40,
 	ar9280_2_0_vals_2g40,
-#endif
 	ar9280_2_0_vals_2g20,
 	nitems(ar9280_2_0_cm_regs),
 	ar9280_2_0_cm_regs,
@@ -284,9 +278,7 @@ static const struct athn_ini ar9280_2_0_ini = {
 	nitems(ar9280_2_0_fast_clock_regs),
 	ar9280_2_0_fast_clock_regs,
 	ar9280_2_0_fast_clock_vals_5g20,
-#ifndef IEEE80211_NO_HT
 	ar9280_2_0_fast_clock_vals_5g40
-#endif
 };
 
 /*
diff --git a/sys/dev/ic/ar9285.c b/sys/dev/ic/ar9285.c
index d9b252f968d..9e379236e53 100644
--- a/sys/dev/ic/ar9285.c
+++ b/sys/dev/ic/ar9285.c
@@ -1,4 +1,4 @@
-/*	$OpenBSD: ar9285.c,v 1.25 2015/11/24 17:11:39 mpi Exp $	*/
+/*	$OpenBSD: ar9285.c,v 1.26 2016/01/05 18:41:15 stsp Exp $	*/
 
 /*-
  * Copyright (c) 2009-2010 Damien Bergamini <damien.bergamini@free.fr>
@@ -386,13 +386,11 @@ ar9285_init_from_rom(struct athn_softc *sc, struct ieee80211_channel *c,
 		    modal->txFrameToDataStart);
 		AR_WRITE(sc, AR_PHY_RF_CTL2, reg);
 	}
-#ifndef IEEE80211_NO_HT
 	if (sc->eep_rev >= AR_EEP_MINOR_VER_3 && extc != NULL) {
 		reg = AR_READ(sc, AR_PHY_SETTLING);
 		reg = RW(reg, AR_PHY_SETTLING_SWITCH, modal->swSettleHt40);
 		AR_WRITE(sc, AR_PHY_SETTLING, reg);
 	}
-#endif
 	AR_WRITE_BARRIER(sc);
 }
 
@@ -590,7 +588,6 @@ ar9285_cl_cal(struct athn_softc *sc, struct ieee80211_channel *c,
 	int ntries;
 
 	AR_SETBITS(sc, AR_PHY_CL_CAL_CTL, AR_PHY_CL_CAL_ENABLE);
-#ifndef IEEE80211_NO_HT
 	if (0 && extc == NULL) {	/* XXX IS_CHAN_HT20!! */
 		AR_SETBITS(sc, AR_PHY_CL_CAL_CTL, AR_PHY_PARALLEL_CAL_ENABLE);
 		AR_SETBITS(sc, AR_PHY_TURBO, AR_PHY_FC_DYN2040_EN);
@@ -610,7 +607,6 @@ ar9285_cl_cal(struct athn_softc *sc, struct ieee80211_channel *c,
 		AR_CLRBITS(sc, AR_PHY_CL_CAL_CTL, AR_PHY_PARALLEL_CAL_ENABLE);
 		AR_CLRBITS(sc, AR_PHY_CL_CAL_CTL, AR_PHY_CL_CAL_ENABLE);
 	}
-#endif
 	AR_CLRBITS(sc, AR_PHY_ADC_CTL, AR_PHY_ADC_CTL_OFF_PWDADC);
 	AR_SETBITS(sc, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_FLTR_CAL);
 	AR_SETBITS(sc, AR_PHY_TPCRG1, AR_PHY_TPCRG1_PD_CAL_ENABLE);
@@ -792,11 +788,9 @@ ar9285_set_txpower(struct athn_softc *sc, struct ieee80211_channel *c,
 	const struct ar9285_eeprom *eep = sc->eep;
 	const struct ar9285_modal_eep_header *modal = &eep->modalHeader;
 	uint8_t tpow_cck[4], tpow_ofdm[4];
-#ifndef IEEE80211_NO_HT
 	uint8_t tpow_cck_ext[4], tpow_ofdm_ext[4];
 	uint8_t tpow_ht20[8], tpow_ht40[8];
 	uint8_t ht40inc;
-#endif
 	int16_t max_ant_gain, power[ATHN_POWER_COUNT];
 	int i;
 
@@ -814,7 +808,6 @@ ar9285_set_txpower(struct athn_softc *sc, struct ieee80211_channel *c,
 	ar5008_get_lg_tpow(sc, c, AR_CTL_11G, eep->calTargetPower2G,
 	    AR9285_NUM_2G_20_TARGET_POWERS, tpow_ofdm);
 
-#ifndef IEEE80211_NO_HT
 	/* Get HT-20 target powers. */
 	ar5008_get_ht_tpow(sc, c, AR_CTL_2GHT20, eep->calTargetPower2GHT20,
 	    AR9285_NUM_2G_20_TARGET_POWERS, tpow_ht20);
@@ -835,7 +828,6 @@ ar9285_set_txpower(struct athn_softc *sc, struct ieee80211_channel *c,
 		    eep->calTargetPower2G, AR9285_NUM_2G_20_TARGET_POWERS,
 		    tpow_ofdm_ext);
 	}
-#endif
 
 	memset(power, 0, sizeof(power));
 	/* Shuffle target powers accross transmit rates. */
@@ -855,7 +847,6 @@ ar9285_set_txpower(struct athn_softc *sc, struct ieee80211_channel *c,
 	power[ATHN_POWER_CCK55_SP] = tpow_cck[2];
 	power[ATHN_POWER_CCK11_LP] =
 	power[ATHN_POWER_CCK11_SP] = tpow_cck[3];
-#ifndef IEEE80211_NO_HT
 	for (i = 0; i < nitems(tpow_ht20); i++)
 		power[ATHN_POWER_HT20(i)] = tpow_ht20[i];
 	if (extc != NULL) {
@@ -871,7 +862,6 @@ ar9285_set_txpower(struct athn_softc *sc, struct ieee80211_channel *c,
 		power[ATHN_POWER_OFDM_EXT] = tpow_ofdm_ext[0];
 		power[ATHN_POWER_CCK_EXT ] = tpow_cck_ext[0];
 	}
-#endif
 
 	for (i = 0; i < ATHN_POWER_COUNT; i++) {
 		power[i] -= AR_PWR_TABLE_OFFSET_DB * 2;	/* In half dB. */
diff --git a/sys/dev/ic/ar9285reg.h b/sys/dev/ic/ar9285reg.h
index 708e3772180..0a11b9fbf85 100644
--- a/sys/dev/ic/ar9285reg.h
+++ b/sys/dev/ic/ar9285reg.h
@@ -1,4 +1,4 @@
-/*	$OpenBSD: ar9285reg.h,v 1.7 2011/01/06 07:27:15 damien Exp $	*/
+/*	$OpenBSD: ar9285reg.h,v 1.8 2016/01/05 18:41:15 stsp Exp $	*/
 
 /*-
  * Copyright (c) 2009 Damien Bergamini <damien.bergamini@free.fr>
@@ -321,7 +321,6 @@ static const uint16_t ar9285_1_2_regs[] = {
 	P(0x0a250), P(0x0a358)
 };
 
-#ifndef IEEE80211_NO_HT
 static const uint32_t ar9285_1_2_vals_2g40[] = {
 	0x000002c0, 0x00000318, 0x00007c70, 0x00000000, 0x10801600,
 	0x12e00057, 0x00006880, 0x000003c4, 0x02020200, 0x01000e0e,
@@ -385,7 +384,6 @@ static const uint32_t ar9285_1_2_vals_2g40[] = {
 	0x00000004, 0x0001f000, 0x0001f000, 0x1883800a, 0x00000210,
 	0x0004a000, 0x7999aa0e
 };
-#endif
 
 static const uint32_t ar9285_1_2_vals_2g20[] = {
 	0x00000160, 0x0000018c, 0x00003e38, 0x00000000, 0x08400b00,
@@ -589,10 +587,8 @@ static const struct athn_ini ar9285_1_2_ini = {
 	nitems(ar9285_1_2_regs),
 	ar9285_1_2_regs,
 	NULL,	/* 2GHz only. */
-#ifndef IEEE80211_NO_HT
 	NULL,	/* 2GHz only. */
 	ar9285_1_2_vals_2g40,
-#endif
 	ar9285_1_2_vals_2g20,
 	nitems(ar9285_1_2_cm_regs),
 	ar9285_1_2_cm_regs,
@@ -667,7 +663,6 @@ static const uint16_t ar9271_regs[] = {
 	P(0x0a230), P(0x0a250), P(0x0a358)
 };
 
-#ifndef IEEE80211_NO_HT
 static const uint32_t ar9271_vals_2g40[] = {
 	0x000002c0, 0x00000318, 0x00007c70, 0x00000000, 0x10801600,
 	0x12e00057, 0x00006880, 0x000003c4, 0x02020200, 0x01000e0e,
@@ -731,7 +726,6 @@ static const uint32_t ar9271_vals_2g40[] = {
 	0x000eb7db, 0x00000004, 0x0001f000, 0x0001f000, 0x1883800a,
 	0x00000210, 0x0004a000, 0x7999aa0e
 };
-#endif
 
 static const uint32_t ar9271_vals_2g20[] = {
 	0x00000160, 0x0000018c, 0x00003e38, 0x00000000, 0x08400b00,
@@ -937,10 +931,8 @@ static const struct athn_ini ar9271_ini = {
 	nitems(ar9271_regs),
 	ar9271_regs,
 	NULL,	/* 2GHz only. */
-#ifndef IEEE80211_NO_HT
 	NULL,	/* 2GHz only. */
 	ar9271_vals_2g40,
-#endif
 	ar9271_vals_2g20,
 	nitems(ar9271_cm_regs),
 	ar9271_cm_regs,
diff --git a/sys/dev/ic/ar9287.c b/sys/dev/ic/ar9287.c
index f75052c9e96..2bb331501fd 100644
--- a/sys/dev/ic/ar9287.c
+++ b/sys/dev/ic/ar9287.c
@@ -1,4 +1,4 @@
-/*	$OpenBSD: ar9287.c,v 1.23 2015/11/24 17:11:39 mpi Exp $	*/
+/*	$OpenBSD: ar9287.c,v 1.24 2016/01/05 18:41:15 stsp Exp $	*/
 
 /*-
  * Copyright (c) 2009 Damien Bergamini <damien.bergamini@free.fr>
@@ -201,11 +201,9 @@ ar9287_init_from_rom(struct athn_softc *sc, struct ieee80211_channel *c,
 	}
 
 	reg = AR_READ(sc, AR_PHY_SETTLING);
-#ifndef IEEE80211_NO_HT
 	if (extc != NULL)
 		reg = RW(reg, AR_PHY_SETTLING_SWITCH, modal->swSettleHt40);
 	else
-#endif
 		reg = RW(reg, AR_PHY_SETTLING_SWITCH, modal->switchSettling);
 	AR_WRITE(sc, AR_PHY_SETTLING, reg);
 
@@ -440,11 +438,9 @@ ar9287_set_txpower(struct athn_softc *sc, struct ieee80211_channel *c,
 	const struct ar9287_eeprom *eep = sc->eep;
 	const struct ar9287_modal_eep_header *modal = &eep->modalHeader;
 	uint8_t tpow_cck[4], tpow_ofdm[4];
-#ifndef IEEE80211_NO_HT
 	uint8_t tpow_cck_ext[4], tpow_ofdm_ext[4];
 	uint8_t tpow_ht20[8], tpow_ht40[8];
 	uint8_t ht40inc;
-#endif
 	int16_t pwr = 0, max_ant_gain, power[ATHN_POWER_COUNT];
 	int i;
 
@@ -471,7 +467,6 @@ ar9287_set_txpower(struct athn_softc *sc, struct ieee80211_channel *c,
 	ar5008_get_lg_tpow(sc, c, AR_CTL_11G, eep->calTargetPower2G,
 	    AR9287_NUM_2G_20_TARGET_POWERS, tpow_ofdm);
 
-#ifndef IEEE80211_NO_HT
 	/* Get HT-20 target powers. */
 	ar5008_get_ht_tpow(sc, c, AR_CTL_2GHT20, eep->calTargetPower2GHT20,
 	    AR9287_NUM_2G_20_TARGET_POWERS, tpow_ht20);
@@ -492,7 +487,6 @@ ar9287_set_txpower(struct athn_softc *sc, struct ieee80211_channel *c,
 		    eep->calTargetPower2G, AR9287_NUM_2G_20_TARGET_POWERS,
 		    tpow_ofdm_ext);
 	}
-#endif
 
 	memset(power, 0, sizeof(power));
 	/* Shuffle target powers accross transmit rates. */
@@ -512,7 +506,6 @@ ar9287_set_txpower(struct athn_softc *sc, struct ieee80211_channel *c,
 	power[ATHN_POWER_CCK55_SP] = tpow_cck[2];
 	power[ATHN_POWER_CCK11_LP] =
 	power[ATHN_POWER_CCK11_SP] = tpow_cck[3];
-#ifndef IEEE80211_NO_HT
 	for (i = 0; i < nitems(tpow_ht20); i++)
 		power[ATHN_POWER_HT20(i)] = tpow_ht20[i];
 	if (extc != NULL) {
@@ -529,7 +522,6 @@ ar9287_set_txpower(struct athn_softc *sc, struct ieee80211_channel *c,
 		if (IEEE80211_IS_CHAN_2GHZ(c))
 			power[ATHN_POWER_CCK_EXT] = tpow_cck_ext[0];
 	}
-#endif
 
 	for (i = 0; i < ATHN_POWER_COUNT; i++) {
 		power[i] -= AR_PWR_TABLE_OFFSET_DB * 2;	/* In half dB. */
diff --git a/sys/dev/ic/ar9287reg.h b/sys/dev/ic/ar9287reg.h
index f72586a29c1..d00f8fd6458 100644
--- a/sys/dev/ic/ar9287reg.h
+++ b/sys/dev/ic/ar9287reg.h
@@ -1,4 +1,4 @@
-/*	$OpenBSD: ar9287reg.h,v 1.3 2010/07/15 19:07:43 damien Exp $	*/
+/*	$OpenBSD: ar9287reg.h,v 1.4 2016/01/05 18:41:15 stsp Exp $	*/
 
 /*-
  * Copyright (c) 2009 Damien Bergamini <damien.bergamini@free.fr>
@@ -186,7 +186,6 @@ static const uint16_t ar9287_1_1_regs[] = {
 	P(0x0a250), P(0x0a358), P(0x0a3d8)
 };
 
-#ifndef IEEE80211_NO_HT
 static const uint32_t ar9287_1_1_vals_2g40[] = {
 	0x000002c0, 0x00000318, 0x00007c70, 0x00000000, 0x10801600,
 	0x12e00057, 0x08f04810, 0x0000320a, 0x00006880, 0x000003c4,
@@ -198,7 +197,6 @@ static const uint32_t ar9287_1_1_vals_2g40[] = {
 	0x00000444, 0x00000000, 0x00000000, 0x1883800a, 0x00000210,
 	0x0004a000, 0x7999aa0e, 0x00000000
 };
-#endif
 
 static const uint32_t ar9287_1_1_vals_2g20[] = {
 	0x00000160, 0x0000018c, 0x00003e38, 0x00000000, 0x08400b00,
@@ -368,10 +366,8 @@ static const struct athn_ini ar9287_1_1_ini = {
 	nitems(ar9287_1_1_regs),
 	ar9287_1_1_regs,
 	NULL,	/* 2GHz only. */
-#ifndef IEEE80211_NO_HT
 	NULL,	/* 2GHz only. */
 	ar9287_1_1_vals_2g40,
-#endif
 	ar9287_1_1_vals_2g20,
 	nitems(ar9287_1_1_cm_regs),
 	ar9287_1_1_cm_regs,
diff --git a/sys/dev/ic/ar9380.c b/sys/dev/ic/ar9380.c
index ff211a0cfd2..cb6a115713f 100644
--- a/sys/dev/ic/ar9380.c
+++ b/sys/dev/ic/ar9380.c
@@ -1,4 +1,4 @@
-/*	$OpenBSD: ar9380.c,v 1.23 2015/11/24 17:11:39 mpi Exp $	*/
+/*	$OpenBSD: ar9380.c,v 1.24 2016/01/05 18:41:15 stsp Exp $	*/
 
 /*-
  * Copyright (c) 2011 Damien Bergamini <damien.bergamini@free.fr>
@@ -582,7 +582,6 @@ ar9380_spur_mitigate_ofdm(struct athn_softc *sc, struct ieee80211_channel *c,
 	AR_WRITE_BARRIER(sc);
 
 	freq = c->ic_freq;
-#ifndef IEEE80211_NO_HT
 	if (extc != NULL) {
 		range = 19;	/* +/- 19MHz range. */
 		if (AR_READ(sc, AR_PHY_GEN_CTRL) & AR_PHY_GC_DYN2040_PRI_CH)
@@ -590,7 +589,6 @@ ar9380_spur_mitigate_ofdm(struct athn_softc *sc, struct ieee80211_channel *c,
 		else
 			freq -= 10;
 	} else
-#endif
 		range = 10;	/* +/- 10MHz range. */
 	for (i = 0; i < AR9380_EEPROM_MODAL_SPURS; i++) {
 		spur = spurchans[i];
@@ -609,7 +607,6 @@ ar9380_spur_mitigate_ofdm(struct athn_softc *sc, struct ieee80211_channel *c,
 		return;
 
 	/* Enable OFDM spur mitigation. */
-#ifndef IEEE80211_NO_HT
 	if (extc != NULL) {
 		spur_delta_phase = (spur * 131072) / 5;
 		reg = AR_READ(sc, AR_PHY_GEN_CTRL);
@@ -622,9 +619,7 @@ ar9380_spur_mitigate_ofdm(struct athn_softc *sc, struct ieee80211_channel *c,
 			    (reg & AR_PHY_GC_DYN2040_PRI_CH) != 0;
 			spur_off = spur - 10;
 		}
-	} else
-#endif
-	{
+	} else {
 		spur_delta_phase = (spur * 262144) / 5;
 		spur_subchannel_sd = 0;
 		spur_off = spur;
diff --git a/sys/dev/ic/ar9380reg.h b/sys/dev/ic/ar9380reg.h
index 4389ec2b8e9..c9625ccfb22 100644
--- a/sys/dev/ic/ar9380reg.h
+++ b/sys/dev/ic/ar9380reg.h
@@ -1,4 +1,4 @@
-/*	$OpenBSD: ar9380reg.h,v 1.20 2013/10/21 16:12:41 stsp Exp $	*/
+/*	$OpenBSD: ar9380reg.h,v 1.21 2016/01/05 18:41:15 stsp Exp $	*/
 
 /*-
  * Copyright (c) 2010 Damien Bergamini <damien.bergamini@free.fr>
@@ -828,7 +828,6 @@ static const uint32_t ar9380_2_2_vals_5g20[] = {
 	0x001c0000, 0x00000000, 0x0000019c, 0x000001b5, 0x00000000
 };
 
-#ifndef IEEE80211_NO_HT
 static const uint32_t ar9380_2_2_vals_5g40[] = {
 	0x00000023, 0x00000460, 0x000002d0, 0x00001cc0, 0x07d007d0,
 	0x128d804f, 0x08f04800, 0x00003210, 0x00007d00, 0x0dd08f29,
@@ -862,7 +861,6 @@ static const uint32_t ar9380_2_2_vals_2g40[] = {
 	0x00000000, 0x0000019c, 0x000001ce, 0x00000150, 0x0000019c,
 	0x001c0000, 0x00000000, 0x0000019c, 0x000001ce, 0x00000150
 };
-#endif
 
 static const uint32_t ar9380_2_2_vals_2g20[] = {
 	0x00000023, 0x00000160, 0x0000018c, 0x00003e38, 0x08400b00,
@@ -1081,21 +1079,17 @@ static const uint32_t ar9380_2_2_fast_clock_vals_5g20[] = {
 	0x000044c0, 0x0372131c, 0x0000000b, 0x00000898
 };
 
-#ifndef IEEE80211_NO_HT
 static const uint32_t ar9380_2_2_fast_clock_vals_5g40[] = {
 	0x000004d0, 0x00000318, 0x00001fa0, 0x08980898, 0x148ec057,
 	0x00008980, 0x0372131c, 0x00000016, 0x00001130
 };
-#endif
 
 static const struct athn_ini ar9380_2_2_ini = {
 	nitems(ar9380_2_2_regs),
 	ar9380_2_2_regs,
 	ar9380_2_2_vals_5g20,
-#ifndef IEEE80211_NO_HT
 	ar9380_2_2_vals_5g40,
 	ar9380_2_2_vals_2g40,
-#endif
 	ar9380_2_2_vals_2g20,
 	nitems(ar9380_2_2_cm_regs),
 	ar9380_2_2_cm_regs,
@@ -1103,9 +1097,7 @@ static const struct athn_ini ar9380_2_2_ini = {
 	nitems(ar9380_2_2_fast_clock_regs),
 	ar9380_2_2_fast_clock_regs,
 	ar9380_2_2_fast_clock_vals_5g20,
-#ifndef IEEE80211_NO_HT
 	ar9380_2_2_fast_clock_vals_5g40
-#endif
 };
 
 /*
@@ -1316,10 +1308,8 @@ static const struct athn_ini ar9485_1_1_ini = {
 	nitems(ar9485_1_1_regs),
 	ar9485_1_1_regs,
 	NULL,	/* 2GHz only. */
-#ifndef IEEE80211_NO_HT
 	NULL,	/* 2GHz only. */
 	ar9485_1_1_vals_2g40,
-#endif
 	ar9485_1_1_vals_2g20,
 	nitems(ar9485_1_1_cm_regs),
 	ar9485_1_1_cm_regs,
diff --git a/sys/dev/ic/athn.c b/sys/dev/ic/athn.c
index 51cfed88adf..03460ef830e 100644
--- a/sys/dev/ic/athn.c
+++ b/sys/dev/ic/athn.c
@@ -1,4 +1,4 @@
-/*	$OpenBSD: athn.c,v 1.91 2015/12/03 14:39:37 stsp Exp $	*/
+/*	$OpenBSD: athn.c,v 1.92 2016/01/05 18:41:15 stsp Exp $	*/
 
 /*-
  * Copyright (c) 2009 Damien Bergamini <damien.bergamini@free.fr>
@@ -285,7 +285,6 @@ athn_attach(struct athn_softc *sc)
 	    IEEE80211_C_SHPREAMBLE |	/* Short preamble supported. */
 	    IEEE80211_C_PMGT;		/* Power saving supported. */
 
-#ifndef IEEE80211_NO_HT
 	if (sc->flags & ATHN_FLAG_11N) {
 		int i, ntxstreams, nrxstreams;
 
@@ -318,7 +317,6 @@ athn_attach(struct athn_softc *sc)
 			ic->ic_tx_mcs_set |= (ntxstreams - 1) << 2;
 		}
 	}
-#endif
 
 	/* Set supported rates. */
 	if (sc->flags & ATHN_FLAG_11G) {
@@ -451,10 +449,8 @@ athn_rx_start(struct athn_softc *sc)
 
 	/* Set Rx filter. */
 	rfilt = AR_RX_FILTER_UCAST | AR_RX_FILTER_BCAST | AR_RX_FILTER_MCAST;
-#ifndef IEEE80211_NO_HT
 	/* Want Compressed Block Ack Requests. */
 	rfilt |= AR_RX_FILTER_COMPR_BAR;
-#endif
 	rfilt |= AR_RX_FILTER_BEACON;
 	if (ic->ic_opmode != IEEE80211_M_STA) {
 		rfilt |= AR_RX_FILTER_PROBEREQ;
@@ -2511,10 +2507,9 @@ athn_clock_rate(struct athn_softc *sc)
 		clockrate = AR_CLOCK_RATE_CCK;
 	} else
 		clockrate = AR_CLOCK_RATE_2GHZ_OFDM;
-#ifndef IEEE80211_NO_HT
 	if (sc->curchanext != NULL)
 		clockrate *= 2;
-#endif
+
 	return (clockrate);
 }
 
diff --git a/sys/dev/ic/athnvar.h b/sys/dev/ic/athnvar.h
index c8982e7254b..6073413c8f1 100644
--- a/sys/dev/ic/athnvar.h
+++ b/sys/dev/ic/athnvar.h
@@ -1,4 +1,4 @@
-/*	$OpenBSD: athnvar.h,v 1.35 2013/12/06 21:03:02 deraadt Exp $	*/
+/*	$OpenBSD: athnvar.h,v 1.36 2016/01/05 18:41:15 stsp Exp $	*/
 
 /*-
  * Copyright (c) 2009 Damien Bergamini <damien.bergamini@free.fr>
@@ -178,10 +178,8 @@ struct athn_ini {
 	int		nregs;
 	const uint16_t	*regs;
 	const uint32_t	*vals_5g20;
-#ifndef IEEE80211_NO_HT
 	const uint32_t	*vals_5g40;
 	const uint32_t	*vals_2g40;
-#endif
 	const uint32_t	*vals_2g20;
 	int		ncmregs;
 	const uint16_t	*cmregs;
@@ -189,9 +187,7 @@ struct athn_ini {
 	int		nfastregs;
 	const uint16_t	*fastregs;
 	const uint32_t	*fastvals_5g20;
-#ifndef IEEE80211_NO_HT
 	const uint32_t	*fastvals_5g40;
-#endif
 };
 
 struct athn_gain {
diff --git a/sys/dev/ic/rt2860.c b/sys/dev/ic/rt2860.c
index 71f79efa6f4..d1524ac3241 100644
--- a/sys/dev/ic/rt2860.c
+++ b/sys/dev/ic/rt2860.c
@@ -1,4 +1,4 @@
-/*	$OpenBSD: rt2860.c,v 1.86 2015/12/11 16:07:01 mpi Exp $	*/
+/*	$OpenBSD: rt2860.c,v 1.87 2016/01/05 18:41:15 stsp Exp $	*/
 
 /*-
  * Copyright (c) 2007-2010 Damien Bergamini <damien.bergamini@free.fr>
@@ -345,10 +345,8 @@ rt2860_attachhook(struct device *self)
 #ifndef IEEE80211_STA_ONLY
 	ic->ic_node_leave = rt2860_node_leave;
 #endif
-#ifndef IEEE80211_NO_HT
 	ic->ic_ampdu_rx_start = rt2860_ampdu_rx_start;
 	ic->ic_ampdu_rx_stop = rt2860_ampdu_rx_stop;
-#endif
 	ic->ic_updateslot = rt2860_updateslot;
 	ic->ic_updateedca = rt2860_updateedca;
 	ic->ic_set_key = rt2860_set_key;
@@ -875,7 +873,6 @@ rt2860_node_leave(struct ieee80211com *ic, struct ieee80211_node *ni)
 }
 #endif
 
-#ifndef IEEE80211_NO_HT
 int
 rt2860_ampdu_rx_start(struct ieee80211com *ic, struct ieee80211_node *ni,
     uint8_t tid)
@@ -904,7 +901,6 @@ rt2860_ampdu_rx_stop(struct ieee80211com *ic, struct ieee80211_node *ni,
 	tmp &= ~((1 << tid) << 16);
 	RAL_WRITE(sc, RT2860_WCID_ENTRY(wcid) + 4, tmp);
 }
-#endif
 
 int
 rt2860_newstate(struct ieee80211com *ic, enum ieee80211_state nstate, int arg)