bye bye unportable bitfields

7 files changed, 637 insertions, 469 deletions

diff --git a/sys/dev/ic/ar5210.c b/sys/dev/ic/ar5210.c
index 23f620d6998..5cb4fb91896 100644
--- a/sys/dev/ic/ar5210.c
+++ b/sys/dev/ic/ar5210.c
@@ -1,4 +1,4 @@
-/*     $OpenBSD: ar5210.c,v 1.17 2005/04/06 09:14:53 reyk Exp $        */
+/*     $OpenBSD: ar5210.c,v 1.18 2005/04/08 22:02:49 reyk Exp $        */
 
 /*
  * Copyright (c) 2004, 2005 Reyk Floeter <reyk@vantronix.net>
@@ -1004,6 +1004,7 @@ ar5k_ar5210_setupTxDesc(hal, desc, packet_length, header_length, type, tx_power,
 	u_int rtscts_rate;
 	u_int rtscts_duration;
 {
+	u_int32_t frame_type;
 	struct ar5k_ar5210_tx_desc *tx_desc;
 
 	tx_desc = (struct ar5k_ar5210_tx_desc*)&desc->ds_ctl0;
@@ -1017,58 +1018,54 @@ ar5k_ar5210_setupTxDesc(hal, desc, packet_length, header_length, type, tx_power,
 	if (tx_tries0 == 0)
 		return (AH_FALSE);
 
-	switch (type) {
-	case HAL_PKT_TYPE_NORMAL:
-		tx_desc->frame_type = AR5K_AR5210_DESC_TX_FRAME_TYPE_NORMAL;
-		break;
-
-	case HAL_PKT_TYPE_ATIM:
-		tx_desc->frame_type = AR5K_AR5210_DESC_TX_FRAME_TYPE_ATIM;
-		break;
-
-	case HAL_PKT_TYPE_PSPOLL:
-		tx_desc->frame_type = AR5K_AR5210_DESC_TX_FRAME_TYPE_PSPOLL;
-		break;
-
-	case HAL_PKT_TYPE_BEACON:
-	case HAL_PKT_TYPE_PROBE_RESP:
-		tx_desc->frame_type = AR5K_AR5210_DESC_TX_FRAME_TYPE_NO_DELAY;
-		break;
-
-	case HAL_PKT_TYPE_PIFS:
-		tx_desc->frame_type = AR5K_AR5210_DESC_TX_FRAME_TYPE_PIFS;
-		break;
-
-	default:
-		/* Invalid packet type (possibly not supported) */
+	if ((tx_desc->tx_control_0 = (packet_length &
+	    AR5K_AR5210_DESC_TX_CTL0_FRAME_LEN)) != packet_length)
 		return (AH_FALSE);
-	}
 
-	if ((tx_desc->frame_len = packet_length) != packet_length)
+	if ((tx_desc->tx_control_0 = (header_length &
+	    AR5K_AR5210_DESC_TX_CTL0_HEADER_LEN)) != header_length)
 		return (AH_FALSE);
 
-	if ((tx_desc->header_len = header_length) != header_length)
-		return (AH_FALSE);
+	if (type == HAL_PKT_TYPE_BEACON || type == HAL_PKT_TYPE_PROBE_RESP)
+		frame_type = AR5K_AR5210_DESC_TX_FRAME_TYPE_NO_DELAY;
+	else if (type == HAL_PKT_TYPE_PIFS)
+		frame_type = AR5K_AR5210_DESC_TX_FRAME_TYPE_PIFS;
+	else
+		frame_type = type;
+	
+	tx_desc->tx_control_0 =
+	    AR5K_REG_SM(frame_type, AR5K_AR5210_DESC_TX_CTL0_FRAME_TYPE);
+	tx_desc->tx_control_0 |=
+	    AR5K_REG_SM(tx_rate0, AR5K_AR5210_DESC_TX_CTL0_XMIT_RATE);
 
-	tx_desc->xmit_rate = tx_rate0;
-	tx_desc->ant_mode_xmit = antenna_mode ? 1 : 0;
-	tx_desc->clear_dest_mask = flags & HAL_TXDESC_CLRDMASK ? 1 : 0;
-	tx_desc->inter_req = flags & HAL_TXDESC_INTREQ ? 1 : 0;
+#define _TX_FLAGS(_c, _flag)	 					\
+	if (flags & HAL_TXDESC_##_flag)					\
+		tx_desc->tx_control_##_c |=    				\
+			AR5K_AR5210_DESC_TX_CTL##_c##_##_flag
+
+	_TX_FLAGS(0, CLRDMASK);
+	_TX_FLAGS(0, INTREQ);
+	_TX_FLAGS(0, RTSENA);
+
+#undef _TX_FLAGS
 
 	/*
 	 * WEP crap
 	 */
 	if (key_index != HAL_TXKEYIX_INVALID) {
-		tx_desc->encrypt_key_valid = 1;
-		tx_desc->encrypt_key_index = key_index;
+		tx_desc->tx_control_0 |=
+		    AR5K_AR5210_DESC_TX_CTL0_ENCRYPT_KEY_VALID;
+		tx_desc->tx_control_1 |=
+		    AR5K_REG_SM(key_index,
+		    AR5K_AR5210_DESC_TX_CTL1_ENCRYPT_KEY_INDEX);
 	}
 
 	/*
 	 * RTS/CTS
 	 */
 	if (flags & (HAL_TXDESC_RTSENA | HAL_TXDESC_CTSENA)) {
-		tx_desc->rts_cts_enable = 1;
-		tx_desc->rts_duration = rtscts_duration;
+		tx_desc->tx_control_1 |=
+		    rtscts_duration & AR5K_AR5210_DESC_TX_CTL1_RTS_DURATION;
 	}
 
 	return (AH_TRUE);
@@ -1090,13 +1087,15 @@ ar5k_ar5210_fillTxDesc(hal, desc, segment_length, first_segment, last_segment)
 	bzero(desc->ds_hw, sizeof(desc->ds_hw));
 
 	/* Validate segment length and initialize the descriptor */
-	if ((tx_desc->buf_len = segment_length) != segment_length)
+	if ((tx_desc->tx_control_1 = (segment_length &
+	    AR5K_AR5210_DESC_TX_CTL1_BUF_LEN)) != segment_length)
 		return (AH_FALSE);
 
 	if (first_segment != AH_TRUE)
-		tx_desc->frame_len = 0;
+		tx_desc->tx_control_0 &= ~AR5K_AR5210_DESC_TX_CTL0_FRAME_LEN;
 
-	tx_desc->more = last_segment == AH_TRUE ? 0 : 1;
+	if (last_segment != AH_TRUE)
+		tx_desc->tx_control_1 |= AR5K_AR5210_DESC_TX_CTL1_MORE;
 
 	return (AH_TRUE);
 }
@@ -1133,38 +1132,47 @@ ar5k_ar5210_procTxDesc(hal, desc)
 	tx_status = (struct ar5k_ar5210_tx_status*)&desc->ds_hw[0];
 
 	/* No frame has been send or error */
-	if (tx_status->done == 0)
+	if ((tx_status->tx_status_1 & AR5K_AR5210_DESC_TX_STATUS1_DONE) == 0)
 		return (HAL_EINPROGRESS);
 
 	/*
 	 * Get descriptor status
 	 */
-	desc->ds_us.tx.ts_seqnum = tx_status->seq_num;
-	desc->ds_us.tx.ts_tstamp = tx_status->send_timestamp;
-	desc->ds_us.tx.ts_shortretry = tx_status->short_retry_count;
-	desc->ds_us.tx.ts_longretry = tx_status->long_retry_count;
-	desc->ds_us.tx.ts_rssi = tx_status->ack_sig_strength;
-	desc->ds_us.tx.ts_rate = tx_desc->xmit_rate;
-	desc->ds_us.tx.ts_antenna = 0;
+	desc->ds_us.tx.ts_tstamp =
+	    AR5K_REG_MS(tx_status->tx_status_0,
+	    AR5K_AR5210_DESC_TX_STATUS0_SEND_TIMESTAMP);
+	desc->ds_us.tx.ts_shortretry =
+	    AR5K_REG_MS(tx_status->tx_status_0,
+	    AR5K_AR5210_DESC_TX_STATUS0_SHORT_RETRY_COUNT);
+	desc->ds_us.tx.ts_longretry =
+	    AR5K_REG_MS(tx_status->tx_status_0,
+	    AR5K_AR5210_DESC_TX_STATUS0_LONG_RETRY_COUNT);
+	desc->ds_us.tx.ts_seqnum =
+	    AR5K_REG_MS(tx_status->tx_status_1,
+	    AR5K_AR5210_DESC_TX_STATUS1_SEQ_NUM);
+	desc->ds_us.tx.ts_rssi =
+	    AR5K_REG_MS(tx_status->tx_status_1,
+	    AR5K_AR5210_DESC_TX_STATUS1_ACK_SIG_STRENGTH);
+	desc->ds_us.tx.ts_antenna = 1;
 	desc->ds_us.tx.ts_status = 0;
-
-	if (tx_status->frame_xmit_ok == 0) {
-		if (tx_status->excessive_retries)
+	desc->ds_us.tx.ts_tstamp =
+	    AR5K_REG_MS(tx_desc->tx_control_0,
+	    AR5K_AR5210_DESC_TX_CTL0_XMIT_RATE);
+
+	if ((tx_status->tx_status_0 &
+	    AR5K_AR5210_DESC_TX_STATUS0_FRAME_XMIT_OK) == 0) {
+		if (tx_status->tx_status_0 &
+		    AR5K_AR5210_DESC_TX_STATUS0_EXCESSIVE_RETRIES)
 			desc->ds_us.tx.ts_status |= HAL_TXERR_XRETRY;
 
-		if (tx_status->fifo_underrun)
+		if (tx_status->tx_status_0 &
+		    AR5K_AR5210_DESC_TX_STATUS0_FIFO_UNDERRUN)
 			desc->ds_us.tx.ts_status |= HAL_TXERR_FIFO;
 
-		if (tx_status->filtered)
+		if (tx_status->tx_status_0 &
+		    AR5K_AR5210_DESC_TX_STATUS0_FILTERED)
 			desc->ds_us.tx.ts_status |= HAL_TXERR_FILT;
 	}
-#if 0
-	/*
-	 * Reset descriptor
-	 */
-	bzero(tx_desc, sizeof(struct ar5k_ar5210_tx_desc));
-	bzero(tx_status, sizeof(struct ar5k_ar5210_tx_status));
-#endif
 
 	return (HAL_OK);
 }
@@ -1321,11 +1329,12 @@ ar5k_ar5210_setupRxDesc(hal, desc, size, flags)
 
 	rx_desc = (struct ar5k_ar5210_rx_desc*)&desc->ds_ctl0;
 
-	if ((rx_desc->buf_len = size) != size)
+	if ((rx_desc->rx_control_1 = (size &
+	    AR5K_AR5210_DESC_RX_CTL1_BUF_LEN)) != size)
 		return (AH_FALSE);
 
 	if (flags & HAL_RXDESC_INTREQ)
-		rx_desc->inter_req = 1;
+		rx_desc->rx_control_1 |= AR5K_AR5210_DESC_RX_CTL1_INTREQ;
 
 	return (AH_TRUE);
 }
@@ -1337,56 +1346,69 @@ ar5k_ar5210_procRxDesc(hal, desc, phys_addr, next)
 	u_int32_t phys_addr;
 	struct ath_desc *next;
 {
-	u_int32_t now, tstamp;
 	struct ar5k_ar5210_rx_status *rx_status;
 
 	rx_status = (struct ar5k_ar5210_rx_status*)&desc->ds_hw[0];
 
 	/* No frame received / not ready */
-	if (!rx_status->done)
+	if ((rx_status->rx_status_1 & AR5K_AR5210_DESC_RX_STATUS1_DONE) == 0)
 		return (HAL_EINPROGRESS);
 
 	/*
 	 * Frame receive status
 	 */
-	now = (AR5K_REG_READ(AR5K_AR5210_TSF_L32) >> 10) & 0xffff;
-	tstamp = ((now & 0x1fff) < rx_status->receive_timestamp) ?
-	    (((now - 0x2000) & 0xffff) |
-		(u_int32_t)rx_status->receive_timestamp) :
-	    (now | (u_int32_t)rx_status->receive_timestamp);
-	desc->ds_us.rx.rs_tstamp = rx_status->receive_timestamp & 0x7fff;
-	desc->ds_us.rx.rs_datalen = rx_status->data_len;
-	desc->ds_us.rx.rs_rssi = rx_status->receive_sig_strength;
-	desc->ds_us.rx.rs_rate = rx_status->receive_rate;
-	desc->ds_us.rx.rs_antenna = rx_status->receive_antenna ? 1 : 0;
-	desc->ds_us.rx.rs_more = rx_status->more ? 1 : 0;
+	desc->ds_us.rx.rs_datalen = rx_status->rx_status_0 &
+	    AR5K_AR5210_DESC_RX_STATUS0_DATA_LEN;
+	desc->ds_us.rx.rs_rssi =
+	    AR5K_REG_MS(rx_status->rx_status_0,
+	    AR5K_AR5210_DESC_RX_STATUS0_RECEIVE_SIGNAL);
+	desc->ds_us.rx.rs_rate =
+	    AR5K_REG_MS(rx_status->rx_status_0,
+	    AR5K_AR5210_DESC_RX_STATUS0_RECEIVE_RATE);
+	desc->ds_us.rx.rs_antenna = rx_status->rx_status_0 &
+	    AR5K_AR5210_DESC_RX_STATUS0_RECEIVE_ANTENNA;
+	desc->ds_us.rx.rs_more = rx_status->rx_status_0 &
+	    AR5K_AR5210_DESC_RX_STATUS0_MORE;
+	desc->ds_us.rx.rs_tstamp =
+	    AR5K_REG_MS(rx_status->rx_status_1,
+	    AR5K_AR5210_DESC_RX_STATUS1_RECEIVE_TIMESTAMP);
 	desc->ds_us.rx.rs_status = 0;
 
 	/*
 	 * Key table status
 	 */
-	if (!rx_status->key_index_valid) {
-		desc->ds_us.rx.rs_keyix = HAL_RXKEYIX_INVALID;
+	if (rx_status->rx_status_1 &
+	    AR5K_AR5210_DESC_RX_STATUS1_KEY_INDEX_VALID) {
+		desc->ds_us.rx.rs_keyix =
+		    AR5K_REG_MS(rx_status->rx_status_1,
+		    AR5K_AR5210_DESC_RX_STATUS1_KEY_INDEX);
 	} else {
-		desc->ds_us.rx.rs_keyix = rx_status->key_index;
+		desc->ds_us.rx.rs_keyix = HAL_RXKEYIX_INVALID;
 	}
 
 	/*
 	 * Receive/descriptor errors
 	 */
-	if (!rx_status->frame_receive_ok) {
-		if (rx_status->crc_error)
+	if ((rx_status->rx_status_1 &
+	    AR5K_AR5210_DESC_RX_STATUS1_FRAME_RECEIVE_OK) == 0) {
+		if (rx_status->rx_status_1 &
+		    AR5K_AR5210_DESC_RX_STATUS1_CRC_ERROR)
 			desc->ds_us.rx.rs_status |= HAL_RXERR_CRC;
 
-		if (rx_status->phy_error) {
+		if (rx_status->rx_status_1 &
+		    AR5K_AR5210_DESC_RX_STATUS1_FIFO_OVERRUN)
+			desc->ds_us.rx.rs_status |= HAL_RXERR_FIFO;
+
+		if (rx_status->rx_status_1 &
+		    AR5K_AR5210_DESC_RX_STATUS1_PHY_ERROR) {
 			desc->ds_us.rx.rs_status |= HAL_RXERR_PHY;
-			desc->ds_us.rx.rs_phyerr = rx_status->phy_error;
+			desc->ds_us.rx.rs_phyerr =
+			    AR5K_REG_MS(rx_status->rx_status_1,
+			    AR5K_AR5210_DESC_RX_STATUS1_PHY_ERROR);
 		}
 
-		if (rx_status->fifo_overrun)
-			desc->ds_us.rx.rs_status |= HAL_RXERR_FIFO;
-
-		if (rx_status->decrypt_crc_error)
+		if (rx_status->rx_status_1 &
+		    AR5K_AR5210_DESC_RX_STATUS1_DECRYPT_CRC_ERROR)
 			desc->ds_us.rx.rs_status |= HAL_RXERR_DECRYPT;
 	}
 
diff --git a/sys/dev/ic/ar5210var.h b/sys/dev/ic/ar5210var.h
index 9d88415c503..1615b348539 100644
--- a/sys/dev/ic/ar5210var.h
+++ b/sys/dev/ic/ar5210var.h
@@ -1,4 +1,4 @@
-/*	$OpenBSD: ar5210var.h,v 1.7 2005/02/17 23:52:05 reyk Exp $	*/
+/*	$OpenBSD: ar5210var.h,v 1.8 2005/04/08 22:02:49 reyk Exp $	*/
 
 /*
  * Copyright (c) 2004, 2005 Reyk Floeter <reyk@vantronix.net>
@@ -50,45 +50,53 @@
 
 struct ar5k_ar5210_rx_desc {
 	/*
-	 * First word
+	 * RX control word 0
 	 */
-	u_int32_t	r1;
+	u_int32_t	rx_control_0;
+
+#define AR5K_AR5210_DESC_RX_CTL0			0x00000000
 
 	/*
-	 * Second word
+	 * RX control word 1
 	 */
-	u_int32_t	buf_len:12;
-	u_int32_t	r2:1;
-	u_int32_t	inter_req:1;
-	u_int32_t	r3:18;
+	u_int32_t	rx_control_1;
+
+#define AR5K_AR5210_DESC_RX_CTL1_BUF_LEN		0x00000fff
+#define AR5K_AR5210_DESC_RX_CTL1_INTREQ			0x00002000
 } __packed;
 
 struct ar5k_ar5210_rx_status {
 	/*
-	 * First word
+	 * RX status word 0
 	 */
-	u_int32_t	data_len:12;
-	u_int32_t	more:1;
-	u_int32_t	r1:1;
-	u_int32_t	receive_antenna:1;
-	u_int32_t	receive_rate:4;
-	u_int32_t	receive_sig_strength:8;
-	u_int32_t	r2:5;
+	u_int32_t	rx_status_0;
+	
+#define AR5K_AR5210_DESC_RX_STATUS0_DATA_LEN		0x00000fff
+#define AR5K_AR5210_DESC_RX_STATUS0_MORE		0x00001000
+#define AR5K_AR5210_DESC_RX_STATUS0_RECEIVE_ANTENNA	0x00004000
+#define AR5K_AR5210_DESC_RX_STATUS0_RECEIVE_RATE	0x00078000
+#define AR5K_AR5210_DESC_RX_STATUS0_RECEIVE_RATE_S	15
+#define AR5K_AR5210_DESC_RX_STATUS0_RECEIVE_SIGNAL	0x07f80000
+#define AR5K_AR5210_DESC_RX_STATUS0_RECEIVE_SIGNAL_S	19
 
 	/*
-	 * Second word
+	 * RX status word 1
 	 */
-	u_int32_t	done:1;
-	u_int32_t	frame_receive_ok:1;
-	u_int32_t	crc_error:1;
-	u_int32_t	fifo_overrun:1;
-	u_int32_t	decrypt_crc_error:1;
-	u_int32_t	phy_error:3;
-	u_int32_t	key_index_valid:1;
-	u_int32_t	key_index:6;
-	u_int32_t	receive_timestamp:13;
-	u_int32_t	key_cache_miss:1;
-	u_int32_t	r3:3;
+	u_int32_t	rx_status_1;
+
+#define AR5K_AR5210_DESC_RX_STATUS1_DONE		0x00000001
+#define AR5K_AR5210_DESC_RX_STATUS1_FRAME_RECEIVE_OK	0x00000002
+#define AR5K_AR5210_DESC_RX_STATUS1_CRC_ERROR		0x00000004
+#define AR5K_AR5210_DESC_RX_STATUS1_FIFO_OVERRUN	0x00000008
+#define AR5K_AR5210_DESC_RX_STATUS1_DECRYPT_CRC_ERROR	0x00000010
+#define AR5K_AR5210_DESC_RX_STATUS1_PHY_ERROR		0x000000e0
+#define AR5K_AR5210_DESC_RX_STATUS1_PHY_ERROR_S		5
+#define AR5K_AR5210_DESC_RX_STATUS1_KEY_INDEX_VALID	0x00000100
+#define AR5K_AR5210_DESC_RX_STATUS1_KEY_INDEX		0x00007e00
+#define AR5K_AR5210_DESC_RX_STATUS1_KEY_INDEX_S		9
+#define AR5K_AR5210_DESC_RX_STATUS1_RECEIVE_TIMESTAMP	0x0fff8000
+#define AR5K_AR5210_DESC_RX_STATUS1_RECEIVE_TIMESTAMP_S	15
+#define AR5K_AR5210_DESC_RX_STATUS1_KEY_CACHE_MISS	0x10000000
 } __packed;
 
 #define AR5K_AR5210_DESC_RX_PHY_ERROR_NONE		0x00
@@ -102,64 +110,69 @@ struct ar5k_ar5210_rx_status {
 
 struct ar5k_ar5210_tx_desc {
 	/*
-	 * First word
+	 * TX control word 0
 	 */
-	u_int32_t	frame_len:12;
-	u_int32_t	header_len:6;
-	u_int32_t	xmit_rate:4;
-	u_int32_t	rts_cts_enable:1;
-	u_int32_t	long_packet:1;
-	u_int32_t	clear_dest_mask:1;
-	u_int32_t	ant_mode_xmit:1;
-	u_int32_t	frame_type:3;
-	u_int32_t	inter_req:1;
-	u_int32_t	encrypt_key_valid:1;
-	u_int32_t	r1:1;
+	u_int32_t	tx_control_0;
+
+#define AR5K_AR5210_DESC_TX_CTL0_FRAME_LEN		0x00000fff
+#define AR5K_AR5210_DESC_TX_CTL0_HEADER_LEN		0x0003f000
+#define AR5K_AR5210_DESC_TX_CTL0_HEADER_LEN_S		12
+#define AR5K_AR5210_DESC_TX_CTL0_XMIT_RATE		0x003c0000
+#define AR5K_AR5210_DESC_TX_CTL0_XMIT_RATE_S		18
+#define AR5K_AR5210_DESC_TX_CTL0_RTSENA			0x00400000
+#define AR5K_AR5210_DESC_TX_CTL0_LONG_PACKET		0x00800000
+#define AR5K_AR5210_DESC_TX_CTL0_CLRDMASK		0x01000000
+#define AR5K_AR5210_DESC_TX_CTL0_ANT_MODE_XMIT		0x02000000
+#define AR5K_AR5210_DESC_TX_CTL0_FRAME_TYPE		0x1c000000
+#define AR5K_AR5210_DESC_TX_CTL0_FRAME_TYPE_S		26
+#define AR5K_AR5210_DESC_TX_CTL0_INTREQ			0x20000000
+#define AR5K_AR5210_DESC_TX_CTL0_ENCRYPT_KEY_VALID	0x40000000
 
 	/*
-	 * Second word
+	 * TX control word 1
 	 */
-	u_int32_t	buf_len:12;
-	u_int32_t	more:1;
-	u_int32_t	encrypt_key_index:6;
-	u_int32_t	rts_duration:13;
-} __packed;
+	u_int32_t	tx_control_1;
 
-#define AR5K_AR5210_DESC_TX_XMIT_RATE_6		0xb
-#define AR5K_AR5210_DESC_TX_XMIT_RATE_9		0xf
-#define AR5K_AR5210_DESC_TX_XMIT_RATE_12	0xa
-#define AR5K_AR5210_DESC_TX_XMIT_RATE_18	0xe
-#define AR5K_AR5210_DESC_TX_XMIT_RATE_24	0x9
-#define AR5K_AR5210_DESC_TX_XMIT_RATE_36	0xd
-#define AR5K_AR5210_DESC_TX_XMIT_RATE_48	0x8
-#define AR5K_AR5210_DESC_TX_XMIT_RATE_54	0xc
+#define AR5K_AR5210_DESC_TX_CTL1_BUF_LEN		0x00000fff
+#define AR5K_AR5210_DESC_TX_CTL1_MORE			0x00001000
+#define AR5K_AR5210_DESC_TX_CTL1_ENCRYPT_KEY_INDEX	0x0007e000
+#define AR5K_AR5210_DESC_TX_CTL1_ENCRYPT_KEY_INDEX_S	13
+#define AR5K_AR5210_DESC_TX_CTL1_RTS_DURATION		0xfff80000
+} __packed;
 
-#define AR5K_AR5210_DESC_TX_FRAME_TYPE_NORMAL	0x00
-#define AR5K_AR5210_DESC_TX_FRAME_TYPE_ATIM	0x04
-#define AR5K_AR5210_DESC_TX_FRAME_TYPE_PSPOLL	0x08
+#define AR5K_AR5210_DESC_TX_FRAME_TYPE_NORMAL   0x00
+#define AR5K_AR5210_DESC_TX_FRAME_TYPE_ATIM     0x04
+#define AR5K_AR5210_DESC_TX_FRAME_TYPE_PSPOLL   0x08
 #define AR5K_AR5210_DESC_TX_FRAME_TYPE_NO_DELAY 0x0c
-#define AR5K_AR5210_DESC_TX_FRAME_TYPE_PIFS	0x10
+#define AR5K_AR5210_DESC_TX_FRAME_TYPE_PIFS     0x10
 
 struct ar5k_ar5210_tx_status {
 	/*
-	 * First word
+	 * TX status word 0
 	 */
-	u_int32_t	frame_xmit_ok:1;
-	u_int32_t	excessive_retries:1;
-	u_int32_t	fifo_underrun:1;
-	u_int32_t	filtered:1;
-	u_int32_t	short_retry_count:4;
-	u_int32_t	long_retry_count:4;
-	u_int32_t	r1:4;
-	u_int32_t	send_timestamp:16;
+	u_int32_t	tx_status_0;
+
+#define AR5K_AR5210_DESC_TX_STATUS0_FRAME_XMIT_OK	0x00000001
+#define AR5K_AR5210_DESC_TX_STATUS0_EXCESSIVE_RETRIES	0x00000002
+#define AR5K_AR5210_DESC_TX_STATUS0_FIFO_UNDERRUN	0x00000004
+#define AR5K_AR5210_DESC_TX_STATUS0_FILTERED		0x00000008
+#define AR5K_AR5210_DESC_TX_STATUS0_SHORT_RETRY_COUNT	0x000000f0
+#define AR5K_AR5210_DESC_TX_STATUS0_SHORT_RETRY_COUNT_S	4
+#define AR5K_AR5210_DESC_TX_STATUS0_LONG_RETRY_COUNT	0x00000f00
+#define AR5K_AR5210_DESC_TX_STATUS0_LONG_RETRY_COUNT_S	8
+#define AR5K_AR5210_DESC_TX_STATUS0_SEND_TIMESTAMP	0xffff0000
+#define AR5K_AR5210_DESC_TX_STATUS0_SEND_TIMESTAMP_S	16
 
 	/*
-	 * Second word
+	 * TX status word 1
 	 */
-	u_int32_t	done:1;
-	u_int32_t	seq_num:12;
-	u_int32_t	ack_sig_strength:8;
-	u_int32_t	r2:11;
+	u_int32_t	tx_status_1;
+
+#define AR5K_AR5210_DESC_TX_STATUS1_DONE		0x00000001
+#define AR5K_AR5210_DESC_TX_STATUS1_SEQ_NUM		0x00001ffe
+#define AR5K_AR5210_DESC_TX_STATUS1_SEQ_NUM_S		1
+#define AR5K_AR5210_DESC_TX_STATUS1_ACK_SIG_STRENGTH	0x001fe000
+#define AR5K_AR5210_DESC_TX_STATUS1_ACK_SIG_STRENGTH_S	13
 } __packed;
 
 /*
diff --git a/sys/dev/ic/ar5211.c b/sys/dev/ic/ar5211.c
index 12325475951..da66f4e3d76 100644
--- a/sys/dev/ic/ar5211.c
+++ b/sys/dev/ic/ar5211.c
@@ -1,4 +1,4 @@
-/*	$OpenBSD: ar5211.c,v 1.8 2005/04/06 09:14:53 reyk Exp $	*/
+/*	$OpenBSD: ar5211.c,v 1.9 2005/04/08 22:02:49 reyk Exp $	*/
 
 /*
  * Copyright (c) 2004, 2005 Reyk Floeter <reyk@vantronix.net>
@@ -1127,21 +1127,26 @@ ar5k_ar5211_setupTxDesc(hal, desc, packet_length, header_length, type, tx_power,
 	if (tx_tries0 == 0)
 		return (AH_FALSE);
 
-	if ((tx_desc->frame_len = packet_length) != packet_length)
+	if ((tx_desc->tx_control_0 = (packet_length &
+	    AR5K_AR5211_DESC_TX_CTL0_FRAME_LEN)) != packet_length)
 		return (AH_FALSE);
 
-	tx_desc->frame_type = type;
-	tx_desc->xmit_rate = tx_rate0;
-	tx_desc->ant_mode_xmit = antenna_mode;
+	tx_desc->tx_control_0 |=
+	    AR5K_REG_SM(tx_rate0, AR5K_AR5211_DESC_TX_CTL0_XMIT_RATE) |
+	    AR5K_REG_SM(antenna_mode, AR5K_AR5211_DESC_TX_CTL0_ANT_MODE_XMIT);
+	tx_desc->tx_control_1 =
+	    AR5K_REG_SM(type, AR5K_AR5211_DESC_TX_CTL1_FRAME_TYPE);
 
-#define _TX_FLAGS(_flag, _field) \
-	tx_desc->_field = flags & HAL_TXDESC_##_flag ? 1 : 0
+#define _TX_FLAGS(_c, _flag)	 					\
+	if (flags & HAL_TXDESC_##_flag)					\
+		tx_desc->tx_control_##_c |=    				\
+			AR5K_AR5211_DESC_TX_CTL##_c##_##_flag
 
-	_TX_FLAGS(CLRDMASK, clear_dest_mask);
-	_TX_FLAGS(VEOL, veol);
-	_TX_FLAGS(INTREQ, inter_req);
-	_TX_FLAGS(NOACK, no_ack);
-	_TX_FLAGS(RTSENA, rts_cts_enable);
+	_TX_FLAGS(0, CLRDMASK);
+	_TX_FLAGS(0, VEOL);
+	_TX_FLAGS(0, INTREQ);
+	_TX_FLAGS(0, RTSENA);
+	_TX_FLAGS(1, NOACK);
 
 #undef _TX_FLAGS
 
@@ -1149,8 +1154,11 @@ ar5k_ar5211_setupTxDesc(hal, desc, packet_length, header_length, type, tx_power,
 	 * WEP crap
 	 */
 	if (key_index != HAL_TXKEYIX_INVALID) {
-		tx_desc->encrypt_key_valid = 1;
-		tx_desc->encrypt_key_index = key_index;
+		tx_desc->tx_control_0 |=
+		    AR5K_AR5211_DESC_TX_CTL0_ENCRYPT_KEY_VALID;
+		tx_desc->tx_control_1 |=
+		    AR5K_REG_SM(key_index,
+		    AR5K_AR5211_DESC_TX_CTL1_ENCRYPT_KEY_INDEX);
 	}
 
 	return (AH_TRUE);
@@ -1172,13 +1180,15 @@ ar5k_ar5211_fillTxDesc(hal, desc, segment_length, first_segment, last_segment)
 	bzero(desc->ds_hw, sizeof(desc->ds_hw));
 
 	/* Validate segment length and initialize the descriptor */
-	if ((tx_desc->buf_len = segment_length) != segment_length)
+	if ((tx_desc->tx_control_1 = (segment_length &
+	    AR5K_AR5211_DESC_TX_CTL1_BUF_LEN)) != segment_length)
 		return (AH_FALSE);
 
 	if (first_segment != AH_TRUE)
-		tx_desc->frame_len = 0;
+		tx_desc->tx_control_0 &= ~AR5K_AR5211_DESC_TX_CTL0_FRAME_LEN;
 
-	tx_desc->more = last_segment == AH_TRUE ? 0 : 1;
+	if (last_segment != AH_TRUE)
+		tx_desc->tx_control_1 |= AR5K_AR5211_DESC_TX_CTL1_MORE;
 
 	return (AH_TRUE);
 }
@@ -1210,31 +1220,45 @@ ar5k_ar5211_procTxDesc(hal, desc)
 	tx_status = (struct ar5k_ar5211_tx_status*)&desc->ds_hw[0];
 
 	/* No frame has been send or error */
-	if (tx_status->done == 0)
+	if ((tx_status->tx_status_1 & AR5K_AR5211_DESC_TX_STATUS1_DONE) == 0)
 		return (HAL_EINPROGRESS);
 
 	/*
 	 * Get descriptor status
 	 */
-	desc->ds_us.tx.ts_seqnum = tx_status->seq_num;
-	desc->ds_us.tx.ts_tstamp = tx_status->send_timestamp;
-	desc->ds_us.tx.ts_shortretry = tx_status->rts_fail_count ?
-	    (tx_status->rts_fail_count + 1) : 0;
-	desc->ds_us.tx.ts_longretry = tx_status->data_fail_count ?
-	    (tx_status->data_fail_count + 1) : 0;
-	desc->ds_us.tx.ts_rssi = tx_status->ack_sig_strength;
-	desc->ds_us.tx.ts_antenna = 0;
+	desc->ds_us.tx.ts_tstamp =
+	    AR5K_REG_MS(tx_status->tx_status_0,
+	    AR5K_AR5211_DESC_TX_STATUS0_SEND_TIMESTAMP);
+	desc->ds_us.tx.ts_shortretry =
+	    AR5K_REG_MS(tx_status->tx_status_0,
+	    AR5K_AR5211_DESC_TX_STATUS0_RTS_FAIL_COUNT);
+	desc->ds_us.tx.ts_longretry =
+	    AR5K_REG_MS(tx_status->tx_status_0,
+	    AR5K_AR5211_DESC_TX_STATUS0_DATA_FAIL_COUNT);
+	desc->ds_us.tx.ts_seqnum =
+	    AR5K_REG_MS(tx_status->tx_status_1,
+	    AR5K_AR5211_DESC_TX_STATUS1_SEQ_NUM);
+	desc->ds_us.tx.ts_rssi =
+	    AR5K_REG_MS(tx_status->tx_status_1,
+	    AR5K_AR5211_DESC_TX_STATUS1_ACK_SIG_STRENGTH);
+	desc->ds_us.tx.ts_antenna = 1;
 	desc->ds_us.tx.ts_status = 0;
-	desc->ds_us.tx.ts_rate = tx_desc->xmit_rate;
-
-	if (tx_status->frame_xmit_ok == 0) {
-		if (tx_status->excessive_retries)
+	desc->ds_us.tx.ts_tstamp =
+	    AR5K_REG_MS(tx_desc->tx_control_0,
+	    AR5K_AR5211_DESC_TX_CTL0_XMIT_RATE);
+
+	if ((tx_status->tx_status_0 &
+	    AR5K_AR5211_DESC_TX_STATUS0_FRAME_XMIT_OK) == 0) {
+		if (tx_status->tx_status_0 &
+		    AR5K_AR5211_DESC_TX_STATUS0_EXCESSIVE_RETRIES)
 			desc->ds_us.tx.ts_status |= HAL_TXERR_XRETRY;
 
-		if (tx_status->fifo_underrun)
+		if (tx_status->tx_status_0 &
+		    AR5K_AR5211_DESC_TX_STATUS0_FIFO_UNDERRUN)
 			desc->ds_us.tx.ts_status |= HAL_TXERR_FIFO;
 
-		if (tx_status->filtered)
+		if (tx_status->tx_status_0 &
+		    AR5K_AR5211_DESC_TX_STATUS0_FILTERED)
 			desc->ds_us.tx.ts_status |= HAL_TXERR_FILT;
 	}
 
@@ -1386,11 +1410,12 @@ ar5k_ar5211_setupRxDesc(hal, desc, size, flags)
 
 	rx_desc = (struct ar5k_ar5211_rx_desc*)&desc->ds_ctl0;
 
-	if ((rx_desc->buf_len = size) != size)
+	if ((rx_desc->rx_control_1 = (size &
+	    AR5K_AR5211_DESC_RX_CTL1_BUF_LEN)) != size)
 		return (AH_FALSE);
 
 	if (flags & HAL_RXDESC_INTREQ)
-		rx_desc->inter_req = 1;
+		rx_desc->rx_control_1 |= AR5K_AR5211_DESC_RX_CTL1_INTREQ;
 
 	return (AH_TRUE);
 }
@@ -1402,53 +1427,65 @@ ar5k_ar5211_procRxDesc(hal, desc, phys_addr, next)
 	u_int32_t phys_addr;
 	struct ath_desc *next;
 {
-	u_int32_t now, tstamp;
 	struct ar5k_ar5211_rx_status *rx_status;
 
 	rx_status = (struct ar5k_ar5211_rx_status*)&desc->ds_hw[0];
 
 	/* No frame received / not ready */
-	if (!rx_status->done)
+	if ((rx_status->rx_status_1 & AR5K_AR5211_DESC_RX_STATUS1_DONE) == 0)
 		return (HAL_EINPROGRESS);
 
 	/*
 	 * Frame receive status
 	 */
-	now = (AR5K_REG_READ(AR5K_AR5211_TSF_L32) >> 10) & 0xffff;
-	tstamp = ((now & 0x1fff) < rx_status->receive_timestamp) ?
-	    (((now - 0x2000) & 0xffff) |
-	    (u_int32_t)rx_status->receive_timestamp) :
-	    (now | (u_int32_t)rx_status->receive_timestamp);
-	desc->ds_us.rx.rs_tstamp = rx_status->receive_timestamp & 0x7fff;
-	desc->ds_us.rx.rs_datalen = rx_status->data_len;
-	desc->ds_us.rx.rs_rssi = rx_status->receive_sig_strength;
-	desc->ds_us.rx.rs_rate = rx_status->receive_rate;
-	desc->ds_us.rx.rs_antenna = rx_status->receive_antenna ? 1 : 0;
-	desc->ds_us.rx.rs_more = rx_status->more ? 1 : 0;
+	desc->ds_us.rx.rs_datalen = rx_status->rx_status_0 &
+	    AR5K_AR5211_DESC_RX_STATUS0_DATA_LEN;
+	desc->ds_us.rx.rs_rssi =
+	    AR5K_REG_MS(rx_status->rx_status_0,
+	    AR5K_AR5211_DESC_RX_STATUS0_RECEIVE_SIGNAL);
+	desc->ds_us.rx.rs_rate =
+	    AR5K_REG_MS(rx_status->rx_status_0,
+	    AR5K_AR5211_DESC_RX_STATUS0_RECEIVE_RATE);
+	desc->ds_us.rx.rs_antenna = rx_status->rx_status_0 &
+	    AR5K_AR5211_DESC_RX_STATUS0_RECEIVE_ANTENNA;
+	desc->ds_us.rx.rs_more = rx_status->rx_status_0 &
+	    AR5K_AR5211_DESC_RX_STATUS0_MORE;
+	desc->ds_us.rx.rs_tstamp =
+	    AR5K_REG_MS(rx_status->rx_status_1,
+	    AR5K_AR5211_DESC_RX_STATUS1_RECEIVE_TIMESTAMP);
 	desc->ds_us.rx.rs_status = 0;
 
 	/*
 	 * Key table status
 	 */
-	if (!rx_status->key_index_valid) {
-		desc->ds_us.rx.rs_keyix = HAL_RXKEYIX_INVALID;
+	if (rx_status->rx_status_1 &
+	    AR5K_AR5211_DESC_RX_STATUS1_KEY_INDEX_VALID) {
+		desc->ds_us.rx.rs_keyix =
+		    AR5K_REG_MS(rx_status->rx_status_1,
+		    AR5K_AR5211_DESC_RX_STATUS1_KEY_INDEX);
 	} else {
-		desc->ds_us.rx.rs_keyix = rx_status->key_index;
+		desc->ds_us.rx.rs_keyix = HAL_RXKEYIX_INVALID;
 	}
 
 	/*
 	 * Receive/descriptor errors
 	 */
-	if (!rx_status->frame_receive_ok) {
-		if (rx_status->crc_error)
+	if ((rx_status->rx_status_1 &
+	    AR5K_AR5211_DESC_RX_STATUS1_FRAME_RECEIVE_OK) == 0) {
+		if (rx_status->rx_status_1 &
+		    AR5K_AR5211_DESC_RX_STATUS1_CRC_ERROR)
 			desc->ds_us.rx.rs_status |= HAL_RXERR_CRC;
 
-		if (rx_status->phy_error) {
+		if (rx_status->rx_status_1 &
+		    AR5K_AR5211_DESC_RX_STATUS1_PHY_ERROR) {
 			desc->ds_us.rx.rs_status |= HAL_RXERR_PHY;
-			desc->ds_us.rx.rs_phyerr = rx_status->phy_error;
+			desc->ds_us.rx.rs_phyerr =
+			    AR5K_REG_MS(rx_status->rx_status_1,
+			    AR5K_AR5211_DESC_RX_STATUS1_PHY_ERROR);
 		}
 
-		if (rx_status->decrypt_crc_error)
+		if (rx_status->rx_status_1 &
+		    AR5K_AR5211_DESC_RX_STATUS1_DECRYPT_CRC_ERROR)
 			desc->ds_us.rx.rs_status |= HAL_RXERR_DECRYPT;
 	}
 
diff --git a/sys/dev/ic/ar5211var.h b/sys/dev/ic/ar5211var.h
index f9d59a38186..c316b0409dc 100644
--- a/sys/dev/ic/ar5211var.h
+++ b/sys/dev/ic/ar5211var.h
@@ -1,4 +1,4 @@
-/*	$OpenBSD: ar5211var.h,v 1.1 2005/02/25 22:25:30 reyk Exp $	*/
+/*	$OpenBSD: ar5211var.h,v 1.2 2005/04/08 22:02:49 reyk Exp $	*/
 
 /*
  * Copyright (c) 2004, 2005 Reyk Floeter <reyk@vantronix.net>
@@ -50,45 +50,54 @@
 
 struct ar5k_ar5211_rx_desc {
 	/*
-	 * First word
+	 * RX control word 0
 	 */
-	u_int32_t	r1;
+	u_int32_t	rx_control_0;
+
+#define AR5K_AR5211_DESC_RX_CTL0			0x00000000
 
 	/*
-	 * Second word
+	 * RX control word 1
 	 */
-	u_int32_t	buf_len:12;
-	u_int32_t	r2:1;
-	u_int32_t	inter_req:1;
-	u_int32_t	r3:18;
+	u_int32_t	rx_control_1;
+
+#define AR5K_AR5211_DESC_RX_CTL1_BUF_LEN		0x00000fff
+#define AR5K_AR5211_DESC_RX_CTL1_INTREQ			0x00002000
 } __packed;
 
 struct ar5k_ar5211_rx_status {
 	/*
-	 * First word
+	 * RX status word 0
 	 */
-	u_int32_t	data_len:12;
-	u_int32_t	more:1;
-	u_int32_t	r1:1;
-	u_int32_t	receive_antenna:1;
-	u_int32_t	receive_rate:4;
-	u_int32_t	receive_sig_strength:8;
-	u_int32_t	r2:5;
+	u_int32_t	rx_status_0;
+	
+#define AR5K_AR5211_DESC_RX_STATUS0_DATA_LEN		0x00000fff
+#define AR5K_AR5211_DESC_RX_STATUS0_MORE		0x00001000
+#define AR5K_AR5211_DESC_RX_STATUS0_RECEIVE_RATE	0x00078000
+#define AR5K_AR5211_DESC_RX_STATUS0_RECEIVE_RATE_S	15
+#define AR5K_AR5211_DESC_RX_STATUS0_RECEIVE_SIGNAL	0x07f80000
+#define AR5K_AR5211_DESC_RX_STATUS0_RECEIVE_SIGNAL_S	19
+#define AR5K_AR5211_DESC_RX_STATUS0_RECEIVE_ANTENNA	0x38000000
+#define AR5K_AR5211_DESC_RX_STATUS0_RECEIVE_ANTENNA_S	27
 
 	/*
-	 * Second word
+	 * RX status word 1
 	 */
-	u_int32_t	done:1;
-	u_int32_t	frame_receive_ok:1;
-	u_int32_t	crc_error:1;
-	u_int32_t	fifo_overrun:1;
-	u_int32_t	decrypt_crc_error:1;
-	u_int32_t	phy_error:3;
-	u_int32_t	key_index_valid:1;
-	u_int32_t	key_index:6;
-	u_int32_t	receive_timestamp:13;
-	u_int32_t	key_cache_miss:1;
-	u_int32_t	r3:3;
+	u_int32_t	rx_status_1;
+
+#define AR5K_AR5211_DESC_RX_STATUS1_DONE		0x00000001
+#define AR5K_AR5211_DESC_RX_STATUS1_FRAME_RECEIVE_OK	0x00000002
+#define AR5K_AR5211_DESC_RX_STATUS1_CRC_ERROR		0x00000004
+#define AR5K_AR5211_DESC_RX_STATUS1_FIFO_OVERRUN	0x00000008
+#define AR5K_AR5211_DESC_RX_STATUS1_DECRYPT_CRC_ERROR	0x00000010
+#define AR5K_AR5211_DESC_RX_STATUS1_PHY_ERROR		0x000000e0
+#define AR5K_AR5211_DESC_RX_STATUS1_PHY_ERROR_S		5
+#define AR5K_AR5211_DESC_RX_STATUS1_KEY_INDEX_VALID	0x00000100
+#define AR5K_AR5211_DESC_RX_STATUS1_KEY_INDEX		0x00007e00
+#define AR5K_AR5211_DESC_RX_STATUS1_KEY_INDEX_S		9
+#define AR5K_AR5211_DESC_RX_STATUS1_RECEIVE_TIMESTAMP	0x0fff8000
+#define AR5K_AR5211_DESC_RX_STATUS1_RECEIVE_TIMESTAMP_S	15
+#define AR5K_AR5211_DESC_RX_STATUS1_KEY_CACHE_MISS	0x10000000
 } __packed;
 
 #define AR5K_AR5211_DESC_RX_PHY_ERROR_NONE		0x00
@@ -102,65 +111,64 @@ struct ar5k_ar5211_rx_status {
 
 struct ar5k_ar5211_tx_desc {
 	/*
-	 * First word
+	 * TX control word 0
 	 */
-	u_int32_t	frame_len:12;
-	u_int32_t	reserved_12_17:6;
-	u_int32_t	xmit_rate:4;
-	u_int32_t	rts_cts_enable:1;
-	u_int32_t	veol:1;
-	u_int32_t	clear_dest_mask:1;
-	u_int32_t	ant_mode_xmit:4;
-	u_int32_t	inter_req:1;
-	u_int32_t	encrypt_key_valid:1;
-	u_int32_t	reserved_31:1;
+	u_int32_t	tx_control_0;
+
+#define AR5K_AR5211_DESC_TX_CTL0_FRAME_LEN		0x00000fff
+#define AR5K_AR5211_DESC_TX_CTL0_XMIT_RATE		0x003c0000
+#define AR5K_AR5211_DESC_TX_CTL0_XMIT_RATE_S		18
+#define AR5K_AR5211_DESC_TX_CTL0_RTSENA			0x00400000
+#define AR5K_AR5211_DESC_TX_CTL0_VEOL			0x00800000
+#define AR5K_AR5211_DESC_TX_CTL0_CLRDMASK		0x01000000
+#define AR5K_AR5211_DESC_TX_CTL0_ANT_MODE_XMIT		0x1e000000
+#define AR5K_AR5211_DESC_TX_CTL0_ANT_MODE_XMIT_S	25
+#define AR5K_AR5211_DESC_TX_CTL0_INTREQ			0x20000000
+#define AR5K_AR5211_DESC_TX_CTL0_ENCRYPT_KEY_VALID	0x40000000
 
 	/*
-	 * Second word
+	 * TX control word 1
 	 */
-	u_int32_t	buf_len:12;
-	u_int32_t	more:1;
-	u_int32_t	encrypt_key_index:7;
-	u_int32_t	frame_type:4;
-	u_int32_t	no_ack:1;
-	u_int32_t	reserved_24_31:1;
-} __packed;
+	u_int32_t	tx_control_1;
 
-#define AR5K_AR5211_DESC_TX_XMIT_RATE_6		0xb
-#define AR5K_AR5211_DESC_TX_XMIT_RATE_9		0xf
-#define AR5K_AR5211_DESC_TX_XMIT_RATE_12	0xa
-#define AR5K_AR5211_DESC_TX_XMIT_RATE_18	0xe
-#define AR5K_AR5211_DESC_TX_XMIT_RATE_24	0x9
-#define AR5K_AR5211_DESC_TX_XMIT_RATE_36	0xd
-#define AR5K_AR5211_DESC_TX_XMIT_RATE_48	0x8
-#define AR5K_AR5211_DESC_TX_XMIT_RATE_54	0xc
-
-#define AR5K_AR5211_DESC_TX_FRAME_TYPE_NORMAL	0x00
-#define AR5K_AR5211_DESC_TX_FRAME_TYPE_ATIM	0x04
-#define AR5K_AR5211_DESC_TX_FRAME_TYPE_PSPOLL	0x08
-#define AR5K_AR5211_DESC_TX_FRAME_TYPE_NO_DELAY 0x0c
-#define AR5K_AR5211_DESC_TX_FRAME_TYPE_PIFS	0x10
+#define AR5K_AR5211_DESC_TX_CTL1_BUF_LEN		0x00000fff
+#define AR5K_AR5211_DESC_TX_CTL1_MORE			0x00001000
+#define AR5K_AR5211_DESC_TX_CTL1_ENCRYPT_KEY_INDEX	0x000fe000
+#define AR5K_AR5211_DESC_TX_CTL1_ENCRYPT_KEY_INDEX_S	13
+#define AR5K_AR5211_DESC_TX_CTL1_FRAME_TYPE		0x00700000
+#define AR5K_AR5211_DESC_TX_CTL1_FRAME_TYPE_S		20
+#define AR5K_AR5211_DESC_TX_CTL1_NOACK			0x00800000
+} __packed;
 
 struct ar5k_ar5211_tx_status {
 	/*
-	 * First word
+	 * TX status word 0
 	 */
-	u_int32_t	frame_xmit_ok:1;
-	u_int32_t	excessive_retries:1;
-	u_int32_t	fifo_underrun:1;
-	u_int32_t	filtered:1;
-	u_int32_t	rts_fail_count:4;
-	u_int32_t	data_fail_count:4;
-	u_int32_t	virt_coll_count:4;
-	u_int32_t	send_timestamp:16;
+	u_int32_t	tx_status_0;
+
+#define AR5K_AR5211_DESC_TX_STATUS0_FRAME_XMIT_OK	0x00000001
+#define AR5K_AR5211_DESC_TX_STATUS0_EXCESSIVE_RETRIES	0x00000002
+#define AR5K_AR5211_DESC_TX_STATUS0_FIFO_UNDERRUN	0x00000004
+#define AR5K_AR5211_DESC_TX_STATUS0_FILTERED		0x00000008
+#define AR5K_AR5211_DESC_TX_STATUS0_RTS_FAIL_COUNT	0x000000f0
+#define AR5K_AR5211_DESC_TX_STATUS0_RTS_FAIL_COUNT_S	4
+#define AR5K_AR5211_DESC_TX_STATUS0_DATA_FAIL_COUNT	0x00000f00
+#define AR5K_AR5211_DESC_TX_STATUS0_DATA_FAIL_COUNT_S	8
+#define AR5K_AR5211_DESC_TX_STATUS0_VIRT_COLL_COUNT	0x0000f000
+#define AR5K_AR5211_DESC_TX_STATUS0_VIRT_COLL_COUNT_S	12
+#define AR5K_AR5211_DESC_TX_STATUS0_SEND_TIMESTAMP	0xffff0000
+#define AR5K_AR5211_DESC_TX_STATUS0_SEND_TIMESTAMP_S	16
 
 	/*
-	 * Second word
+	 * TX status word 1
 	 */
-	u_int32_t	done:1;
-	u_int32_t	seq_num:12;
-	u_int32_t	ack_sig_strength:8;
-	u_int32_t	reserved_21_31:11;
+	u_int32_t	tx_status_1;
+
+#define AR5K_AR5211_DESC_TX_STATUS1_DONE		0x00000001
+#define AR5K_AR5211_DESC_TX_STATUS1_SEQ_NUM		0x00001ffe
+#define AR5K_AR5211_DESC_TX_STATUS1_SEQ_NUM_S		1
+#define AR5K_AR5211_DESC_TX_STATUS1_ACK_SIG_STRENGTH	0x001fe000
+#define AR5K_AR5211_DESC_TX_STATUS1_ACK_SIG_STRENGTH_S	13
 } __packed;
 
 /*
diff --git a/sys/dev/ic/ar5212.c b/sys/dev/ic/ar5212.c
index ec6e5bae051..796cdb7cf72 100644
--- a/sys/dev/ic/ar5212.c
+++ b/sys/dev/ic/ar5212.c
@@ -1,4 +1,4 @@
-/*	$OpenBSD: ar5212.c,v 1.12 2005/04/06 09:14:53 reyk Exp $	*/
+/*	$OpenBSD: ar5212.c,v 1.13 2005/04/08 22:02:49 reyk Exp $	*/
 
 /*
  * Copyright (c) 2004, 2005 Reyk Floeter <reyk@vantronix.net>
@@ -1276,24 +1276,31 @@ ar5k_ar5212_setupTxDesc(hal, desc, packet_length, header_length, type, tx_power,
 	if (tx_tries0 == 0)
 		return (AH_FALSE);
 
-	if ((tx_desc->frame_len = packet_length) != packet_length)
+	if ((tx_desc->tx_control_0 = (packet_length &
+	    AR5K_AR5212_DESC_TX_CTL0_FRAME_LEN)) != packet_length)
 		return (AH_FALSE);
 
-	tx_desc->frame_type = type;
-	tx_desc->xmit_power = tx_power;
-	tx_desc->xmit_rate0 = tx_rate0;
-	tx_desc->xmit_tries0 = tx_tries0;
-	tx_desc->ant_mode_xmit = antenna_mode;
-
-#define _TX_FLAGS(_flag, _field) \
-	tx_desc->_field = flags & HAL_TXDESC_##_flag ? 1 : 0
-
-	_TX_FLAGS(CLRDMASK, clear_dest_mask);
-	_TX_FLAGS(VEOL, veol);
-	_TX_FLAGS(INTREQ, inter_req);
-	_TX_FLAGS(NOACK, no_ack);
-	_TX_FLAGS(RTSENA, rts_cts_enable);
-	_TX_FLAGS(CTSENA, cts_enable);
+	tx_desc->tx_control_0 |=
+	    AR5K_REG_SM(tx_power, AR5K_AR5212_DESC_TX_CTL0_XMIT_POWER) |
+	    AR5K_REG_SM(antenna_mode, AR5K_AR5212_DESC_TX_CTL0_ANT_MODE_XMIT);
+	tx_desc->tx_control_1 =
+	    AR5K_REG_SM(type, AR5K_AR5212_DESC_TX_CTL1_FRAME_TYPE);
+	tx_desc->tx_control_2 =
+	    AR5K_REG_SM(tx_tries0, AR5K_AR5212_DESC_TX_CTL2_XMIT_TRIES0);
+	tx_desc->tx_control_3 =
+	    tx_rate0 & AR5K_AR5212_DESC_TX_CTL3_XMIT_RATE0;
+
+#define _TX_FLAGS(_c, _flag)	 					\
+	if (flags & HAL_TXDESC_##_flag)					\
+		tx_desc->tx_control_##_c |=    				\
+			AR5K_AR5212_DESC_TX_CTL##_c##_##_flag
+
+	_TX_FLAGS(0, CLRDMASK);
+	_TX_FLAGS(0, VEOL);
+	_TX_FLAGS(0, INTREQ);
+	_TX_FLAGS(0, RTSENA);
+	_TX_FLAGS(0, CTSENA);
+	_TX_FLAGS(1, NOACK);
 
 #undef _TX_FLAGS
 
@@ -1301,8 +1308,11 @@ ar5k_ar5212_setupTxDesc(hal, desc, packet_length, header_length, type, tx_power,
 	 * WEP crap
 	 */
 	if (key_index != HAL_TXKEYIX_INVALID) {
-		tx_desc->encrypt_key_valid = 1;
-		tx_desc->encrypt_key_index = key_index;
+		tx_desc->tx_control_0 |=
+		    AR5K_AR5212_DESC_TX_CTL0_ENCRYPT_KEY_VALID;
+		tx_desc->tx_control_1 |=
+		    AR5K_REG_SM(key_index,
+		    AR5K_AR5212_DESC_TX_CTL1_ENCRYPT_KEY_INDEX);
 	}
 
 	/*
@@ -1312,8 +1322,11 @@ ar5k_ar5212_setupTxDesc(hal, desc, packet_length, header_length, type, tx_power,
 		if ((flags & HAL_TXDESC_RTSENA) &&
 		    (flags & HAL_TXDESC_CTSENA))
 			return (AH_FALSE);
-		tx_desc->rts_cts_rate = rtscts_rate;
-		tx_desc->rts_duration = rtscts_duration;
+		tx_desc->tx_control_2 |=
+		    rtscts_duration & AR5K_AR5212_DESC_TX_CTL2_RTS_DURATION;
+		tx_desc->tx_control_3 |=
+		    AR5K_REG_SM(rtscts_rate,
+		    AR5K_AR5212_DESC_TX_CTL3_RTS_CTS_RATE);
 	}
 
 	return (AH_TRUE);
@@ -1335,13 +1348,15 @@ ar5k_ar5212_fillTxDesc(hal, desc, segment_length, first_segment, last_segment)
 	bzero(desc->ds_hw, sizeof(desc->ds_hw));
 
 	/* Validate segment length and initialize the descriptor */
-	if ((tx_desc->buf_len = segment_length) != segment_length)
+	if ((tx_desc->tx_control_1 = (segment_length &
+	    AR5K_AR5212_DESC_TX_CTL1_BUF_LEN)) != segment_length)
 		return (AH_FALSE);
 
 	if (first_segment != AH_TRUE)
-		tx_desc->frame_len = 0;
+		tx_desc->tx_control_0 &= ~AR5K_AR5212_DESC_TX_CTL0_FRAME_LEN;
 
-	tx_desc->more = last_segment == AH_TRUE ? 0 : 1;
+	if (last_segment != AH_TRUE)
+		tx_desc->tx_control_1 |= AR5K_AR5212_DESC_TX_CTL1_MORE;
 
 	return (AH_TRUE);
 }
@@ -1364,8 +1379,12 @@ ar5k_ar5212_setupXTxDesc(hal, desc, tx_rate1, tx_tries1, tx_rate2, tx_tries2,
 
 #define _XTX_TRIES(_n)							\
 	if (tx_tries##_n) {						\
-		tx_desc->xmit_tries##_n = tx_tries##_n;			\
-		tx_desc->xmit_rate##_n = tx_rate##_n;			\
+		tx_desc->tx_control_2 |=				\
+		    AR5K_REG_SM(tx_tries##_n,				\
+		    AR5K_AR5212_DESC_TX_CTL2_XMIT_TRIES##_n);		\
+		tx_desc->tx_control_3 |=				\
+		    AR5K_REG_SM(tx_rate##_n,				\
+		    AR5K_AR5212_DESC_TX_CTL3_XMIT_RATE##_n);		\
 	}
 
 	_XTX_TRIES(1);
@@ -1389,46 +1408,75 @@ ar5k_ar5212_procTxDesc(hal, desc)
 	tx_status = (struct ar5k_ar5212_tx_status*)&desc->ds_hw[2];
 
 	/* No frame has been send or error */
-	if (tx_status->done == 0)
+	if ((tx_status->tx_status_1 & AR5K_AR5212_DESC_TX_STATUS1_DONE) == 0)
 		return (HAL_EINPROGRESS);
 
 	/*
 	 * Get descriptor status
 	 */
-	desc->ds_us.tx.ts_seqnum = tx_status->seq_num;
-	desc->ds_us.tx.ts_tstamp = tx_status->send_timestamp;
-	desc->ds_us.tx.ts_shortretry = tx_status->rts_fail_count;
-	desc->ds_us.tx.ts_longretry = tx_status->data_fail_count;
-	desc->ds_us.tx.ts_rssi = tx_status->ack_sig_strength;
-	desc->ds_us.tx.ts_antenna = tx_status->xmit_antenna ? 2 : 1;
+	desc->ds_us.tx.ts_tstamp =
+	    AR5K_REG_MS(tx_status->tx_status_0,
+	    AR5K_AR5212_DESC_TX_STATUS0_SEND_TIMESTAMP);
+	desc->ds_us.tx.ts_shortretry =
+	    AR5K_REG_MS(tx_status->tx_status_0,
+	    AR5K_AR5212_DESC_TX_STATUS0_RTS_FAIL_COUNT);
+	desc->ds_us.tx.ts_longretry =
+	    AR5K_REG_MS(tx_status->tx_status_0,
+	    AR5K_AR5212_DESC_TX_STATUS0_DATA_FAIL_COUNT);
+	desc->ds_us.tx.ts_seqnum =
+	    AR5K_REG_MS(tx_status->tx_status_1,
+	    AR5K_AR5212_DESC_TX_STATUS1_SEQ_NUM);
+	desc->ds_us.tx.ts_rssi =
+	    AR5K_REG_MS(tx_status->tx_status_1,
+	    AR5K_AR5212_DESC_TX_STATUS1_ACK_SIG_STRENGTH);
+	desc->ds_us.tx.ts_antenna = (tx_status->tx_status_1 &
+	    AR5K_AR5212_DESC_TX_STATUS1_XMIT_ANTENNA) ? 2 : 1;
 	desc->ds_us.tx.ts_status = 0;
 
-	switch (tx_status->final_ts_index) {
+	switch (AR5K_REG_MS(tx_status->tx_status_1,
+	    AR5K_AR5212_DESC_TX_STATUS1_FINAL_TS_INDEX)) {
 	case 0:
-		desc->ds_us.tx.ts_rate = tx_desc->xmit_rate0;
+		desc->ds_us.tx.ts_rate = tx_desc->tx_control_3 &
+		    AR5K_AR5212_DESC_TX_CTL3_XMIT_RATE0;
 		break;
 	case 1:
-		desc->ds_us.tx.ts_rate = tx_desc->xmit_rate1;
-		desc->ds_us.tx.ts_longretry += tx_desc->xmit_tries0;
+		desc->ds_us.tx.ts_rate =
+		    AR5K_REG_MS(tx_desc->tx_control_3,
+		    AR5K_AR5212_DESC_TX_CTL3_XMIT_RATE1);
+		desc->ds_us.tx.ts_longretry +=
+		    AR5K_REG_MS(tx_desc->tx_control_2,
+		    AR5K_AR5212_DESC_TX_CTL2_XMIT_TRIES1);
 		break;
 	case 2:
-		desc->ds_us.tx.ts_rate = tx_desc->xmit_rate2;
-		desc->ds_us.tx.ts_longretry += tx_desc->xmit_tries1;
+		desc->ds_us.tx.ts_rate =
+		    AR5K_REG_MS(tx_desc->tx_control_3,
+		    AR5K_AR5212_DESC_TX_CTL3_XMIT_RATE2);
+		desc->ds_us.tx.ts_longretry +=
+		    AR5K_REG_MS(tx_desc->tx_control_2,
+		    AR5K_AR5212_DESC_TX_CTL2_XMIT_TRIES2);
 		break;
 	case 3:
-		desc->ds_us.tx.ts_rate = tx_desc->xmit_rate3;
-		desc->ds_us.tx.ts_longretry += tx_desc->xmit_tries2;
+		desc->ds_us.tx.ts_rate =
+		    AR5K_REG_MS(tx_desc->tx_control_3,
+		    AR5K_AR5212_DESC_TX_CTL3_XMIT_RATE3);
+		desc->ds_us.tx.ts_longretry +=
+		    AR5K_REG_MS(tx_desc->tx_control_2,
+		    AR5K_AR5212_DESC_TX_CTL2_XMIT_TRIES3);
 		break;
 	}
 
-	if (tx_status->frame_xmit_ok == 0) {
-		if (tx_status->excessive_retries)
+	if ((tx_status->tx_status_0 &
+	    AR5K_AR5212_DESC_TX_STATUS0_FRAME_XMIT_OK) == 0) {
+		if (tx_status->tx_status_0 &
+		    AR5K_AR5212_DESC_TX_STATUS0_EXCESSIVE_RETRIES)
 			desc->ds_us.tx.ts_status |= HAL_TXERR_XRETRY;
 
-		if (tx_status->fifo_underrun)
+		if (tx_status->tx_status_0 &
+		    AR5K_AR5212_DESC_TX_STATUS0_FIFO_UNDERRUN)
 			desc->ds_us.tx.ts_status |= HAL_TXERR_FIFO;
 
-		if (tx_status->filtered)
+		if (tx_status->tx_status_0 &
+		    AR5K_AR5212_DESC_TX_STATUS0_FILTERED)
 			desc->ds_us.tx.ts_status |= HAL_TXERR_FILT;
 	}
 
@@ -1601,18 +1649,14 @@ ar5k_ar5212_setupRxDesc(hal, desc, size, flags)
 {
 	struct ar5k_ar5212_rx_desc *rx_desc;
 
-	/* Reset descriptor */
-	desc->ds_ctl0 = 0;
-	desc->ds_ctl1 = 0;
-	bzero(&desc->ds_hw[0], sizeof(struct ar5k_ar5212_rx_status));
-
 	rx_desc = (struct ar5k_ar5212_rx_desc*)&desc->ds_ctl0;
 
-	if ((rx_desc->buf_len = size) != size)
+	if ((rx_desc->rx_control_1 = (size &
+	    AR5K_AR5212_DESC_RX_CTL1_BUF_LEN)) != size)
 		return (AH_FALSE);
 
 	if (flags & HAL_RXDESC_INTREQ)
-		rx_desc->inter_req = 1;
+		rx_desc->rx_control_1 |= AR5K_AR5212_DESC_RX_CTL1_INTREQ;
 
 	return (AH_TRUE);
 }
@@ -1624,56 +1668,73 @@ ar5k_ar5212_procRxDesc(hal, desc, phys_addr, next)
 	u_int32_t phys_addr;
 	struct ath_desc *next;
 {
-	u_int32_t now, tstamp;
 	struct ar5k_ar5212_rx_status *rx_status;
+	struct ar5k_ar5212_rx_error *rx_err;
 
 	rx_status = (struct ar5k_ar5212_rx_status*)&desc->ds_hw[0];
 
+	/* Overlay on error */
+	rx_err = (struct ar5k_ar5212_rx_error*)&desc->ds_hw[0];
+
 	/* No frame received / not ready */
-	if (!rx_status->done)
+	if ((rx_status->rx_status_1 & AR5K_AR5212_DESC_RX_STATUS1_DONE) == 0)
 		return (HAL_EINPROGRESS);
 
 	/*
 	 * Frame receive status
 	 */
-	now = (AR5K_REG_READ(AR5K_AR5212_TSF_L32) >> 10) & 0xffff;
-	tstamp = ((now & 0x1fff) < rx_status->receive_timestamp) ?
-	    (((now - 0x2000) & 0xffff) |
-	    (u_int32_t)rx_status->receive_timestamp) :
-	    (now | (u_int32_t)rx_status->receive_timestamp);
-	desc->ds_us.rx.rs_tstamp = rx_status->receive_timestamp & 0x7fff;
-	desc->ds_us.rx.rs_datalen = rx_status->data_len;
-	desc->ds_us.rx.rs_rssi = rx_status->receive_sig_strength;
-	desc->ds_us.rx.rs_rate = rx_status->receive_rate;
-	desc->ds_us.rx.rs_antenna = rx_status->receive_antenna ? 1 : 0;
-	desc->ds_us.rx.rs_more = rx_status->more ? 1 : 0;
+	desc->ds_us.rx.rs_datalen = rx_status->rx_status_0 &
+	    AR5K_AR5212_DESC_RX_STATUS0_DATA_LEN;
+	desc->ds_us.rx.rs_rssi =
+	    AR5K_REG_MS(rx_status->rx_status_0,
+	    AR5K_AR5212_DESC_RX_STATUS0_RECEIVE_SIGNAL);
+	desc->ds_us.rx.rs_rate =
+	    AR5K_REG_MS(rx_status->rx_status_0,
+	    AR5K_AR5212_DESC_RX_STATUS0_RECEIVE_RATE);
+	desc->ds_us.rx.rs_antenna = rx_status->rx_status_0 &
+	    AR5K_AR5212_DESC_RX_STATUS0_RECEIVE_ANTENNA;
+	desc->ds_us.rx.rs_more = rx_status->rx_status_0 &
+	    AR5K_AR5212_DESC_RX_STATUS0_MORE;
+	desc->ds_us.rx.rs_tstamp =
+	    AR5K_REG_MS(rx_status->rx_status_1,
+	    AR5K_AR5212_DESC_RX_STATUS1_RECEIVE_TIMESTAMP);
 	desc->ds_us.rx.rs_status = 0;
 
 	/*
 	 * Key table status
 	 */
-	if (!rx_status->key_index_valid) {
-		desc->ds_us.rx.rs_keyix = HAL_RXKEYIX_INVALID;
+	if (rx_status->rx_status_1 &
+	    AR5K_AR5212_DESC_RX_STATUS1_KEY_INDEX_VALID) {
+		desc->ds_us.rx.rs_keyix =
+		    AR5K_REG_MS(rx_status->rx_status_1,
+		    AR5K_AR5212_DESC_RX_STATUS1_KEY_INDEX);
 	} else {
-		desc->ds_us.rx.rs_keyix = rx_status->key_index;
+		desc->ds_us.rx.rs_keyix = HAL_RXKEYIX_INVALID;
 	}
 
 	/*
 	 * Receive/descriptor errors
 	 */
-	if (!rx_status->frame_receive_ok) {
-		if (rx_status->crc_error)
+	if ((rx_status->rx_status_1 &
+	    AR5K_AR5212_DESC_RX_STATUS1_FRAME_RECEIVE_OK) == 0) {
+		if (rx_status->rx_status_1 &
+		    AR5K_AR5212_DESC_RX_STATUS1_CRC_ERROR)
 			desc->ds_us.rx.rs_status |= HAL_RXERR_CRC;
 
-		if (rx_status->phy_error) {
+		if (rx_status->rx_status_1 &
+		    AR5K_AR5212_DESC_RX_STATUS1_PHY_ERROR) {
 			desc->ds_us.rx.rs_status |= HAL_RXERR_PHY;
-			desc->ds_us.rx.rs_phyerr = rx_status->phy_error;
+			desc->ds_us.rx.rs_phyerr =
+			    AR5K_REG_MS(rx_err->rx_error_1,
+			    AR5K_AR5212_DESC_RX_ERROR1_PHY_ERROR_CODE);
 		}
 
-		if (rx_status->decrypt_crc_error)
+		if (rx_status->rx_status_1 &
+		    AR5K_AR5212_DESC_RX_STATUS1_DECRYPT_CRC_ERROR)
 			desc->ds_us.rx.rs_status |= HAL_RXERR_DECRYPT;
 
-		if (rx_status->mic_error)
+		if (rx_status->rx_status_1 &
+		    AR5K_AR5212_DESC_RX_STATUS1_MIC_ERROR)
 			desc->ds_us.rx.rs_status |= HAL_RXERR_MIC;
 	}
 
diff --git a/sys/dev/ic/ar5212var.h b/sys/dev/ic/ar5212var.h
index 76c0d8033d7..d4c5c1a6aed 100644
--- a/sys/dev/ic/ar5212var.h
+++ b/sys/dev/ic/ar5212var.h
@@ -1,4 +1,4 @@
-/*	$OpenBSD: ar5212var.h,v 1.4 2005/03/20 04:21:55 reyk Exp $	*/
+/*	$OpenBSD: ar5212var.h,v 1.5 2005/04/08 22:02:49 reyk Exp $	*/
 
 /*
  * Copyright (c) 2004, 2005 Reyk Floeter <reyk@vantronix.net>
@@ -50,59 +50,71 @@
 
 struct ar5k_ar5212_rx_desc {
 	/*
-	 * rx_control_0
+	 * RX control word 0
 	 */
-	u_int32_t	reserved:32;
+	u_int32_t	rx_control_0;
+
+#define AR5K_AR5212_DESC_RX_CTL0			0x00000000
 
 	/*
-	 * rx_control_1
+	 * RX control word 1
 	 */
-	u_int32_t	buf_len:12;
-	u_int32_t	reserved_12:1;
-	u_int32_t	inter_req:1;
-	u_int32_t	reserved_14_31:18;
+	u_int32_t	rx_control_1;
+
+#define AR5K_AR5212_DESC_RX_CTL1_BUF_LEN		0x00000fff
+#define AR5K_AR5212_DESC_RX_CTL1_INTREQ			0x00002000
 } __packed;
 
 struct ar5k_ar5212_rx_status {
 	/*
-	 * rx_status_0
+	 * RX status word 0
 	 */
-	u_int32_t	data_len:12;
-	u_int32_t	more:1;
-	u_int32_t	decomp_crc_error:1;
-	u_int32_t	reserved_14:1;
-	u_int32_t	receive_rate:5;
-	u_int32_t	receive_sig_strength:8;
-	u_int32_t	receive_antenna:4;
+	u_int32_t	rx_status_0;
+	
+#define AR5K_AR5212_DESC_RX_STATUS0_DATA_LEN		0x00000fff
+#define AR5K_AR5212_DESC_RX_STATUS0_MORE		0x00001000
+#define AR5K_AR5212_DESC_RX_STATUS0_DECOMP_CRC_ERROR	0x00002000
+#define AR5K_AR5212_DESC_RX_STATUS0_RECEIVE_RATE	0x000f8000
+#define AR5K_AR5212_DESC_RX_STATUS0_RECEIVE_RATE_S	15
+#define AR5K_AR5212_DESC_RX_STATUS0_RECEIVE_SIGNAL	0x0ff00000
+#define AR5K_AR5212_DESC_RX_STATUS0_RECEIVE_SIGNAL_S	20
+#define AR5K_AR5212_DESC_RX_STATUS0_RECEIVE_ANTENNA	0xf0000000
+#define AR5K_AR5212_DESC_RX_STATUS0_RECEIVE_ANTENNA_S	28
 
 	/*
-	 * rx_status_1
+	 * RX status word 1
 	 */
-	u_int32_t	done:1;
-	u_int32_t	frame_receive_ok:1;
-	u_int32_t	crc_error:1;
-	u_int32_t	decrypt_crc_error:1;
-	u_int32_t	phy_error:1;
-	u_int32_t	mic_error:1;
-	u_int32_t	reserved_6_7:2;
-	u_int32_t	key_index_valid:1;
-	u_int32_t	key_index:7;
-	u_int32_t	receive_timestamp:15;
-	u_int32_t	key_cache_miss:1;
+	u_int32_t	rx_status_1;
+
+#define AR5K_AR5212_DESC_RX_STATUS1_DONE		0x00000001
+#define AR5K_AR5212_DESC_RX_STATUS1_FRAME_RECEIVE_OK	0x00000002
+#define AR5K_AR5212_DESC_RX_STATUS1_CRC_ERROR		0x00000004
+#define AR5K_AR5212_DESC_RX_STATUS1_DECRYPT_CRC_ERROR	0x00000008
+#define AR5K_AR5212_DESC_RX_STATUS1_PHY_ERROR		0x00000010
+#define AR5K_AR5212_DESC_RX_STATUS1_MIC_ERROR		0x00000020
+#define AR5K_AR5212_DESC_RX_STATUS1_KEY_INDEX_VALID	0x00000100
+#define AR5K_AR5212_DESC_RX_STATUS1_KEY_INDEX		0x0000fe00
+#define AR5K_AR5212_DESC_RX_STATUS1_KEY_INDEX_S		9
+#define AR5K_AR5212_DESC_RX_STATUS1_RECEIVE_TIMESTAMP	0x7fff0000
+#define AR5K_AR5212_DESC_RX_STATUS1_RECEIVE_TIMESTAMP_S	16
+#define AR5K_AR5212_DESC_RX_STATUS1_KEY_CACHE_MISS	0x80000000
 } __packed;
 
 struct ar5k_ar5212_rx_error {
 	/*
-	 * rx_error_0
+	 * RX error word 0
 	 */
-	u_int32_t	reserved:32;
+	u_int32_t	rx_error_0;
+
+#define AR5K_AR5212_DESC_RX_ERROR0			0x00000000
 
 	/*
-	 * rx_error_1
+	 * RX error word 1
 	 */
-	u_int32_t	reserved_1_7:8;
-	u_int32_t	phy_error_code:8;
-	u_int32_t	reserved_16_31:16;
+	u_int32_t	rx_error_1;
+
+#define AR5K_AR5212_DESC_RX_ERROR1_PHY_ERROR_CODE	0x0000ff00
+#define AR5K_AR5212_DESC_RX_ERROR1_PHY_ERROR_CODE_S	8
 } __packed;
 
 #define AR5K_AR5212_DESC_RX_PHY_ERROR_NONE		0x00
@@ -116,91 +128,106 @@ struct ar5k_ar5212_rx_error {
 
 struct ar5k_ar5212_tx_desc {
 	/*
-	 * tx_control_0
+	 * TX control word 0
 	 */
-	u_int32_t	frame_len:12;
-	u_int32_t	reserved_12_15:4;
-	u_int32_t	xmit_power:6;
-	u_int32_t	rts_cts_enable:1;
-	u_int32_t	veol:1;
-	u_int32_t	clear_dest_mask:1;
-	u_int32_t	ant_mode_xmit:4;
-	u_int32_t	inter_req:1;
-	u_int32_t	encrypt_key_valid:1;
-	u_int32_t	cts_enable:1;
+	u_int32_t	tx_control_0;
+
+#define AR5K_AR5212_DESC_TX_CTL0_FRAME_LEN		0x00000fff
+#define AR5K_AR5212_DESC_TX_CTL0_XMIT_POWER		0x003f0000
+#define AR5K_AR5212_DESC_TX_CTL0_XMIT_POWER_S		16
+#define AR5K_AR5212_DESC_TX_CTL0_RTSENA			0x00400000
+#define AR5K_AR5212_DESC_TX_CTL0_VEOL			0x00800000
+#define AR5K_AR5212_DESC_TX_CTL0_CLRDMASK		0x01000000
+#define AR5K_AR5212_DESC_TX_CTL0_ANT_MODE_XMIT		0x1e000000
+#define AR5K_AR5212_DESC_TX_CTL0_ANT_MODE_XMIT_S	25
+#define AR5K_AR5212_DESC_TX_CTL0_INTREQ			0x20000000
+#define AR5K_AR5212_DESC_TX_CTL0_ENCRYPT_KEY_VALID	0x40000000
+#define AR5K_AR5212_DESC_TX_CTL0_CTSENA			0x80000000
 
 	/*
-	 * tx_control_1
+	 * TX control word 1
 	 */
-	u_int32_t	buf_len:12;
-	u_int32_t	more:1;
-	u_int32_t	encrypt_key_index:7;
-	u_int32_t	frame_type:4;
-	u_int32_t	no_ack:1;
-	u_int32_t	comp_proc:2;
-	u_int32_t	comp_iv_len:2;
-	u_int32_t	comp_icv_len:2;
-	u_int32_t	reserved_31:1;
+	u_int32_t	tx_control_1;
+
+#define AR5K_AR5212_DESC_TX_CTL1_BUF_LEN		0x00000fff
+#define AR5K_AR5212_DESC_TX_CTL1_MORE			0x00001000
+#define AR5K_AR5212_DESC_TX_CTL1_ENCRYPT_KEY_INDEX	0x000fe000
+#define AR5K_AR5212_DESC_TX_CTL1_ENCRYPT_KEY_INDEX_S	13
+#define AR5K_AR5212_DESC_TX_CTL1_FRAME_TYPE		0x00f00000
+#define AR5K_AR5212_DESC_TX_CTL1_FRAME_TYPE_S		20
+#define AR5K_AR5212_DESC_TX_CTL1_NOACK			0x01000000
+#define AR5K_AR5212_DESC_TX_CTL1_COMP_PROC		0x06000000
+#define AR5K_AR5212_DESC_TX_CTL1_COMP_PROC_S		25
+#define AR5K_AR5212_DESC_TX_CTL1_COMP_IV_LEN		0x18000000
+#define AR5K_AR5212_DESC_TX_CTL1_COMP_IV_LEN_S		27
+#define AR5K_AR5212_DESC_TX_CTL1_COMP_ICV_LEN		0x60000000
+#define AR5K_AR5212_DESC_TX_CTL1_COMP_ICV_LEN_S		29
 
 	/*
-	 * tx_control_2
+	 * TX control word 2
 	 */
-	u_int32_t	rts_duration:15;
-	u_int32_t	duration_update_enable:1;
-	u_int32_t	xmit_tries0:4;
-	u_int32_t	xmit_tries1:4;
-	u_int32_t	xmit_tries2:4;
-	u_int32_t	xmit_tries3:4;
+	u_int32_t	tx_control_2;
+
+#define AR5K_AR5212_DESC_TX_CTL2_RTS_DURATION		0x00007fff
+#define AR5K_AR5212_DESC_TX_CTL2_DURATION_UPDATE_ENABLE	0x00008000
+#define AR5K_AR5212_DESC_TX_CTL2_XMIT_TRIES0		0x000f0000
+#define AR5K_AR5212_DESC_TX_CTL2_XMIT_TRIES0_S		16
+#define AR5K_AR5212_DESC_TX_CTL2_XMIT_TRIES1		0x00f00000
+#define AR5K_AR5212_DESC_TX_CTL2_XMIT_TRIES1_S		20
+#define AR5K_AR5212_DESC_TX_CTL2_XMIT_TRIES2		0x0f000000
+#define AR5K_AR5212_DESC_TX_CTL2_XMIT_TRIES2_S		24
+#define AR5K_AR5212_DESC_TX_CTL2_XMIT_TRIES3		0xf0000000
+#define AR5K_AR5212_DESC_TX_CTL2_XMIT_TRIES3_S		28
 
 	/*
-	 * tx_control_3
+	 * TX control word 3
 	 */
-	u_int32_t	xmit_rate0:5;
-	u_int32_t	xmit_rate1:5;
-	u_int32_t	xmit_rate2:5;
-	u_int32_t	xmit_rate3:5;
-	u_int32_t	rts_cts_rate:5;
-	u_int32_t	reserved_25_31:7;
-} __packed;
+	u_int32_t	tx_control_3;
 
-#define AR5K_AR5212_DESC_TX_XMIT_RATE_6		0xb
-#define AR5K_AR5212_DESC_TX_XMIT_RATE_9		0xf
-#define AR5K_AR5212_DESC_TX_XMIT_RATE_12	0xa
-#define AR5K_AR5212_DESC_TX_XMIT_RATE_18	0xe
-#define AR5K_AR5212_DESC_TX_XMIT_RATE_24	0x9
-#define AR5K_AR5212_DESC_TX_XMIT_RATE_36	0xd
-#define AR5K_AR5212_DESC_TX_XMIT_RATE_48	0x8
-#define AR5K_AR5212_DESC_TX_XMIT_RATE_54	0xc
-
-#define AR5K_AR5212_DESC_TX_FRAME_TYPE_NORMAL	0x00
-#define AR5K_AR5212_DESC_TX_FRAME_TYPE_ATIM	0x04
-#define AR5K_AR5212_DESC_TX_FRAME_TYPE_PSPOLL	0x08
-#define AR5K_AR5212_DESC_TX_FRAME_TYPE_NO_DELAY 0x0c
-#define AR5K_AR5212_DESC_TX_FRAME_TYPE_PIFS	0x10
+#define AR5K_AR5212_DESC_TX_CTL3_XMIT_RATE0		0x0000001f
+#define AR5K_AR5212_DESC_TX_CTL3_XMIT_RATE1		0x000003e0
+#define AR5K_AR5212_DESC_TX_CTL3_XMIT_RATE1_S		5
+#define AR5K_AR5212_DESC_TX_CTL3_XMIT_RATE2		0x00007c00
+#define AR5K_AR5212_DESC_TX_CTL3_XMIT_RATE2_S		10
+#define AR5K_AR5212_DESC_TX_CTL3_XMIT_RATE3		0x000f8000
+#define AR5K_AR5212_DESC_TX_CTL3_XMIT_RATE3_S		15
+#define AR5K_AR5212_DESC_TX_CTL3_RTS_CTS_RATE		0x01f00000
+#define AR5K_AR5212_DESC_TX_CTL3_RTS_CTS_RATE_S		20
+} __packed;
 
 struct ar5k_ar5212_tx_status {
 	/*
-	 * tx_status_0
+	 * TX status word 0
 	 */
-	u_int32_t	frame_xmit_ok:1;
-	u_int32_t	excessive_retries:1;
-	u_int32_t	fifo_underrun:1;
-	u_int32_t	filtered:1;
-	u_int32_t	rts_fail_count:4;
-	u_int32_t	data_fail_count:4;
-	u_int32_t	virt_coll_count:4;
-	u_int32_t	send_timestamp:16;
+	u_int32_t	tx_status_0;
+
+#define AR5K_AR5212_DESC_TX_STATUS0_FRAME_XMIT_OK	0x00000001
+#define AR5K_AR5212_DESC_TX_STATUS0_EXCESSIVE_RETRIES	0x00000002
+#define AR5K_AR5212_DESC_TX_STATUS0_FIFO_UNDERRUN	0x00000004
+#define AR5K_AR5212_DESC_TX_STATUS0_FILTERED		0x00000008
+#define AR5K_AR5212_DESC_TX_STATUS0_RTS_FAIL_COUNT	0x000000f0
+#define AR5K_AR5212_DESC_TX_STATUS0_RTS_FAIL_COUNT_S	4
+#define AR5K_AR5212_DESC_TX_STATUS0_DATA_FAIL_COUNT	0x00000f00
+#define AR5K_AR5212_DESC_TX_STATUS0_DATA_FAIL_COUNT_S	8
+#define AR5K_AR5212_DESC_TX_STATUS0_VIRT_COLL_COUNT	0x0000f000
+#define AR5K_AR5212_DESC_TX_STATUS0_VIRT_COLL_COUNT_S	12
+#define AR5K_AR5212_DESC_TX_STATUS0_SEND_TIMESTAMP	0xffff0000
+#define AR5K_AR5212_DESC_TX_STATUS0_SEND_TIMESTAMP_S	16
 
 	/*
-	 * tx_status_1
+	 * TX status word 1
 	 */
-	u_int32_t	done:1;
-	u_int32_t	seq_num:12;
-	u_int32_t	ack_sig_strength:8;
-	u_int32_t	final_ts_index:2;
-	u_int32_t	comp_success:1;
-	u_int32_t	xmit_antenna:1;
-	u_int32_t	reserved_25_31:7;
+	u_int32_t	tx_status_1;
+
+#define AR5K_AR5212_DESC_TX_STATUS1_DONE		0x00000001
+#define AR5K_AR5212_DESC_TX_STATUS1_SEQ_NUM		0x00001ffe
+#define AR5K_AR5212_DESC_TX_STATUS1_SEQ_NUM_S		1
+#define AR5K_AR5212_DESC_TX_STATUS1_ACK_SIG_STRENGTH	0x001fe000
+#define AR5K_AR5212_DESC_TX_STATUS1_ACK_SIG_STRENGTH_S	13
+#define AR5K_AR5212_DESC_TX_STATUS1_FINAL_TS_INDEX	0x00600000
+#define AR5K_AR5212_DESC_TX_STATUS1_FINAL_TS_INDEX_S	21
+#define AR5K_AR5212_DESC_TX_STATUS1_COMP_SUCCESS	0x00800000
+#define AR5K_AR5212_DESC_TX_STATUS1_XMIT_ANTENNA	0x01000000
 } __packed;
 
 /*
diff --git a/sys/dev/ic/ar5xxx.h b/sys/dev/ic/ar5xxx.h
index b0a3460f083..fbf9299463b 100644
--- a/sys/dev/ic/ar5xxx.h
+++ b/sys/dev/ic/ar5xxx.h
@@ -1,4 +1,4 @@
-/*	$OpenBSD: ar5xxx.h,v 1.16 2005/04/06 09:14:53 reyk Exp $	*/
+/*	$OpenBSD: ar5xxx.h,v 1.17 2005/04/08 22:02:49 reyk Exp $	*/
 
 /*
  * Copyright (c) 2004, 2005 Reyk Floeter <reyk@vantronix.net>
@@ -171,11 +171,11 @@ typedef struct {
 
 typedef enum {
 	HAL_PKT_TYPE_NORMAL = 0,
-	HAL_PKT_TYPE_ATIM,
-	HAL_PKT_TYPE_PSPOLL,
-	HAL_PKT_TYPE_BEACON,
-	HAL_PKT_TYPE_PROBE_RESP,
-	HAL_PKT_TYPE_PIFS,
+	HAL_PKT_TYPE_ATIM = 1,
+	HAL_PKT_TYPE_PSPOLL = 2,
+	HAL_PKT_TYPE_BEACON = 3,
+	HAL_PKT_TYPE_PROBE_RESP = 4,
+	HAL_PKT_TYPE_PIFS = 5,
 } HAL_PKT_TYPE;
 
 /*