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authorMiod Vallat <miod@cvs.openbsd.org>2006-01-09 23:11:50 +0000
committerMiod Vallat <miod@cvs.openbsd.org>2006-01-09 23:11:50 +0000
commitd64ef5326fb80790bc0d1c6351a9da8d3faa6ed1 (patch)
tree9c02a27179b25ad9d0991b4828f49e587bab6226 /sys/dev/ic
parentb2acda502157990a13e7fcf66be5bc8b96592861 (diff)
Delay a bit after sending a reset command if the chip is an 53C94 or a 53C96;
ok deraadt@ krw@
Diffstat (limited to 'sys/dev/ic')
-rw-r--r--sys/dev/ic/ncr53c9x.c16
1 files changed, 15 insertions, 1 deletions
diff --git a/sys/dev/ic/ncr53c9x.c b/sys/dev/ic/ncr53c9x.c
index 6744be1db24..4d0d5f3d921 100644
--- a/sys/dev/ic/ncr53c9x.c
+++ b/sys/dev/ic/ncr53c9x.c
@@ -1,4 +1,4 @@
-/* $OpenBSD: ncr53c9x.c,v 1.28 2006/01/09 23:09:41 brad Exp $ */
+/* $OpenBSD: ncr53c9x.c,v 1.29 2006/01/09 23:11:49 miod Exp $ */
/* $NetBSD: ncr53c9x.c,v 1.56 2000/11/30 14:41:46 thorpej Exp $ */
/*
@@ -442,6 +442,20 @@ ncr53c9x_init(sc, doreset)
if (doreset) {
sc->sc_state = NCR_SBR;
NCRCMD(sc, NCRCMD_RSTSCSI);
+ /*
+ * XXX gross...
+ * On some systems, commands issued too close to a reset
+ * do not work correctly. We'll force a short delay on
+ * known-to-be-sensitive chips.
+ */
+ switch (sc->sc_rev) {
+ case NCR_VARIANT_NCR53C94:
+ DELAY(600000); /* 600ms */
+ break;
+ case NCR_VARIANT_NCR53C96:
+ DELAY(100000); /* 100ms */
+ break;
+ }
} else {
sc->sc_state = NCR_IDLE;
ncr53c9x_sched(sc);