diff options
| author | Jonathan Matthew <jmatthew@cvs.openbsd.org> | 2024-04-25 08:51:38 +0000 |
|---|---|---|
| committer | Jonathan Matthew <jmatthew@cvs.openbsd.org> | 2024-04-25 08:51:38 +0000 |
| commit | de3375a164a10080de4e2200e24814b4f03361f8 (patch) | |
| tree | dbb7827bf9e2637bc6a7ea316ffd8dc249c7082a /sys/dev/ic | |
| parent | 78d2bd22742dad046486f1ad9a5d4b8efed20fa7 (diff) | |
Mask off MAC management counter interrupts. The driver doesn't know how
to handle these, so if they're enabled, they will cause an interrupt
storm.
ok patrick@ jsg@ stsp@
Diffstat (limited to 'sys/dev/ic')
| -rw-r--r-- | sys/dev/ic/dwqe.c | 4 | ||||
| -rw-r--r-- | sys/dev/ic/dwqereg.h | 4 |
2 files changed, 6 insertions, 2 deletions
diff --git a/sys/dev/ic/dwqe.c b/sys/dev/ic/dwqe.c index 0467a4c7247..3e9f6569240 100644 --- a/sys/dev/ic/dwqe.c +++ b/sys/dev/ic/dwqe.c @@ -1,4 +1,4 @@ -/* $OpenBSD: dwqe.c,v 1.18 2024/03/29 08:19:40 stsp Exp $ */ +/* $OpenBSD: dwqe.c,v 1.19 2024/04/25 08:51:37 jmatthew Exp $ */ /* * Copyright (c) 2008, 2019 Mark Kettenis <kettenis@openbsd.org> * Copyright (c) 2017, 2022 Patrick Wildt <patrick@blueri.se> @@ -213,6 +213,8 @@ dwqe_attach(struct dwqe_softc *sc) /* Disable interrupts. */ dwqe_write(sc, GMAC_INT_EN, 0); dwqe_write(sc, GMAC_CHAN_INTR_ENA(0), 0); + dwqe_write(sc, GMAC_MMC_RX_INT_MASK, 0xffffffff); + dwqe_write(sc, GMAC_MMC_TX_INT_MASK, 0xffffffff); return 0; } diff --git a/sys/dev/ic/dwqereg.h b/sys/dev/ic/dwqereg.h index bc6de32a5a5..7f44de46d92 100644 --- a/sys/dev/ic/dwqereg.h +++ b/sys/dev/ic/dwqereg.h @@ -1,4 +1,4 @@ -/* $OpenBSD: dwqereg.h,v 1.5 2023/11/11 16:32:56 stsp Exp $ */ +/* $OpenBSD: dwqereg.h,v 1.6 2024/04/25 08:51:37 jmatthew Exp $ */ /* * Copyright (c) 2008, 2019 Mark Kettenis <kettenis@openbsd.org> * Copyright (c) 2017, 2022 Patrick Wildt <patrick@blueri.se> @@ -83,6 +83,8 @@ #define GMAC_MAC_MDIO_DATA 0x0204 #define GMAC_MAC_ADDR0_HI 0x0300 #define GMAC_MAC_ADDR0_LO 0x0304 +#define GMAC_MMC_RX_INT_MASK 0x070c +#define GMAC_MMC_TX_INT_MASK 0x0710 #define GMAC_MTL_OPERATION_MODE 0x0c00 #define GMAC_MTL_FRPE (1 << 15) |