diff options
| author | Damien Bergamini <damien@cvs.openbsd.org> | 2010-02-24 19:39:44 +0000 |
|---|---|---|
| committer | Damien Bergamini <damien@cvs.openbsd.org> | 2010-02-24 19:39:44 +0000 |
| commit | fd3b0b111c42854de582c577544c5265160b4597 (patch) | |
| tree | f5cadb98a9e9b47809a3b66767519fef84f51529 /sys/dev/ic | |
| parent | 5c35a88800d244a004fa56c06519ff0b806e16c4 (diff) | |
Disable Reduced Interframe Space search on AR9160 to workaround
baseband issues.
It would be cleaner to modify directly the initvals for AR9160 but
I want to keep the exact same initvals as the Linux ath9k driver.
from ath9k
Diffstat (limited to 'sys/dev/ic')
| -rw-r--r-- | sys/dev/ic/athn.c | 8 | ||||
| -rw-r--r-- | sys/dev/ic/athnreg.h | 7 |
2 files changed, 13 insertions, 2 deletions
diff --git a/sys/dev/ic/athn.c b/sys/dev/ic/athn.c index a6adeca58f7..30b08296919 100644 --- a/sys/dev/ic/athn.c +++ b/sys/dev/ic/athn.c @@ -1,4 +1,4 @@ -/* $OpenBSD: athn.c,v 1.26 2010/02/21 19:57:05 kettenis Exp $ */ +/* $OpenBSD: athn.c,v 1.27 2010/02/24 19:39:43 damien Exp $ */ /*- * Copyright (c) 2009 Damien Bergamini <damien.bergamini@free.fr> @@ -4032,6 +4032,12 @@ athn_hw_init(struct athn_softc *sc, struct ieee80211_channel *c, if (AR_SREV_5416_20_OR_LATER(sc) && !AR_SREV_9280_10_OR_LATER(sc)) { /* Disable baseband clock gating. */ AR_WRITE(sc, AR_PHY(651), 0x11); + + if (AR_SREV_9160(sc)) { + /* Disable RIFS search to fix baseband hang. */ + AR_CLRBITS(sc, AR_PHY_HEAVY_CLIP_FACTOR_RIFS, + AR_PHY_RIFS_INIT_DELAY_M); + } } athn_set_phy(sc, c, extc); diff --git a/sys/dev/ic/athnreg.h b/sys/dev/ic/athnreg.h index 6da84a60077..7a0f476b48e 100644 --- a/sys/dev/ic/athnreg.h +++ b/sys/dev/ic/athnreg.h @@ -1,4 +1,4 @@ -/* $OpenBSD: athnreg.h,v 1.5 2010/02/24 19:31:29 damien Exp $ */ +/* $OpenBSD: athnreg.h,v 1.6 2010/02/24 19:39:43 damien Exp $ */ /*- * Copyright (c) 2009 Damien Bergamini <damien.bergamini@free.fr> @@ -328,6 +328,7 @@ #define AR_PHY_CHANNEL_MASK_31_60 0x99d8 #define AR_PHY_CHAN_INFO_MEMORY 0x99dc #define AR_PHY_HEAVY_CLIP_ENABLE 0x99e0 +#define AR_PHY_HEAVY_CLIP_FACTOR_RIFS 0x99ec #define AR_PHY_CALMODE 0x99f0 #define AR_PHY_REFCLKDLY 0x99f4 #define AR_PHY_REFCLKPD 0x99f8 @@ -1695,6 +1696,10 @@ /* Bits for AR_PHY_CHAN_INFO_MEMORY. */ #define AR_PHY_CHAN_INFO_MEMORY_CAPTURE_MASK 0x0001 +/* Bits for AR_PHY_HEAVY_CLIP_FACTOR_RIFS. */ +#define AR_PHY_RIFS_INIT_DELAY_M 0x03ff0000 +#define AR_PHY_RIFS_INIT_DELAY_S 16 + /* Bits for AR_PHY_CALMODE. */ #define AR_PHY_CALMODE_IQ 0x00000000 #define AR_PHY_CALMODE_ADC_GAIN 0x00000001 |