diff options
| author | Jonathan Gray <jsg@cvs.openbsd.org> | 2020-03-06 00:16:16 +0000 |
|---|---|---|
| committer | Jonathan Gray <jsg@cvs.openbsd.org> | 2020-03-06 00:16:16 +0000 |
| commit | 9528a8d8e0fd69bb7abfbc397087dcd8fae12178 (patch) | |
| tree | 0ca7b38499d3ba54d0433a8a75e7d680914caa28 /sys/dev/pci/drm/amd | |
| parent | b275b88126c8a25ca3eb3b3ba42e3a2ef2d8ff19 (diff) | |
amdgpu/gmc_v9: save/restore sdpif regs during S3
From Shirish S
c47655fba16fa9a6af1c3eef997cf26bf2c92645 in linux 4.19.y/4.19.108
a3ed353cf8015ba84a0407a5dc3ffee038166ab0 in mainline linux
Diffstat (limited to 'sys/dev/pci/drm/amd')
| -rw-r--r-- | sys/dev/pci/drm/amd/amdgpu/amdgpu_gmc.h | 1 | ||||
| -rw-r--r-- | sys/dev/pci/drm/amd/amdgpu/gmc_v9_0.c | 37 | ||||
| -rw-r--r-- | sys/dev/pci/drm/amd/include/asic_reg/dce/dce_12_0_offset.h | 2 |
3 files changed, 39 insertions, 1 deletions
diff --git a/sys/dev/pci/drm/amd/amdgpu/amdgpu_gmc.h b/sys/dev/pci/drm/amd/amdgpu/amdgpu_gmc.h index bb5a47a4579..5c76a815396 100644 --- a/sys/dev/pci/drm/amd/amdgpu/amdgpu_gmc.h +++ b/sys/dev/pci/drm/amd/amdgpu/amdgpu_gmc.h @@ -97,6 +97,7 @@ struct amdgpu_gmc { uint32_t srbm_soft_reset; bool prt_warning; uint64_t stolen_size; + uint32_t sdpif_register; /* apertures */ u64 shared_aperture_start; u64 shared_aperture_end; diff --git a/sys/dev/pci/drm/amd/amdgpu/gmc_v9_0.c b/sys/dev/pci/drm/amd/amdgpu/gmc_v9_0.c index c76aff18e63..1e5157717db 100644 --- a/sys/dev/pci/drm/amd/amdgpu/gmc_v9_0.c +++ b/sys/dev/pci/drm/amd/amdgpu/gmc_v9_0.c @@ -997,6 +997,19 @@ static void gmc_v9_0_init_golden_registers(struct amdgpu_device *adev) } /** + * gmc_v9_0_restore_registers - restores regs + * + * @adev: amdgpu_device pointer + * + * This restores register values, saved at suspend. + */ +static void gmc_v9_0_restore_registers(struct amdgpu_device *adev) +{ + if (adev->asic_type == CHIP_RAVEN) + WREG32(mmDCHUBBUB_SDPIF_MMIO_CNTRL_0, adev->gmc.sdpif_register); +} + +/** * gmc_v9_0_gart_enable - gart enable * * @adev: amdgpu_device pointer @@ -1085,6 +1098,20 @@ static int gmc_v9_0_hw_init(void *handle) } /** + * gmc_v9_0_save_registers - saves regs + * + * @adev: amdgpu_device pointer + * + * This saves potential register values that should be + * restored upon resume + */ +static void gmc_v9_0_save_registers(struct amdgpu_device *adev) +{ + if (adev->asic_type == CHIP_RAVEN) + adev->gmc.sdpif_register = RREG32(mmDCHUBBUB_SDPIF_MMIO_CNTRL_0); +} + +/** * gmc_v9_0_gart_disable - gart disable * * @adev: amdgpu_device pointer @@ -1116,9 +1143,16 @@ static int gmc_v9_0_hw_fini(void *handle) static int gmc_v9_0_suspend(void *handle) { + int r; struct amdgpu_device *adev = (struct amdgpu_device *)handle; - return gmc_v9_0_hw_fini(adev); + r = gmc_v9_0_hw_fini(adev); + if (r) + return r; + + gmc_v9_0_save_registers(adev); + + return 0; } static int gmc_v9_0_resume(void *handle) @@ -1126,6 +1160,7 @@ static int gmc_v9_0_resume(void *handle) int r; struct amdgpu_device *adev = (struct amdgpu_device *)handle; + gmc_v9_0_restore_registers(adev); r = gmc_v9_0_hw_init(adev); if (r) return r; diff --git a/sys/dev/pci/drm/amd/include/asic_reg/dce/dce_12_0_offset.h b/sys/dev/pci/drm/amd/include/asic_reg/dce/dce_12_0_offset.h index b6f74bf4af0..27bb8c1ab85 100644 --- a/sys/dev/pci/drm/amd/include/asic_reg/dce/dce_12_0_offset.h +++ b/sys/dev/pci/drm/amd/include/asic_reg/dce/dce_12_0_offset.h @@ -7376,6 +7376,8 @@ #define mmCRTC4_CRTC_DRR_CONTROL 0x0f3e #define mmCRTC4_CRTC_DRR_CONTROL_BASE_IDX 2 +#define mmDCHUBBUB_SDPIF_MMIO_CNTRL_0 0x395d +#define mmDCHUBBUB_SDPIF_MMIO_CNTRL_0_BASE_IDX 2 // addressBlock: dce_dc_fmt4_dispdec // base address: 0x2000 |