A nice little performance speedup.

If we just read access to some data that has been accessed by the gpu,
only sleep until the end of the gpus last write (which we track). So
instead of stalling the gpu until the last time accessed, both can read
at the same time (which is allowed and coherent as long as the right
invalidation happens).

Since we check offsets from userland before we exec a batchbuffer, this
helps 965 (with lots of read only relocations in the render path) quite
a lot.

1 files changed, 1 insertions, 0 deletions

diff --git a/sys/dev/pci/drm/i915_drv.h b/sys/dev/pci/drm/i915_drv.h
index 0d887ed3972..ba62e0906a0 100644
--- a/sys/dev/pci/drm/i915_drv.h
+++ b/sys/dev/pci/drm/i915_drv.h
@@ -405,6 +405,7 @@ struct inteldrm_obj {
 
 	/** Breadcrumb of last rendering to the buffer. */
 	u_int32_t				 last_rendering_seqno;
+	u_int32_t				 last_write_seqno;
 	/** Current tiling mode for the object. */
 	u_int32_t				 tiling_mode;
 	u_int32_t				 stride;