diff options
| author | Jonathan Gray <jsg@cvs.openbsd.org> | 2023-01-01 01:35:01 +0000 |
|---|---|---|
| committer | Jonathan Gray <jsg@cvs.openbsd.org> | 2023-01-01 01:35:01 +0000 |
| commit | fcfd84245b0df2875817d742dfd88764e41c067a (patch) | |
| tree | 874f6e4c0574726d46b13836df04bb362da89c1a /sys/dev/pci/drm/radeon | |
| parent | 8f91af71e0ab43edc02fb4901e86daa2692d08a7 (diff) | |
update drm to linux 6.1.2
new hardware support includes
AMD
Raphael, Ryzen 7000 desktop, gfx1036/GC 10.3.6
Mendocino, Ryzen & Athlon 7020 Series mobile APU, gfx1037/GC 10.3.7
Navi 31, gfx1100 dGPU, GC 11.0.0, Radeon RX 7900 XT/XTX
gfx1101 dGPU
gfx1102 dGPU
gfx1103 APU
Thanks to the OpenBSD Foundation for sponsoring this work.
Diffstat (limited to 'sys/dev/pci/drm/radeon')
58 files changed, 1891 insertions, 3872 deletions
diff --git a/sys/dev/pci/drm/radeon/atom.c b/sys/dev/pci/drm/radeon/atom.c index 84e1713b7bc..90c80b0e8ac 100644 --- a/sys/dev/pci/drm/radeon/atom.c +++ b/sys/dev/pci/drm/radeon/atom.c @@ -25,6 +25,7 @@ #include <linux/module.h> #include <linux/sched.h> #include <linux/slab.h> +#include <linux/string_helpers.h> #include <asm/unaligned.h> @@ -726,7 +727,7 @@ static void atom_op_jump(atom_exec_context *ctx, int *ptr, int arg) break; } if (arg != ATOM_COND_ALWAYS) - SDEBUG(" taken: %s\n", execute ? "yes" : "no"); + SDEBUG(" taken: %s\n", str_yes_no(execute)); SDEBUG(" target: 0x%04X\n", target); if (execute) { if (ctx->last_jump == (ctx->start + target)) { diff --git a/sys/dev/pci/drm/radeon/atombios.h b/sys/dev/pci/drm/radeon/atombios.h index 83e8b8547f9..da35a970fcc 100644 --- a/sys/dev/pci/drm/radeon/atombios.h +++ b/sys/dev/pci/drm/radeon/atombios.h @@ -3599,7 +3599,7 @@ typedef struct _ATOM_LCD_RTS_RECORD UCHAR ucRTSValue; }ATOM_LCD_RTS_RECORD; -//!! If the record below exits, it shoud always be the first record for easy use in command table!!! +//!! If the record below exists, it should always be the first record for easy use in command table!!! // The record below is only used when LVDS_Info is present. From ATOM_LVDS_INFO_V12, use ucLCDPanel_SpecialHandlingCap instead. typedef struct _ATOM_LCD_MODE_CONTROL_CAP { @@ -3823,7 +3823,7 @@ typedef struct _ATOM_DPCD_INFO // Note1: This table is filled by SetBiosReservationStartInFB in CoreCommSubs.asm // at running time. // note2: From RV770, the memory is more than 32bit addressable, so we will change -// ucTableFormatRevision=1,ucTableContentRevision=4, the strcuture remains +// ucTableFormatRevision=1,ucTableContentRevision=4, the structure remains // exactly same as 1.1 and 1.2 (1.3 is never in use), but ulStartAddrUsedByFirmware // (in offset to start of memory address) is KB aligned instead of byte aligend. /***********************************************************************************/ @@ -3858,7 +3858,7 @@ typedef struct _ATOM_VRAM_USAGE_BY_FIRMWARE ATOM_FIRMWARE_VRAM_RESERVE_INFO asFirmwareVramReserveInfo[ATOM_MAX_FIRMWARE_VRAM_USAGE_INFO]; }ATOM_VRAM_USAGE_BY_FIRMWARE; -// change verion to 1.5, when allow driver to allocate the vram area for command table access. +// change version to 1.5, when allow driver to allocate the vram area for command table access. typedef struct _ATOM_FIRMWARE_VRAM_RESERVE_INFO_V1_5 { ULONG ulStartAddrUsedByFirmware; @@ -5973,7 +5973,7 @@ typedef struct _ATOM_ASIC_INTERNAL_SS_INFO_V3 #define CLEAR_ATOM_S7_DOS_8BIT_DAC_EN ((ATOM_DOS_MODE_INFO_DEF << 8 )|ATOM_S7_DOS_8BIT_DAC_EN_SHIFT | ATOM_FLAG_CLEAR ) /****************************************************************************/ -//Portion II: Definitinos only used in Driver +//Portion II: Definitions only used in Driver /****************************************************************************/ // Macros used by driver @@ -5983,7 +5983,7 @@ typedef struct _ATOM_ASIC_INTERNAL_SS_INFO_V3 #define GET_COMMAND_TABLE_COMMANDSET_REVISION(TABLE_HEADER_OFFSET) (((static_cast<ATOM_COMMON_TABLE_HEADER*>(TABLE_HEADER_OFFSET))->ucTableFormatRevision )&0x3F) #define GET_COMMAND_TABLE_PARAMETER_REVISION(TABLE_HEADER_OFFSET) (((static_cast<ATOM_COMMON_TABLE_HEADER*>(TABLE_HEADER_OFFSET))->ucTableContentRevision)&0x3F) #else // not __cplusplus -#define GetIndexIntoMasterTable(MasterOrData, FieldName) (((char*)(&((ATOM_MASTER_LIST_OF_##MasterOrData##_TABLES*)0)->FieldName)-(char*)0)/sizeof(USHORT)) +#define GetIndexIntoMasterTable(MasterOrData, FieldName) (offsetof(ATOM_MASTER_LIST_OF_##MasterOrData##_TABLES, FieldName)/sizeof(USHORT)) #define GET_COMMAND_TABLE_COMMANDSET_REVISION(TABLE_HEADER_OFFSET) ((((ATOM_COMMON_TABLE_HEADER*)TABLE_HEADER_OFFSET)->ucTableFormatRevision)&0x3F) #define GET_COMMAND_TABLE_PARAMETER_REVISION(TABLE_HEADER_OFFSET) ((((ATOM_COMMON_TABLE_HEADER*)TABLE_HEADER_OFFSET)->ucTableContentRevision)&0x3F) @@ -7162,7 +7162,7 @@ typedef struct _DP_ENCODER_SERVICE_PARAMETERS // ucAction #define ATOM_DP_ACTION_GET_SINK_TYPE 0x01 -/* obselete */ +/* obsolete */ #define ATOM_DP_ACTION_TRAINING_START 0x02 #define ATOM_DP_ACTION_TRAINING_COMPLETE 0x03 #define ATOM_DP_ACTION_TRAINING_PATTERN_SEL 0x04 diff --git a/sys/dev/pci/drm/radeon/atombios_crtc.c b/sys/dev/pci/drm/radeon/atombios_crtc.c index c94e429e75f..d28d3acb3ba 100644 --- a/sys/dev/pci/drm/radeon/atombios_crtc.c +++ b/sys/dev/pci/drm/radeon/atombios_crtc.c @@ -28,6 +28,7 @@ #include <drm/drm_fb_helper.h> #include <drm/drm_fixed.h> #include <drm/drm_fourcc.h> +#include <drm/drm_framebuffer.h> #include <drm/drm_vblank.h> #include <drm/radeon_drm.h> @@ -616,13 +617,6 @@ static u32 atombios_adjust_pll(struct drm_crtc *crtc, } } - if (radeon_encoder->is_mst_encoder) { - struct radeon_encoder_mst *mst_enc = radeon_encoder->enc_priv; - struct radeon_connector_atom_dig *dig_connector = mst_enc->connector->con_priv; - - dp_clock = dig_connector->dp_clock; - } - /* use recommended ref_div for ss */ if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) { if (radeon_crtc->ss_enabled) { @@ -971,9 +965,7 @@ static bool atombios_crtc_prepare_pll(struct drm_crtc *crtc, struct drm_display_ radeon_crtc->bpc = 8; radeon_crtc->ss_enabled = false; - if (radeon_encoder->is_mst_encoder) { - radeon_dp_mst_prepare_pll(crtc, mode); - } else if ((radeon_encoder->active_device & (ATOM_DEVICE_LCD_SUPPORT | ATOM_DEVICE_DFP_SUPPORT)) || + if ((radeon_encoder->active_device & (ATOM_DEVICE_LCD_SUPPORT | ATOM_DEVICE_DFP_SUPPORT)) || (radeon_encoder_get_dp_bridge_encoder_id(radeon_crtc->encoder) != ENCODER_OBJECT_ID_NONE)) { struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; struct drm_connector *connector = diff --git a/sys/dev/pci/drm/radeon/atombios_dp.c b/sys/dev/pci/drm/radeon/atombios_dp.c index cb601d31546..c6162176722 100644 --- a/sys/dev/pci/drm/radeon/atombios_dp.c +++ b/sys/dev/pci/drm/radeon/atombios_dp.c @@ -30,7 +30,7 @@ #include "atom.h" #include "atom-bits.h" -#include <drm/drm_dp_helper.h> +#include <drm/display/drm_dp_helper.h> /* move these to drm_dp_helper.c/h */ #define DP_LINK_CONFIGURATION_SIZE 9 diff --git a/sys/dev/pci/drm/radeon/atombios_encoders.c b/sys/dev/pci/drm/radeon/atombios_encoders.c index 70bd84b7ef2..c841c273222 100644 --- a/sys/dev/pci/drm/radeon/atombios_encoders.c +++ b/sys/dev/pci/drm/radeon/atombios_encoders.c @@ -32,6 +32,8 @@ #include <drm/drm_file.h> #include <drm/radeon_drm.h> +#include <acpi/video.h> + #include "atom.h" #include "radeon_atombios.h" #include "radeon.h" @@ -141,8 +143,6 @@ atombios_set_backlight_level(struct radeon_encoder *radeon_encoder, u8 level) } } -#if defined(CONFIG_BACKLIGHT_CLASS_DEVICE) || defined(CONFIG_BACKLIGHT_CLASS_DEVICE_MODULE) - static u8 radeon_atom_bl_level(struct backlight_device *bd) { u8 level; @@ -211,6 +211,11 @@ void radeon_atom_backlight_init(struct radeon_encoder *radeon_encoder, if (!(rdev->mode_info.firmware_flags & ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU)) return; + if (!acpi_video_backlight_use_native()) { + drm_info(dev, "Skipping radeon atom DIG backlight registration\n"); + return; + } + pdata = kmalloc(sizeof(struct radeon_backlight_privdata), GFP_KERNEL); if (!pdata) { DRM_ERROR("Memory allocation failed\n"); @@ -286,18 +291,6 @@ static void radeon_atom_backlight_exit(struct radeon_encoder *radeon_encoder) } } -#else /* !CONFIG_BACKLIGHT_CLASS_DEVICE */ - -void radeon_atom_backlight_init(struct radeon_encoder *encoder) -{ -} - -static void radeon_atom_backlight_exit(struct radeon_encoder *encoder) -{ -} - -#endif - static bool radeon_atom_mode_fixup(struct drm_encoder *encoder, const struct drm_display_mode *mode, struct drm_display_mode *adjusted_mode) @@ -681,15 +674,7 @@ atombios_get_encoder_mode(struct drm_encoder *encoder) struct drm_connector *connector; struct radeon_connector *radeon_connector; struct radeon_connector_atom_dig *dig_connector; - struct radeon_encoder_atom_dig *dig_enc; - if (radeon_encoder_is_digital(encoder)) { - dig_enc = radeon_encoder->enc_priv; - if (dig_enc->active_mst_links) - return ATOM_ENCODER_MODE_DP_MST; - } - if (radeon_encoder->is_mst_encoder || radeon_encoder->offset) - return ATOM_ENCODER_MODE_DP_MST; /* dp bridges are always DP */ if (radeon_encoder_get_dp_bridge_encoder_id(encoder) != ENCODER_OBJECT_ID_NONE) return ATOM_ENCODER_MODE_DP; @@ -1737,10 +1722,6 @@ radeon_atom_encoder_dpms_dig(struct drm_encoder *encoder, int mode) case DRM_MODE_DPMS_SUSPEND: case DRM_MODE_DPMS_OFF: - /* don't power off encoders with active MST links */ - if (dig->active_mst_links) - return; - if (ASIC_IS_DCE4(rdev)) { if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(encoder)) && connector) atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_DP_VIDEO_OFF, 0); @@ -2006,53 +1987,6 @@ atombios_set_encoder_crtc_source(struct drm_encoder *encoder) radeon_atombios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id); } -void -atombios_set_mst_encoder_crtc_source(struct drm_encoder *encoder, int fe) -{ - struct drm_device *dev = encoder->dev; - struct radeon_device *rdev = dev->dev_private; - struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc); - int index = GetIndexIntoMasterTable(COMMAND, SelectCRTC_Source); - uint8_t frev, crev; - union crtc_source_param args; - - memset(&args, 0, sizeof(args)); - - if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev)) - return; - - if (frev != 1 && crev != 2) - DRM_ERROR("Unknown table for MST %d, %d\n", frev, crev); - - args.v2.ucCRTC = radeon_crtc->crtc_id; - args.v2.ucEncodeMode = ATOM_ENCODER_MODE_DP_MST; - - switch (fe) { - case 0: - args.v2.ucEncoderID = ASIC_INT_DIG1_ENCODER_ID; - break; - case 1: - args.v2.ucEncoderID = ASIC_INT_DIG2_ENCODER_ID; - break; - case 2: - args.v2.ucEncoderID = ASIC_INT_DIG3_ENCODER_ID; - break; - case 3: - args.v2.ucEncoderID = ASIC_INT_DIG4_ENCODER_ID; - break; - case 4: - args.v2.ucEncoderID = ASIC_INT_DIG5_ENCODER_ID; - break; - case 5: - args.v2.ucEncoderID = ASIC_INT_DIG6_ENCODER_ID; - break; - case 6: - args.v2.ucEncoderID = ASIC_INT_DIG7_ENCODER_ID; - break; - } - atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); -} - static void atombios_apply_encoder_quirks(struct drm_encoder *encoder, struct drm_display_mode *mode) diff --git a/sys/dev/pci/drm/radeon/cayman_blit_shaders.c b/sys/dev/pci/drm/radeon/cayman_blit_shaders.c deleted file mode 100644 index 9fec4d09f38..00000000000 --- a/sys/dev/pci/drm/radeon/cayman_blit_shaders.c +++ /dev/null @@ -1,320 +0,0 @@ -/* - * Copyright 2010 Advanced Micro Devices, Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice (including the next - * paragraph) shall be included in all copies or substantial portions of the - * Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - * - * Authors: - * Alex Deucher <alexander.deucher@amd.com> - */ - -#include <linux/bug.h> -#include <linux/types.h> -#include <linux/kernel.h> - -/* - * evergreen cards need to use the 3D engine to blit data which requires - * quite a bit of hw state setup. Rather than pull the whole 3D driver - * (which normally generates the 3D state) into the DRM, we opt to use - * statically generated state tables. The register state and shaders - * were hand generated to support blitting functionality. See the 3D - * driver or documentation for descriptions of the registers and - * shader instructions. - */ - -const u32 cayman_default_state[] = -{ - 0xc0066900, - 0x00000000, - 0x00000060, /* DB_RENDER_CONTROL */ - 0x00000000, /* DB_COUNT_CONTROL */ - 0x00000000, /* DB_DEPTH_VIEW */ - 0x0000002a, /* DB_RENDER_OVERRIDE */ - 0x00000000, /* DB_RENDER_OVERRIDE2 */ - 0x00000000, /* DB_HTILE_DATA_BASE */ - - 0xc0026900, - 0x0000000a, - 0x00000000, /* DB_STENCIL_CLEAR */ - 0x00000000, /* DB_DEPTH_CLEAR */ - - 0xc0036900, - 0x0000000f, - 0x00000000, /* DB_DEPTH_INFO */ - 0x00000000, /* DB_Z_INFO */ - 0x00000000, /* DB_STENCIL_INFO */ - - 0xc0016900, - 0x00000080, - 0x00000000, /* PA_SC_WINDOW_OFFSET */ - - 0xc00d6900, - 0x00000083, - 0x0000ffff, /* PA_SC_CLIPRECT_RULE */ - 0x00000000, /* PA_SC_CLIPRECT_0_TL */ - 0x20002000, /* PA_SC_CLIPRECT_0_BR */ - 0x00000000, - 0x20002000, - 0x00000000, - 0x20002000, - 0x00000000, - 0x20002000, - 0xaaaaaaaa, /* PA_SC_EDGERULE */ - 0x00000000, /* PA_SU_HARDWARE_SCREEN_OFFSET */ - 0x0000000f, /* CB_TARGET_MASK */ - 0x0000000f, /* CB_SHADER_MASK */ - - 0xc0226900, - 0x00000094, - 0x80000000, /* PA_SC_VPORT_SCISSOR_0_TL */ - 0x20002000, /* PA_SC_VPORT_SCISSOR_0_BR */ - 0x80000000, - 0x20002000, - 0x80000000, - 0x20002000, - 0x80000000, - 0x20002000, - 0x80000000, - 0x20002000, - 0x80000000, - 0x20002000, - 0x80000000, - 0x20002000, - 0x80000000, - 0x20002000, - 0x80000000, - 0x20002000, - 0x80000000, - 0x20002000, - 0x80000000, - 0x20002000, - 0x80000000, - 0x20002000, - 0x80000000, - 0x20002000, - 0x80000000, - 0x20002000, - 0x80000000, - 0x20002000, - 0x80000000, - 0x20002000, - 0x00000000, /* PA_SC_VPORT_ZMIN_0 */ - 0x3f800000, /* PA_SC_VPORT_ZMAX_0 */ - - 0xc0016900, - 0x000000d4, - 0x00000000, /* SX_MISC */ - - 0xc0026900, - 0x000000d9, - 0x00000000, /* CP_RINGID */ - 0x00000000, /* CP_VMID */ - - 0xc0096900, - 0x00000100, - 0x00ffffff, /* VGT_MAX_VTX_INDX */ - 0x00000000, /* VGT_MIN_VTX_INDX */ - 0x00000000, /* VGT_INDX_OFFSET */ - 0x00000000, /* VGT_MULTI_PRIM_IB_RESET_INDX */ - 0x00000000, /* SX_ALPHA_TEST_CONTROL */ - 0x00000000, /* CB_BLEND_RED */ - 0x00000000, /* CB_BLEND_GREEN */ - 0x00000000, /* CB_BLEND_BLUE */ - 0x00000000, /* CB_BLEND_ALPHA */ - - 0xc0016900, - 0x00000187, - 0x00000100, /* SPI_VS_OUT_ID_0 */ - - 0xc0026900, - 0x00000191, - 0x00000100, /* SPI_PS_INPUT_CNTL_0 */ - 0x00000101, /* SPI_PS_INPUT_CNTL_1 */ - - 0xc0016900, - 0x000001b1, - 0x00000000, /* SPI_VS_OUT_CONFIG */ - - 0xc0106900, - 0x000001b3, - 0x20000001, /* SPI_PS_IN_CONTROL_0 */ - 0x00000000, /* SPI_PS_IN_CONTROL_1 */ - 0x00000000, /* SPI_INTERP_CONTROL_0 */ - 0x00000000, /* SPI_INPUT_Z */ - 0x00000000, /* SPI_FOG_CNTL */ - 0x00100000, /* SPI_BARYC_CNTL */ - 0x00000000, /* SPI_PS_IN_CONTROL_2 */ - 0x00000000, /* SPI_COMPUTE_INPUT_CNTL */ - 0x00000000, /* SPI_COMPUTE_NUM_THREAD_X */ - 0x00000000, /* SPI_COMPUTE_NUM_THREAD_Y */ - 0x00000000, /* SPI_COMPUTE_NUM_THREAD_Z */ - 0x00000000, /* SPI_GPR_MGMT */ - 0x00000000, /* SPI_LDS_MGMT */ - 0x00000000, /* SPI_STACK_MGMT */ - 0x00000000, /* SPI_WAVE_MGMT_1 */ - 0x00000000, /* SPI_WAVE_MGMT_2 */ - - 0xc0016900, - 0x000001e0, - 0x00000000, /* CB_BLEND0_CONTROL */ - - 0xc00e6900, - 0x00000200, - 0x00000000, /* DB_DEPTH_CONTROL */ - 0x00000000, /* DB_EQAA */ - 0x00cc0010, /* CB_COLOR_CONTROL */ - 0x00000210, /* DB_SHADER_CONTROL */ - 0x00010000, /* PA_CL_CLIP_CNTL */ - 0x00000004, /* PA_SU_SC_MODE_CNTL */ - 0x00000100, /* PA_CL_VTE_CNTL */ - 0x00000000, /* PA_CL_VS_OUT_CNTL */ - 0x00000000, /* PA_CL_NANINF_CNTL */ - 0x00000000, /* PA_SU_LINE_STIPPLE_CNTL */ - 0x00000000, /* PA_SU_LINE_STIPPLE_SCALE */ - 0x00000000, /* PA_SU_PRIM_FILTER_CNTL */ - 0x00000000, /* */ - 0x00000000, /* */ - - 0xc0026900, - 0x00000229, - 0x00000000, /* SQ_PGM_START_FS */ - 0x00000000, - - 0xc0016900, - 0x0000023b, - 0x00000000, /* SQ_LDS_ALLOC_PS */ - - 0xc0066900, - 0x00000240, - 0x00000000, /* SQ_ESGS_RING_ITEMSIZE */ - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - - 0xc0046900, - 0x00000247, - 0x00000000, /* SQ_GS_VERT_ITEMSIZE */ - 0x00000000, - 0x00000000, - 0x00000000, - - 0xc0116900, - 0x00000280, - 0x00000000, /* PA_SU_POINT_SIZE */ - 0x00000000, /* PA_SU_POINT_MINMAX */ - 0x00000008, /* PA_SU_LINE_CNTL */ - 0x00000000, /* PA_SC_LINE_STIPPLE */ - 0x00000000, /* VGT_OUTPUT_PATH_CNTL */ - 0x00000000, /* VGT_HOS_CNTL */ - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, /* VGT_GS_MODE */ - - 0xc0026900, - 0x00000292, - 0x00000000, /* PA_SC_MODE_CNTL_0 */ - 0x00000000, /* PA_SC_MODE_CNTL_1 */ - - 0xc0016900, - 0x000002a1, - 0x00000000, /* VGT_PRIMITIVEID_EN */ - - 0xc0016900, - 0x000002a5, - 0x00000000, /* VGT_MULTI_PRIM_IB_RESET_EN */ - - 0xc0026900, - 0x000002a8, - 0x00000000, /* VGT_INSTANCE_STEP_RATE_0 */ - 0x00000000, - - 0xc0026900, - 0x000002ad, - 0x00000000, /* VGT_REUSE_OFF */ - 0x00000000, - - 0xc0016900, - 0x000002d5, - 0x00000000, /* VGT_SHADER_STAGES_EN */ - - 0xc0016900, - 0x000002dc, - 0x0000aa00, /* DB_ALPHA_TO_MASK */ - - 0xc0066900, - 0x000002de, - 0x00000000, /* PA_SU_POLY_OFFSET_DB_FMT_CNTL */ - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - - 0xc0026900, - 0x000002e5, - 0x00000000, /* VGT_STRMOUT_CONFIG */ - 0x00000000, - - 0xc01b6900, - 0x000002f5, - 0x76543210, /* PA_SC_CENTROID_PRIORITY_0 */ - 0xfedcba98, /* PA_SC_CENTROID_PRIORITY_1 */ - 0x00000000, /* PA_SC_LINE_CNTL */ - 0x00000000, /* PA_SC_AA_CONFIG */ - 0x00000005, /* PA_SU_VTX_CNTL */ - 0x3f800000, /* PA_CL_GB_VERT_CLIP_ADJ */ - 0x3f800000, /* PA_CL_GB_VERT_DISC_ADJ */ - 0x3f800000, /* PA_CL_GB_HORZ_CLIP_ADJ */ - 0x3f800000, /* PA_CL_GB_HORZ_DISC_ADJ */ - 0x00000000, /* PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0 */ - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0xffffffff, /* PA_SC_AA_MASK_X0Y0_X1Y0 */ - 0xffffffff, - - 0xc0026900, - 0x00000316, - 0x0000000e, /* VGT_VERTEX_REUSE_BLOCK_CNTL */ - 0x00000010, /* */ -}; - -const u32 cayman_default_size = ARRAY_SIZE(cayman_default_state); diff --git a/sys/dev/pci/drm/radeon/cayman_blit_shaders.h b/sys/dev/pci/drm/radeon/cayman_blit_shaders.h index f5d0e9a6026..1dca73d9e00 100644 --- a/sys/dev/pci/drm/radeon/cayman_blit_shaders.h +++ b/sys/dev/pci/drm/radeon/cayman_blit_shaders.h @@ -20,16 +20,300 @@ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * DEALINGS IN THE SOFTWARE. * + * Authors: + * Alex Deucher <alexander.deucher@amd.com> */ #ifndef CAYMAN_BLIT_SHADERS_H #define CAYMAN_BLIT_SHADERS_H -extern const u32 cayman_ps[]; -extern const u32 cayman_vs[]; -extern const u32 cayman_default_state[]; +/* + * evergreen cards need to use the 3D engine to blit data which requires + * quite a bit of hw state setup. Rather than pull the whole 3D driver + * (which normally generates the 3D state) into the DRM, we opt to use + * statically generated state tables. The register state and shaders + * were hand generated to support blitting functionality. See the 3D + * driver or documentation for descriptions of the registers and + * shader instructions. + */ +static const u32 cayman_default_state[] = { + 0xc0066900, + 0x00000000, + 0x00000060, /* DB_RENDER_CONTROL */ + 0x00000000, /* DB_COUNT_CONTROL */ + 0x00000000, /* DB_DEPTH_VIEW */ + 0x0000002a, /* DB_RENDER_OVERRIDE */ + 0x00000000, /* DB_RENDER_OVERRIDE2 */ + 0x00000000, /* DB_HTILE_DATA_BASE */ + + 0xc0026900, + 0x0000000a, + 0x00000000, /* DB_STENCIL_CLEAR */ + 0x00000000, /* DB_DEPTH_CLEAR */ + + 0xc0036900, + 0x0000000f, + 0x00000000, /* DB_DEPTH_INFO */ + 0x00000000, /* DB_Z_INFO */ + 0x00000000, /* DB_STENCIL_INFO */ + + 0xc0016900, + 0x00000080, + 0x00000000, /* PA_SC_WINDOW_OFFSET */ + + 0xc00d6900, + 0x00000083, + 0x0000ffff, /* PA_SC_CLIPRECT_RULE */ + 0x00000000, /* PA_SC_CLIPRECT_0_TL */ + 0x20002000, /* PA_SC_CLIPRECT_0_BR */ + 0x00000000, + 0x20002000, + 0x00000000, + 0x20002000, + 0x00000000, + 0x20002000, + 0xaaaaaaaa, /* PA_SC_EDGERULE */ + 0x00000000, /* PA_SU_HARDWARE_SCREEN_OFFSET */ + 0x0000000f, /* CB_TARGET_MASK */ + 0x0000000f, /* CB_SHADER_MASK */ + + 0xc0226900, + 0x00000094, + 0x80000000, /* PA_SC_VPORT_SCISSOR_0_TL */ + 0x20002000, /* PA_SC_VPORT_SCISSOR_0_BR */ + 0x80000000, + 0x20002000, + 0x80000000, + 0x20002000, + 0x80000000, + 0x20002000, + 0x80000000, + 0x20002000, + 0x80000000, + 0x20002000, + 0x80000000, + 0x20002000, + 0x80000000, + 0x20002000, + 0x80000000, + 0x20002000, + 0x80000000, + 0x20002000, + 0x80000000, + 0x20002000, + 0x80000000, + 0x20002000, + 0x80000000, + 0x20002000, + 0x80000000, + 0x20002000, + 0x80000000, + 0x20002000, + 0x80000000, + 0x20002000, + 0x00000000, /* PA_SC_VPORT_ZMIN_0 */ + 0x3f800000, /* PA_SC_VPORT_ZMAX_0 */ + + 0xc0016900, + 0x000000d4, + 0x00000000, /* SX_MISC */ + + 0xc0026900, + 0x000000d9, + 0x00000000, /* CP_RINGID */ + 0x00000000, /* CP_VMID */ + + 0xc0096900, + 0x00000100, + 0x00ffffff, /* VGT_MAX_VTX_INDX */ + 0x00000000, /* VGT_MIN_VTX_INDX */ + 0x00000000, /* VGT_INDX_OFFSET */ + 0x00000000, /* VGT_MULTI_PRIM_IB_RESET_INDX */ + 0x00000000, /* SX_ALPHA_TEST_CONTROL */ + 0x00000000, /* CB_BLEND_RED */ + 0x00000000, /* CB_BLEND_GREEN */ + 0x00000000, /* CB_BLEND_BLUE */ + 0x00000000, /* CB_BLEND_ALPHA */ + + 0xc0016900, + 0x00000187, + 0x00000100, /* SPI_VS_OUT_ID_0 */ + + 0xc0026900, + 0x00000191, + 0x00000100, /* SPI_PS_INPUT_CNTL_0 */ + 0x00000101, /* SPI_PS_INPUT_CNTL_1 */ + + 0xc0016900, + 0x000001b1, + 0x00000000, /* SPI_VS_OUT_CONFIG */ + + 0xc0106900, + 0x000001b3, + 0x20000001, /* SPI_PS_IN_CONTROL_0 */ + 0x00000000, /* SPI_PS_IN_CONTROL_1 */ + 0x00000000, /* SPI_INTERP_CONTROL_0 */ + 0x00000000, /* SPI_INPUT_Z */ + 0x00000000, /* SPI_FOG_CNTL */ + 0x00100000, /* SPI_BARYC_CNTL */ + 0x00000000, /* SPI_PS_IN_CONTROL_2 */ + 0x00000000, /* SPI_COMPUTE_INPUT_CNTL */ + 0x00000000, /* SPI_COMPUTE_NUM_THREAD_X */ + 0x00000000, /* SPI_COMPUTE_NUM_THREAD_Y */ + 0x00000000, /* SPI_COMPUTE_NUM_THREAD_Z */ + 0x00000000, /* SPI_GPR_MGMT */ + 0x00000000, /* SPI_LDS_MGMT */ + 0x00000000, /* SPI_STACK_MGMT */ + 0x00000000, /* SPI_WAVE_MGMT_1 */ + 0x00000000, /* SPI_WAVE_MGMT_2 */ + + 0xc0016900, + 0x000001e0, + 0x00000000, /* CB_BLEND0_CONTROL */ + + 0xc00e6900, + 0x00000200, + 0x00000000, /* DB_DEPTH_CONTROL */ + 0x00000000, /* DB_EQAA */ + 0x00cc0010, /* CB_COLOR_CONTROL */ + 0x00000210, /* DB_SHADER_CONTROL */ + 0x00010000, /* PA_CL_CLIP_CNTL */ + 0x00000004, /* PA_SU_SC_MODE_CNTL */ + 0x00000100, /* PA_CL_VTE_CNTL */ + 0x00000000, /* PA_CL_VS_OUT_CNTL */ + 0x00000000, /* PA_CL_NANINF_CNTL */ + 0x00000000, /* PA_SU_LINE_STIPPLE_CNTL */ + 0x00000000, /* PA_SU_LINE_STIPPLE_SCALE */ + 0x00000000, /* PA_SU_PRIM_FILTER_CNTL */ + 0x00000000, /* */ + 0x00000000, /* */ + + 0xc0026900, + 0x00000229, + 0x00000000, /* SQ_PGM_START_FS */ + 0x00000000, + + 0xc0016900, + 0x0000023b, + 0x00000000, /* SQ_LDS_ALLOC_PS */ + + 0xc0066900, + 0x00000240, + 0x00000000, /* SQ_ESGS_RING_ITEMSIZE */ + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + + 0xc0046900, + 0x00000247, + 0x00000000, /* SQ_GS_VERT_ITEMSIZE */ + 0x00000000, + 0x00000000, + 0x00000000, + + 0xc0116900, + 0x00000280, + 0x00000000, /* PA_SU_POINT_SIZE */ + 0x00000000, /* PA_SU_POINT_MINMAX */ + 0x00000008, /* PA_SU_LINE_CNTL */ + 0x00000000, /* PA_SC_LINE_STIPPLE */ + 0x00000000, /* VGT_OUTPUT_PATH_CNTL */ + 0x00000000, /* VGT_HOS_CNTL */ + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, /* VGT_GS_MODE */ + + 0xc0026900, + 0x00000292, + 0x00000000, /* PA_SC_MODE_CNTL_0 */ + 0x00000000, /* PA_SC_MODE_CNTL_1 */ + + 0xc0016900, + 0x000002a1, + 0x00000000, /* VGT_PRIMITIVEID_EN */ + + 0xc0016900, + 0x000002a5, + 0x00000000, /* VGT_MULTI_PRIM_IB_RESET_EN */ + + 0xc0026900, + 0x000002a8, + 0x00000000, /* VGT_INSTANCE_STEP_RATE_0 */ + 0x00000000, + + 0xc0026900, + 0x000002ad, + 0x00000000, /* VGT_REUSE_OFF */ + 0x00000000, + + 0xc0016900, + 0x000002d5, + 0x00000000, /* VGT_SHADER_STAGES_EN */ + + 0xc0016900, + 0x000002dc, + 0x0000aa00, /* DB_ALPHA_TO_MASK */ + + 0xc0066900, + 0x000002de, + 0x00000000, /* PA_SU_POLY_OFFSET_DB_FMT_CNTL */ + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + + 0xc0026900, + 0x000002e5, + 0x00000000, /* VGT_STRMOUT_CONFIG */ + 0x00000000, + + 0xc01b6900, + 0x000002f5, + 0x76543210, /* PA_SC_CENTROID_PRIORITY_0 */ + 0xfedcba98, /* PA_SC_CENTROID_PRIORITY_1 */ + 0x00000000, /* PA_SC_LINE_CNTL */ + 0x00000000, /* PA_SC_AA_CONFIG */ + 0x00000005, /* PA_SU_VTX_CNTL */ + 0x3f800000, /* PA_CL_GB_VERT_CLIP_ADJ */ + 0x3f800000, /* PA_CL_GB_VERT_DISC_ADJ */ + 0x3f800000, /* PA_CL_GB_HORZ_CLIP_ADJ */ + 0x3f800000, /* PA_CL_GB_HORZ_DISC_ADJ */ + 0x00000000, /* PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0 */ + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0xffffffff, /* PA_SC_AA_MASK_X0Y0_X1Y0 */ + 0xffffffff, + + 0xc0026900, + 0x00000316, + 0x0000000e, /* VGT_VERTEX_REUSE_BLOCK_CNTL */ + 0x00000010, /* */ +}; -extern const u32 cayman_ps_size, cayman_vs_size; -extern const u32 cayman_default_size; +static const u32 cayman_default_size = ARRAY_SIZE(cayman_default_state); #endif diff --git a/sys/dev/pci/drm/radeon/ci_dpm.c b/sys/dev/pci/drm/radeon/ci_dpm.c index f0cfb58da46..8ef25ab305a 100644 --- a/sys/dev/pci/drm/radeon/ci_dpm.c +++ b/sys/dev/pci/drm/radeon/ci_dpm.c @@ -390,8 +390,7 @@ static int ci_min_max_v_gnbl_pm_lid_from_bapm_vddc(struct radeon_device *rdev) static int ci_populate_bapm_vddc_base_leakage_sidd(struct radeon_device *rdev) { struct ci_power_info *pi = ci_get_pi(rdev); - u16 hi_sidd = pi->smc_powertune_table.BapmVddCBaseLeakageHiSidd; - u16 lo_sidd = pi->smc_powertune_table.BapmVddCBaseLeakageLoSidd; + u16 hi_sidd, lo_sidd; struct radeon_cac_tdp_table *cac_tdp_table = rdev->pm.dpm.dyn_state.cac_tdp_table; @@ -2057,7 +2056,7 @@ static void ci_clear_vc(struct radeon_device *rdev) static int ci_upload_firmware(struct radeon_device *rdev) { struct ci_power_info *pi = ci_get_pi(rdev); - int i, ret; + int i; for (i = 0; i < rdev->usec_timeout; i++) { if (RREG32_SMC(RCU_UC_EVENTS) & BOOT_SEQ_DONE) @@ -2068,9 +2067,7 @@ static int ci_upload_firmware(struct radeon_device *rdev) ci_stop_smc_clock(rdev); ci_reset_smc(rdev); - ret = ci_load_smc_ucode(rdev, pi->sram_end); - - return ret; + return ci_load_smc_ucode(rdev, pi->sram_end); } diff --git a/sys/dev/pci/drm/radeon/cik.c b/sys/dev/pci/drm/radeon/cik.c index 00d69212a69..62be8749472 100644 --- a/sys/dev/pci/drm/radeon/cik.c +++ b/sys/dev/pci/drm/radeon/cik.c @@ -8519,8 +8519,8 @@ int cik_suspend(struct radeon_device *rdev) cik_cp_enable(rdev, false); cik_sdma_enable(rdev, false); if (rdev->has_uvd) { - uvd_v1_0_fini(rdev); radeon_uvd_suspend(rdev); + uvd_v1_0_fini(rdev); } if (rdev->has_vce) radeon_vce_suspend(rdev); diff --git a/sys/dev/pci/drm/radeon/cik_blit_shaders.c b/sys/dev/pci/drm/radeon/cik_blit_shaders.c deleted file mode 100644 index ff1311806e9..00000000000 --- a/sys/dev/pci/drm/radeon/cik_blit_shaders.c +++ /dev/null @@ -1,246 +0,0 @@ -/* - * Copyright 2012 Advanced Micro Devices, Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice (including the next - * paragraph) shall be included in all copies or substantial portions of the - * Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - * - * Authors: - * Alex Deucher <alexander.deucher@amd.com> - */ - -#include <linux/types.h> -#include <linux/bug.h> -#include <linux/kernel.h> - -const u32 cik_default_state[] = -{ - 0xc0066900, - 0x00000000, - 0x00000060, /* DB_RENDER_CONTROL */ - 0x00000000, /* DB_COUNT_CONTROL */ - 0x00000000, /* DB_DEPTH_VIEW */ - 0x0000002a, /* DB_RENDER_OVERRIDE */ - 0x00000000, /* DB_RENDER_OVERRIDE2 */ - 0x00000000, /* DB_HTILE_DATA_BASE */ - - 0xc0046900, - 0x00000008, - 0x00000000, /* DB_DEPTH_BOUNDS_MIN */ - 0x00000000, /* DB_DEPTH_BOUNDS_MAX */ - 0x00000000, /* DB_STENCIL_CLEAR */ - 0x00000000, /* DB_DEPTH_CLEAR */ - - 0xc0036900, - 0x0000000f, - 0x00000000, /* DB_DEPTH_INFO */ - 0x00000000, /* DB_Z_INFO */ - 0x00000000, /* DB_STENCIL_INFO */ - - 0xc0016900, - 0x00000080, - 0x00000000, /* PA_SC_WINDOW_OFFSET */ - - 0xc00d6900, - 0x00000083, - 0x0000ffff, /* PA_SC_CLIPRECT_RULE */ - 0x00000000, /* PA_SC_CLIPRECT_0_TL */ - 0x20002000, /* PA_SC_CLIPRECT_0_BR */ - 0x00000000, - 0x20002000, - 0x00000000, - 0x20002000, - 0x00000000, - 0x20002000, - 0xaaaaaaaa, /* PA_SC_EDGERULE */ - 0x00000000, /* PA_SU_HARDWARE_SCREEN_OFFSET */ - 0x0000000f, /* CB_TARGET_MASK */ - 0x0000000f, /* CB_SHADER_MASK */ - - 0xc0226900, - 0x00000094, - 0x80000000, /* PA_SC_VPORT_SCISSOR_0_TL */ - 0x20002000, /* PA_SC_VPORT_SCISSOR_0_BR */ - 0x80000000, - 0x20002000, - 0x80000000, - 0x20002000, - 0x80000000, - 0x20002000, - 0x80000000, - 0x20002000, - 0x80000000, - 0x20002000, - 0x80000000, - 0x20002000, - 0x80000000, - 0x20002000, - 0x80000000, - 0x20002000, - 0x80000000, - 0x20002000, - 0x80000000, - 0x20002000, - 0x80000000, - 0x20002000, - 0x80000000, - 0x20002000, - 0x80000000, - 0x20002000, - 0x80000000, - 0x20002000, - 0x80000000, - 0x20002000, - 0x00000000, /* PA_SC_VPORT_ZMIN_0 */ - 0x3f800000, /* PA_SC_VPORT_ZMAX_0 */ - - 0xc0046900, - 0x00000100, - 0xffffffff, /* VGT_MAX_VTX_INDX */ - 0x00000000, /* VGT_MIN_VTX_INDX */ - 0x00000000, /* VGT_INDX_OFFSET */ - 0x00000000, /* VGT_MULTI_PRIM_IB_RESET_INDX */ - - 0xc0046900, - 0x00000105, - 0x00000000, /* CB_BLEND_RED */ - 0x00000000, /* CB_BLEND_GREEN */ - 0x00000000, /* CB_BLEND_BLUE */ - 0x00000000, /* CB_BLEND_ALPHA */ - - 0xc0016900, - 0x000001e0, - 0x00000000, /* CB_BLEND0_CONTROL */ - - 0xc00c6900, - 0x00000200, - 0x00000000, /* DB_DEPTH_CONTROL */ - 0x00000000, /* DB_EQAA */ - 0x00cc0010, /* CB_COLOR_CONTROL */ - 0x00000210, /* DB_SHADER_CONTROL */ - 0x00010000, /* PA_CL_CLIP_CNTL */ - 0x00000004, /* PA_SU_SC_MODE_CNTL */ - 0x00000100, /* PA_CL_VTE_CNTL */ - 0x00000000, /* PA_CL_VS_OUT_CNTL */ - 0x00000000, /* PA_CL_NANINF_CNTL */ - 0x00000000, /* PA_SU_LINE_STIPPLE_CNTL */ - 0x00000000, /* PA_SU_LINE_STIPPLE_SCALE */ - 0x00000000, /* PA_SU_PRIM_FILTER_CNTL */ - - 0xc0116900, - 0x00000280, - 0x00000000, /* PA_SU_POINT_SIZE */ - 0x00000000, /* PA_SU_POINT_MINMAX */ - 0x00000008, /* PA_SU_LINE_CNTL */ - 0x00000000, /* PA_SC_LINE_STIPPLE */ - 0x00000000, /* VGT_OUTPUT_PATH_CNTL */ - 0x00000000, /* VGT_HOS_CNTL */ - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, /* VGT_GS_MODE */ - - 0xc0026900, - 0x00000292, - 0x00000000, /* PA_SC_MODE_CNTL_0 */ - 0x00000000, /* PA_SC_MODE_CNTL_1 */ - - 0xc0016900, - 0x000002a1, - 0x00000000, /* VGT_PRIMITIVEID_EN */ - - 0xc0016900, - 0x000002a5, - 0x00000000, /* VGT_MULTI_PRIM_IB_RESET_EN */ - - 0xc0026900, - 0x000002a8, - 0x00000000, /* VGT_INSTANCE_STEP_RATE_0 */ - 0x00000000, - - 0xc0026900, - 0x000002ad, - 0x00000000, /* VGT_REUSE_OFF */ - 0x00000000, - - 0xc0016900, - 0x000002d5, - 0x00000000, /* VGT_SHADER_STAGES_EN */ - - 0xc0016900, - 0x000002dc, - 0x0000aa00, /* DB_ALPHA_TO_MASK */ - - 0xc0066900, - 0x000002de, - 0x00000000, /* PA_SU_POLY_OFFSET_DB_FMT_CNTL */ - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - - 0xc0026900, - 0x000002e5, - 0x00000000, /* VGT_STRMOUT_CONFIG */ - 0x00000000, - - 0xc01b6900, - 0x000002f5, - 0x76543210, /* PA_SC_CENTROID_PRIORITY_0 */ - 0xfedcba98, /* PA_SC_CENTROID_PRIORITY_1 */ - 0x00000000, /* PA_SC_LINE_CNTL */ - 0x00000000, /* PA_SC_AA_CONFIG */ - 0x00000005, /* PA_SU_VTX_CNTL */ - 0x3f800000, /* PA_CL_GB_VERT_CLIP_ADJ */ - 0x3f800000, /* PA_CL_GB_VERT_DISC_ADJ */ - 0x3f800000, /* PA_CL_GB_HORZ_CLIP_ADJ */ - 0x3f800000, /* PA_CL_GB_HORZ_DISC_ADJ */ - 0x00000000, /* PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0 */ - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0xffffffff, /* PA_SC_AA_MASK_X0Y0_X1Y0 */ - 0xffffffff, - - 0xc0026900, - 0x00000316, - 0x0000000e, /* VGT_VERTEX_REUSE_BLOCK_CNTL */ - 0x00000010, /* */ -}; - -const u32 cik_default_size = ARRAY_SIZE(cik_default_state); diff --git a/sys/dev/pci/drm/radeon/cik_blit_shaders.h b/sys/dev/pci/drm/radeon/cik_blit_shaders.h index dfe7314f9ff..d2a2e231681 100644 --- a/sys/dev/pci/drm/radeon/cik_blit_shaders.h +++ b/sys/dev/pci/drm/radeon/cik_blit_shaders.h @@ -20,13 +20,228 @@ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * DEALINGS IN THE SOFTWARE. * + * Authors: + * Alex Deucher <alexander.deucher@amd.com> */ #ifndef CIK_BLIT_SHADERS_H #define CIK_BLIT_SHADERS_H -extern const u32 cik_default_state[]; +static const u32 cik_default_state[] = +{ + 0xc0066900, + 0x00000000, + 0x00000060, /* DB_RENDER_CONTROL */ + 0x00000000, /* DB_COUNT_CONTROL */ + 0x00000000, /* DB_DEPTH_VIEW */ + 0x0000002a, /* DB_RENDER_OVERRIDE */ + 0x00000000, /* DB_RENDER_OVERRIDE2 */ + 0x00000000, /* DB_HTILE_DATA_BASE */ -extern const u32 cik_default_size; + 0xc0046900, + 0x00000008, + 0x00000000, /* DB_DEPTH_BOUNDS_MIN */ + 0x00000000, /* DB_DEPTH_BOUNDS_MAX */ + 0x00000000, /* DB_STENCIL_CLEAR */ + 0x00000000, /* DB_DEPTH_CLEAR */ + + 0xc0036900, + 0x0000000f, + 0x00000000, /* DB_DEPTH_INFO */ + 0x00000000, /* DB_Z_INFO */ + 0x00000000, /* DB_STENCIL_INFO */ + + 0xc0016900, + 0x00000080, + 0x00000000, /* PA_SC_WINDOW_OFFSET */ + + 0xc00d6900, + 0x00000083, + 0x0000ffff, /* PA_SC_CLIPRECT_RULE */ + 0x00000000, /* PA_SC_CLIPRECT_0_TL */ + 0x20002000, /* PA_SC_CLIPRECT_0_BR */ + 0x00000000, + 0x20002000, + 0x00000000, + 0x20002000, + 0x00000000, + 0x20002000, + 0xaaaaaaaa, /* PA_SC_EDGERULE */ + 0x00000000, /* PA_SU_HARDWARE_SCREEN_OFFSET */ + 0x0000000f, /* CB_TARGET_MASK */ + 0x0000000f, /* CB_SHADER_MASK */ + + 0xc0226900, + 0x00000094, + 0x80000000, /* PA_SC_VPORT_SCISSOR_0_TL */ + 0x20002000, /* PA_SC_VPORT_SCISSOR_0_BR */ + 0x80000000, + 0x20002000, + 0x80000000, + 0x20002000, + 0x80000000, + 0x20002000, + 0x80000000, + 0x20002000, + 0x80000000, + 0x20002000, + 0x80000000, + 0x20002000, + 0x80000000, + 0x20002000, + 0x80000000, + 0x20002000, + 0x80000000, + 0x20002000, + 0x80000000, + 0x20002000, + 0x80000000, + 0x20002000, + 0x80000000, + 0x20002000, + 0x80000000, + 0x20002000, + 0x80000000, + 0x20002000, + 0x80000000, + 0x20002000, + 0x00000000, /* PA_SC_VPORT_ZMIN_0 */ + 0x3f800000, /* PA_SC_VPORT_ZMAX_0 */ + + 0xc0046900, + 0x00000100, + 0xffffffff, /* VGT_MAX_VTX_INDX */ + 0x00000000, /* VGT_MIN_VTX_INDX */ + 0x00000000, /* VGT_INDX_OFFSET */ + 0x00000000, /* VGT_MULTI_PRIM_IB_RESET_INDX */ + + 0xc0046900, + 0x00000105, + 0x00000000, /* CB_BLEND_RED */ + 0x00000000, /* CB_BLEND_GREEN */ + 0x00000000, /* CB_BLEND_BLUE */ + 0x00000000, /* CB_BLEND_ALPHA */ + + 0xc0016900, + 0x000001e0, + 0x00000000, /* CB_BLEND0_CONTROL */ + + 0xc00c6900, + 0x00000200, + 0x00000000, /* DB_DEPTH_CONTROL */ + 0x00000000, /* DB_EQAA */ + 0x00cc0010, /* CB_COLOR_CONTROL */ + 0x00000210, /* DB_SHADER_CONTROL */ + 0x00010000, /* PA_CL_CLIP_CNTL */ + 0x00000004, /* PA_SU_SC_MODE_CNTL */ + 0x00000100, /* PA_CL_VTE_CNTL */ + 0x00000000, /* PA_CL_VS_OUT_CNTL */ + 0x00000000, /* PA_CL_NANINF_CNTL */ + 0x00000000, /* PA_SU_LINE_STIPPLE_CNTL */ + 0x00000000, /* PA_SU_LINE_STIPPLE_SCALE */ + 0x00000000, /* PA_SU_PRIM_FILTER_CNTL */ + + 0xc0116900, + 0x00000280, + 0x00000000, /* PA_SU_POINT_SIZE */ + 0x00000000, /* PA_SU_POINT_MINMAX */ + 0x00000008, /* PA_SU_LINE_CNTL */ + 0x00000000, /* PA_SC_LINE_STIPPLE */ + 0x00000000, /* VGT_OUTPUT_PATH_CNTL */ + 0x00000000, /* VGT_HOS_CNTL */ + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, /* VGT_GS_MODE */ + + 0xc0026900, + 0x00000292, + 0x00000000, /* PA_SC_MODE_CNTL_0 */ + 0x00000000, /* PA_SC_MODE_CNTL_1 */ + + 0xc0016900, + 0x000002a1, + 0x00000000, /* VGT_PRIMITIVEID_EN */ + + 0xc0016900, + 0x000002a5, + 0x00000000, /* VGT_MULTI_PRIM_IB_RESET_EN */ + + 0xc0026900, + 0x000002a8, + 0x00000000, /* VGT_INSTANCE_STEP_RATE_0 */ + 0x00000000, + + 0xc0026900, + 0x000002ad, + 0x00000000, /* VGT_REUSE_OFF */ + 0x00000000, + + 0xc0016900, + 0x000002d5, + 0x00000000, /* VGT_SHADER_STAGES_EN */ + + 0xc0016900, + 0x000002dc, + 0x0000aa00, /* DB_ALPHA_TO_MASK */ + + 0xc0066900, + 0x000002de, + 0x00000000, /* PA_SU_POLY_OFFSET_DB_FMT_CNTL */ + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + + 0xc0026900, + 0x000002e5, + 0x00000000, /* VGT_STRMOUT_CONFIG */ + 0x00000000, + + 0xc01b6900, + 0x000002f5, + 0x76543210, /* PA_SC_CENTROID_PRIORITY_0 */ + 0xfedcba98, /* PA_SC_CENTROID_PRIORITY_1 */ + 0x00000000, /* PA_SC_LINE_CNTL */ + 0x00000000, /* PA_SC_AA_CONFIG */ + 0x00000005, /* PA_SU_VTX_CNTL */ + 0x3f800000, /* PA_CL_GB_VERT_CLIP_ADJ */ + 0x3f800000, /* PA_CL_GB_VERT_DISC_ADJ */ + 0x3f800000, /* PA_CL_GB_HORZ_CLIP_ADJ */ + 0x3f800000, /* PA_CL_GB_HORZ_DISC_ADJ */ + 0x00000000, /* PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0 */ + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0xffffffff, /* PA_SC_AA_MASK_X0Y0_X1Y0 */ + 0xffffffff, + + 0xc0026900, + 0x00000316, + 0x0000000e, /* VGT_VERTEX_REUSE_BLOCK_CNTL */ + 0x00000010, /* */ +}; + +static const u32 cik_default_size = ARRAY_SIZE(cik_default_state); #endif diff --git a/sys/dev/pci/drm/radeon/evergreen.c b/sys/dev/pci/drm/radeon/evergreen.c index 443371b3c36..42507f7c2a2 100644 --- a/sys/dev/pci/drm/radeon/evergreen.c +++ b/sys/dev/pci/drm/radeon/evergreen.c @@ -29,6 +29,7 @@ #include <drm/drm_vblank.h> #include <drm/radeon_drm.h> #include <drm/drm_fourcc.h> +#include <drm/drm_framebuffer.h> #include "atom.h" #include "avivod.h" @@ -5158,8 +5159,8 @@ int evergreen_suspend(struct radeon_device *rdev) radeon_pm_suspend(rdev); radeon_audio_fini(rdev); if (rdev->has_uvd) { - uvd_v1_0_fini(rdev); radeon_uvd_suspend(rdev); + uvd_v1_0_fini(rdev); } r700_cp_stop(rdev); r600_dma_stop(rdev); diff --git a/sys/dev/pci/drm/radeon/evergreen_blit_shaders.c b/sys/dev/pci/drm/radeon/evergreen_blit_shaders.c deleted file mode 100644 index 1a96ddb3e5e..00000000000 --- a/sys/dev/pci/drm/radeon/evergreen_blit_shaders.c +++ /dev/null @@ -1,303 +0,0 @@ -/* - * Copyright 2010 Advanced Micro Devices, Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice (including the next - * paragraph) shall be included in all copies or substantial portions of the - * Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - * - * Authors: - * Alex Deucher <alexander.deucher@amd.com> - */ - -#include <linux/bug.h> -#include <linux/types.h> -#include <linux/kernel.h> - -/* - * evergreen cards need to use the 3D engine to blit data which requires - * quite a bit of hw state setup. Rather than pull the whole 3D driver - * (which normally generates the 3D state) into the DRM, we opt to use - * statically generated state tables. The register state and shaders - * were hand generated to support blitting functionality. See the 3D - * driver or documentation for descriptions of the registers and - * shader instructions. - */ - -const u32 evergreen_default_state[] = -{ - 0xc0016900, - 0x0000023b, - 0x00000000, /* SQ_LDS_ALLOC_PS */ - - 0xc0066900, - 0x00000240, - 0x00000000, /* SQ_ESGS_RING_ITEMSIZE */ - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - - 0xc0046900, - 0x00000247, - 0x00000000, /* SQ_GS_VERT_ITEMSIZE */ - 0x00000000, - 0x00000000, - 0x00000000, - - 0xc0026900, - 0x00000010, - 0x00000000, /* DB_Z_INFO */ - 0x00000000, /* DB_STENCIL_INFO */ - - 0xc0016900, - 0x00000200, - 0x00000000, /* DB_DEPTH_CONTROL */ - - 0xc0066900, - 0x00000000, - 0x00000060, /* DB_RENDER_CONTROL */ - 0x00000000, /* DB_COUNT_CONTROL */ - 0x00000000, /* DB_DEPTH_VIEW */ - 0x0000002a, /* DB_RENDER_OVERRIDE */ - 0x00000000, /* DB_RENDER_OVERRIDE2 */ - 0x00000000, /* DB_HTILE_DATA_BASE */ - - 0xc0026900, - 0x0000000a, - 0x00000000, /* DB_STENCIL_CLEAR */ - 0x00000000, /* DB_DEPTH_CLEAR */ - - 0xc0016900, - 0x000002dc, - 0x0000aa00, /* DB_ALPHA_TO_MASK */ - - 0xc0016900, - 0x00000080, - 0x00000000, /* PA_SC_WINDOW_OFFSET */ - - 0xc00d6900, - 0x00000083, - 0x0000ffff, /* PA_SC_CLIPRECT_RULE */ - 0x00000000, /* PA_SC_CLIPRECT_0_TL */ - 0x20002000, /* PA_SC_CLIPRECT_0_BR */ - 0x00000000, - 0x20002000, - 0x00000000, - 0x20002000, - 0x00000000, - 0x20002000, - 0xaaaaaaaa, /* PA_SC_EDGERULE */ - 0x00000000, /* PA_SU_HARDWARE_SCREEN_OFFSET */ - 0x0000000f, /* CB_TARGET_MASK */ - 0x0000000f, /* CB_SHADER_MASK */ - - 0xc0226900, - 0x00000094, - 0x80000000, /* PA_SC_VPORT_SCISSOR_0_TL */ - 0x20002000, /* PA_SC_VPORT_SCISSOR_0_BR */ - 0x80000000, - 0x20002000, - 0x80000000, - 0x20002000, - 0x80000000, - 0x20002000, - 0x80000000, - 0x20002000, - 0x80000000, - 0x20002000, - 0x80000000, - 0x20002000, - 0x80000000, - 0x20002000, - 0x80000000, - 0x20002000, - 0x80000000, - 0x20002000, - 0x80000000, - 0x20002000, - 0x80000000, - 0x20002000, - 0x80000000, - 0x20002000, - 0x80000000, - 0x20002000, - 0x80000000, - 0x20002000, - 0x80000000, - 0x20002000, - 0x00000000, /* PA_SC_VPORT_ZMIN_0 */ - 0x3f800000, /* PA_SC_VPORT_ZMAX_0 */ - - 0xc0016900, - 0x000000d4, - 0x00000000, /* SX_MISC */ - - 0xc0026900, - 0x00000292, - 0x00000000, /* PA_SC_MODE_CNTL_0 */ - 0x00000000, /* PA_SC_MODE_CNTL_1 */ - - 0xc0106900, - 0x00000300, - 0x00000000, /* PA_SC_LINE_CNTL */ - 0x00000000, /* PA_SC_AA_CONFIG */ - 0x00000005, /* PA_SU_VTX_CNTL */ - 0x3f800000, /* PA_CL_GB_VERT_CLIP_ADJ */ - 0x3f800000, /* PA_CL_GB_VERT_DISC_ADJ */ - 0x3f800000, /* PA_CL_GB_HORZ_CLIP_ADJ */ - 0x3f800000, /* PA_CL_GB_HORZ_DISC_ADJ */ - 0x00000000, /* PA_SC_AA_SAMPLE_LOCS_0 */ - 0x00000000, /* */ - 0x00000000, /* */ - 0x00000000, /* */ - 0x00000000, /* */ - 0x00000000, /* */ - 0x00000000, /* */ - 0x00000000, /* PA_SC_AA_SAMPLE_LOCS_7 */ - 0xffffffff, /* PA_SC_AA_MASK */ - - 0xc00d6900, - 0x00000202, - 0x00cc0010, /* CB_COLOR_CONTROL */ - 0x00000210, /* DB_SHADER_CONTROL */ - 0x00010000, /* PA_CL_CLIP_CNTL */ - 0x00000004, /* PA_SU_SC_MODE_CNTL */ - 0x00000100, /* PA_CL_VTE_CNTL */ - 0x00000000, /* PA_CL_VS_OUT_CNTL */ - 0x00000000, /* PA_CL_NANINF_CNTL */ - 0x00000000, /* PA_SU_LINE_STIPPLE_CNTL */ - 0x00000000, /* PA_SU_LINE_STIPPLE_SCALE */ - 0x00000000, /* PA_SU_PRIM_FILTER_CNTL */ - 0x00000000, /* */ - 0x00000000, /* */ - 0x00000000, /* SQ_DYN_GPR_RESOURCE_LIMIT_1 */ - - 0xc0066900, - 0x000002de, - 0x00000000, /* PA_SU_POLY_OFFSET_DB_FMT_CNTL */ - 0x00000000, /* */ - 0x00000000, /* */ - 0x00000000, /* */ - 0x00000000, /* */ - 0x00000000, /* */ - - 0xc0016900, - 0x00000229, - 0x00000000, /* SQ_PGM_START_FS */ - - 0xc0016900, - 0x0000022a, - 0x00000000, /* SQ_PGM_RESOURCES_FS */ - - 0xc0096900, - 0x00000100, - 0x00ffffff, /* VGT_MAX_VTX_INDX */ - 0x00000000, /* */ - 0x00000000, /* */ - 0x00000000, /* */ - 0x00000000, /* SX_ALPHA_TEST_CONTROL */ - 0x00000000, /* CB_BLEND_RED */ - 0x00000000, /* CB_BLEND_GREEN */ - 0x00000000, /* CB_BLEND_BLUE */ - 0x00000000, /* CB_BLEND_ALPHA */ - - 0xc0026900, - 0x000002a8, - 0x00000000, /* VGT_INSTANCE_STEP_RATE_0 */ - 0x00000000, /* */ - - 0xc0026900, - 0x000002ad, - 0x00000000, /* VGT_REUSE_OFF */ - 0x00000000, /* */ - - 0xc0116900, - 0x00000280, - 0x00000000, /* PA_SU_POINT_SIZE */ - 0x00000000, /* PA_SU_POINT_MINMAX */ - 0x00000008, /* PA_SU_LINE_CNTL */ - 0x00000000, /* PA_SC_LINE_STIPPLE */ - 0x00000000, /* VGT_OUTPUT_PATH_CNTL */ - 0x00000000, /* VGT_HOS_CNTL */ - 0x00000000, /* */ - 0x00000000, /* */ - 0x00000000, /* */ - 0x00000000, /* */ - 0x00000000, /* */ - 0x00000000, /* */ - 0x00000000, /* */ - 0x00000000, /* */ - 0x00000000, /* */ - 0x00000000, /* */ - 0x00000000, /* VGT_GS_MODE */ - - 0xc0016900, - 0x000002a1, - 0x00000000, /* VGT_PRIMITIVEID_EN */ - - 0xc0016900, - 0x000002a5, - 0x00000000, /* VGT_MULTI_PRIM_IB_RESET_EN */ - - 0xc0016900, - 0x000002d5, - 0x00000000, /* VGT_SHADER_STAGES_EN */ - - 0xc0026900, - 0x000002e5, - 0x00000000, /* VGT_STRMOUT_CONFIG */ - 0x00000000, /* */ - - 0xc0016900, - 0x000001e0, - 0x00000000, /* CB_BLEND0_CONTROL */ - - 0xc0016900, - 0x000001b1, - 0x00000000, /* SPI_VS_OUT_CONFIG */ - - 0xc0016900, - 0x00000187, - 0x00000000, /* SPI_VS_OUT_ID_0 */ - - 0xc0016900, - 0x00000191, - 0x00000100, /* SPI_PS_INPUT_CNTL_0 */ - - 0xc00b6900, - 0x000001b3, - 0x20000001, /* SPI_PS_IN_CONTROL_0 */ - 0x00000000, /* SPI_PS_IN_CONTROL_1 */ - 0x00000000, /* SPI_INTERP_CONTROL_0 */ - 0x00000000, /* SPI_INPUT_Z */ - 0x00000000, /* SPI_FOG_CNTL */ - 0x00100000, /* SPI_BARYC_CNTL */ - 0x00000000, /* SPI_PS_IN_CONTROL_2 */ - 0x00000000, /* */ - 0x00000000, /* */ - 0x00000000, /* */ - 0x00000000, /* */ - - 0xc0026900, - 0x00000316, - 0x0000000e, /* VGT_VERTEX_REUSE_BLOCK_CNTL */ - 0x00000010, /* */ -}; - -const u32 evergreen_default_size = ARRAY_SIZE(evergreen_default_state); diff --git a/sys/dev/pci/drm/radeon/evergreen_blit_shaders.h b/sys/dev/pci/drm/radeon/evergreen_blit_shaders.h index bb8d6c75159..4492524ee1d 100644 --- a/sys/dev/pci/drm/radeon/evergreen_blit_shaders.h +++ b/sys/dev/pci/drm/radeon/evergreen_blit_shaders.h @@ -20,16 +20,284 @@ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * DEALINGS IN THE SOFTWARE. * + * Authors: + * Alex Deucher <alexander.deucher@amd.com> */ #ifndef EVERGREEN_BLIT_SHADERS_H #define EVERGREEN_BLIT_SHADERS_H -extern const u32 evergreen_ps[]; -extern const u32 evergreen_vs[]; -extern const u32 evergreen_default_state[]; +/* + * evergreen cards need to use the 3D engine to blit data which requires + * quite a bit of hw state setup. Rather than pull the whole 3D driver + * (which normally generates the 3D state) into the DRM, we opt to use + * statically generated state tables. The register state and shaders + * were hand generated to support blitting functionality. See the 3D + * driver or documentation for descriptions of the registers and + * shader instructions. + */ + +static const u32 evergreen_default_state[] = { + 0xc0016900, + 0x0000023b, + 0x00000000, /* SQ_LDS_ALLOC_PS */ + + 0xc0066900, + 0x00000240, + 0x00000000, /* SQ_ESGS_RING_ITEMSIZE */ + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + + 0xc0046900, + 0x00000247, + 0x00000000, /* SQ_GS_VERT_ITEMSIZE */ + 0x00000000, + 0x00000000, + 0x00000000, + + 0xc0026900, + 0x00000010, + 0x00000000, /* DB_Z_INFO */ + 0x00000000, /* DB_STENCIL_INFO */ + + 0xc0016900, + 0x00000200, + 0x00000000, /* DB_DEPTH_CONTROL */ + + 0xc0066900, + 0x00000000, + 0x00000060, /* DB_RENDER_CONTROL */ + 0x00000000, /* DB_COUNT_CONTROL */ + 0x00000000, /* DB_DEPTH_VIEW */ + 0x0000002a, /* DB_RENDER_OVERRIDE */ + 0x00000000, /* DB_RENDER_OVERRIDE2 */ + 0x00000000, /* DB_HTILE_DATA_BASE */ + + 0xc0026900, + 0x0000000a, + 0x00000000, /* DB_STENCIL_CLEAR */ + 0x00000000, /* DB_DEPTH_CLEAR */ + + 0xc0016900, + 0x000002dc, + 0x0000aa00, /* DB_ALPHA_TO_MASK */ + + 0xc0016900, + 0x00000080, + 0x00000000, /* PA_SC_WINDOW_OFFSET */ + + 0xc00d6900, + 0x00000083, + 0x0000ffff, /* PA_SC_CLIPRECT_RULE */ + 0x00000000, /* PA_SC_CLIPRECT_0_TL */ + 0x20002000, /* PA_SC_CLIPRECT_0_BR */ + 0x00000000, + 0x20002000, + 0x00000000, + 0x20002000, + 0x00000000, + 0x20002000, + 0xaaaaaaaa, /* PA_SC_EDGERULE */ + 0x00000000, /* PA_SU_HARDWARE_SCREEN_OFFSET */ + 0x0000000f, /* CB_TARGET_MASK */ + 0x0000000f, /* CB_SHADER_MASK */ + + 0xc0226900, + 0x00000094, + 0x80000000, /* PA_SC_VPORT_SCISSOR_0_TL */ + 0x20002000, /* PA_SC_VPORT_SCISSOR_0_BR */ + 0x80000000, + 0x20002000, + 0x80000000, + 0x20002000, + 0x80000000, + 0x20002000, + 0x80000000, + 0x20002000, + 0x80000000, + 0x20002000, + 0x80000000, + 0x20002000, + 0x80000000, + 0x20002000, + 0x80000000, + 0x20002000, + 0x80000000, + 0x20002000, + 0x80000000, + 0x20002000, + 0x80000000, + 0x20002000, + 0x80000000, + 0x20002000, + 0x80000000, + 0x20002000, + 0x80000000, + 0x20002000, + 0x80000000, + 0x20002000, + 0x00000000, /* PA_SC_VPORT_ZMIN_0 */ + 0x3f800000, /* PA_SC_VPORT_ZMAX_0 */ + + 0xc0016900, + 0x000000d4, + 0x00000000, /* SX_MISC */ + + 0xc0026900, + 0x00000292, + 0x00000000, /* PA_SC_MODE_CNTL_0 */ + 0x00000000, /* PA_SC_MODE_CNTL_1 */ + + 0xc0106900, + 0x00000300, + 0x00000000, /* PA_SC_LINE_CNTL */ + 0x00000000, /* PA_SC_AA_CONFIG */ + 0x00000005, /* PA_SU_VTX_CNTL */ + 0x3f800000, /* PA_CL_GB_VERT_CLIP_ADJ */ + 0x3f800000, /* PA_CL_GB_VERT_DISC_ADJ */ + 0x3f800000, /* PA_CL_GB_HORZ_CLIP_ADJ */ + 0x3f800000, /* PA_CL_GB_HORZ_DISC_ADJ */ + 0x00000000, /* PA_SC_AA_SAMPLE_LOCS_0 */ + 0x00000000, /* */ + 0x00000000, /* */ + 0x00000000, /* */ + 0x00000000, /* */ + 0x00000000, /* */ + 0x00000000, /* */ + 0x00000000, /* PA_SC_AA_SAMPLE_LOCS_7 */ + 0xffffffff, /* PA_SC_AA_MASK */ + + 0xc00d6900, + 0x00000202, + 0x00cc0010, /* CB_COLOR_CONTROL */ + 0x00000210, /* DB_SHADER_CONTROL */ + 0x00010000, /* PA_CL_CLIP_CNTL */ + 0x00000004, /* PA_SU_SC_MODE_CNTL */ + 0x00000100, /* PA_CL_VTE_CNTL */ + 0x00000000, /* PA_CL_VS_OUT_CNTL */ + 0x00000000, /* PA_CL_NANINF_CNTL */ + 0x00000000, /* PA_SU_LINE_STIPPLE_CNTL */ + 0x00000000, /* PA_SU_LINE_STIPPLE_SCALE */ + 0x00000000, /* PA_SU_PRIM_FILTER_CNTL */ + 0x00000000, /* */ + 0x00000000, /* */ + 0x00000000, /* SQ_DYN_GPR_RESOURCE_LIMIT_1 */ + + 0xc0066900, + 0x000002de, + 0x00000000, /* PA_SU_POLY_OFFSET_DB_FMT_CNTL */ + 0x00000000, /* */ + 0x00000000, /* */ + 0x00000000, /* */ + 0x00000000, /* */ + 0x00000000, /* */ + + 0xc0016900, + 0x00000229, + 0x00000000, /* SQ_PGM_START_FS */ + + 0xc0016900, + 0x0000022a, + 0x00000000, /* SQ_PGM_RESOURCES_FS */ + + 0xc0096900, + 0x00000100, + 0x00ffffff, /* VGT_MAX_VTX_INDX */ + 0x00000000, /* */ + 0x00000000, /* */ + 0x00000000, /* */ + 0x00000000, /* SX_ALPHA_TEST_CONTROL */ + 0x00000000, /* CB_BLEND_RED */ + 0x00000000, /* CB_BLEND_GREEN */ + 0x00000000, /* CB_BLEND_BLUE */ + 0x00000000, /* CB_BLEND_ALPHA */ + + 0xc0026900, + 0x000002a8, + 0x00000000, /* VGT_INSTANCE_STEP_RATE_0 */ + 0x00000000, /* */ + + 0xc0026900, + 0x000002ad, + 0x00000000, /* VGT_REUSE_OFF */ + 0x00000000, /* */ + + 0xc0116900, + 0x00000280, + 0x00000000, /* PA_SU_POINT_SIZE */ + 0x00000000, /* PA_SU_POINT_MINMAX */ + 0x00000008, /* PA_SU_LINE_CNTL */ + 0x00000000, /* PA_SC_LINE_STIPPLE */ + 0x00000000, /* VGT_OUTPUT_PATH_CNTL */ + 0x00000000, /* VGT_HOS_CNTL */ + 0x00000000, /* */ + 0x00000000, /* */ + 0x00000000, /* */ + 0x00000000, /* */ + 0x00000000, /* */ + 0x00000000, /* */ + 0x00000000, /* */ + 0x00000000, /* */ + 0x00000000, /* */ + 0x00000000, /* */ + 0x00000000, /* VGT_GS_MODE */ + + 0xc0016900, + 0x000002a1, + 0x00000000, /* VGT_PRIMITIVEID_EN */ + + 0xc0016900, + 0x000002a5, + 0x00000000, /* VGT_MULTI_PRIM_IB_RESET_EN */ + + 0xc0016900, + 0x000002d5, + 0x00000000, /* VGT_SHADER_STAGES_EN */ + + 0xc0026900, + 0x000002e5, + 0x00000000, /* VGT_STRMOUT_CONFIG */ + 0x00000000, /* */ + + 0xc0016900, + 0x000001e0, + 0x00000000, /* CB_BLEND0_CONTROL */ + + 0xc0016900, + 0x000001b1, + 0x00000000, /* SPI_VS_OUT_CONFIG */ + + 0xc0016900, + 0x00000187, + 0x00000000, /* SPI_VS_OUT_ID_0 */ + + 0xc0016900, + 0x00000191, + 0x00000100, /* SPI_PS_INPUT_CNTL_0 */ + + 0xc00b6900, + 0x000001b3, + 0x20000001, /* SPI_PS_IN_CONTROL_0 */ + 0x00000000, /* SPI_PS_IN_CONTROL_1 */ + 0x00000000, /* SPI_INTERP_CONTROL_0 */ + 0x00000000, /* SPI_INPUT_Z */ + 0x00000000, /* SPI_FOG_CNTL */ + 0x00100000, /* SPI_BARYC_CNTL */ + 0x00000000, /* SPI_PS_IN_CONTROL_2 */ + 0x00000000, /* */ + 0x00000000, /* */ + 0x00000000, /* */ + 0x00000000, /* */ + + 0xc0026900, + 0x00000316, + 0x0000000e, /* VGT_VERTEX_REUSE_BLOCK_CNTL */ + 0x00000010, /* */ +}; -extern const u32 evergreen_ps_size, evergreen_vs_size; -extern const u32 evergreen_default_size; +static const u32 evergreen_default_size = ARRAY_SIZE(evergreen_default_state); #endif diff --git a/sys/dev/pci/drm/radeon/ni.c b/sys/dev/pci/drm/radeon/ni.c index 85de441726a..d30b6406b6c 100644 --- a/sys/dev/pci/drm/radeon/ni.c +++ b/sys/dev/pci/drm/radeon/ni.c @@ -2323,8 +2323,8 @@ int cayman_suspend(struct radeon_device *rdev) cayman_cp_enable(rdev, false); cayman_dma_stop(rdev); if (rdev->has_uvd) { - uvd_v1_0_fini(rdev); radeon_uvd_suspend(rdev); + uvd_v1_0_fini(rdev); } evergreen_irq_suspend(rdev); radeon_wb_disable(rdev); diff --git a/sys/dev/pci/drm/radeon/r100.c b/sys/dev/pci/drm/radeon/r100.c index 0e4029d8220..f499b12443c 100644 --- a/sys/dev/pci/drm/radeon/r100.c +++ b/sys/dev/pci/drm/radeon/r100.c @@ -35,6 +35,7 @@ #include <drm/drm_device.h> #include <drm/drm_file.h> #include <drm/drm_fourcc.h> +#include <drm/drm_framebuffer.h> #include <drm/drm_vblank.h> #include <drm/radeon_drm.h> diff --git a/sys/dev/pci/drm/radeon/r300_reg.h b/sys/dev/pci/drm/radeon/r300_reg.h index 60d5413bafa..9d341cff63e 100644 --- a/sys/dev/pci/drm/radeon/r300_reg.h +++ b/sys/dev/pci/drm/radeon/r300_reg.h @@ -1103,7 +1103,7 @@ * The destination register index is in FPI1 (color) and FPI3 (alpha) * together with enable bits. * There are separate enable bits for writing into temporary registers - * (DSTC_REG_* /DSTA_REG) and and program output registers (DSTC_OUTPUT_* + * (DSTC_REG_* /DSTA_REG) and program output registers (DSTC_OUTPUT_* * /DSTA_OUTPUT). You can write to both at once, or not write at all (the * same index must be used for both). * diff --git a/sys/dev/pci/drm/radeon/r600.c b/sys/dev/pci/drm/radeon/r600.c index db3651e4acd..70ae95074b3 100644 --- a/sys/dev/pci/drm/radeon/r600.c +++ b/sys/dev/pci/drm/radeon/r600.c @@ -3232,8 +3232,8 @@ int r600_suspend(struct radeon_device *rdev) radeon_audio_fini(rdev); r600_cp_stop(rdev); if (rdev->has_uvd) { - uvd_v1_0_fini(rdev); radeon_uvd_suspend(rdev); + uvd_v1_0_fini(rdev); } r600_irq_suspend(rdev); radeon_wb_disable(rdev); diff --git a/sys/dev/pci/drm/radeon/r600_blit_shaders.c b/sys/dev/pci/drm/radeon/r600_blit_shaders.c deleted file mode 100644 index 443cbe59b27..00000000000 --- a/sys/dev/pci/drm/radeon/r600_blit_shaders.c +++ /dev/null @@ -1,719 +0,0 @@ -/* - * Copyright 2009 Advanced Micro Devices, Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice (including the next - * paragraph) shall be included in all copies or substantial portions of the - * Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - * - * Authors: - * Alex Deucher <alexander.deucher@amd.com> - */ - -#include <linux/bug.h> -#include <linux/types.h> -#include <linux/kernel.h> - -/* - * R6xx+ cards need to use the 3D engine to blit data which requires - * quite a bit of hw state setup. Rather than pull the whole 3D driver - * (which normally generates the 3D state) into the DRM, we opt to use - * statically generated state tables. The register state and shaders - * were hand generated to support blitting functionality. See the 3D - * driver or documentation for descriptions of the registers and - * shader instructions. - */ - -const u32 r6xx_default_state[] = -{ - 0xc0002400, /* START_3D_CMDBUF */ - 0x00000000, - - 0xc0012800, /* CONTEXT_CONTROL */ - 0x80000000, - 0x80000000, - - 0xc0016800, - 0x00000010, - 0x00008000, /* WAIT_UNTIL */ - - 0xc0016800, - 0x00000542, - 0x07000003, /* TA_CNTL_AUX */ - - 0xc0016800, - 0x000005c5, - 0x00000000, /* VC_ENHANCE */ - - 0xc0016800, - 0x00000363, - 0x00000000, /* SQ_DYN_GPR_CNTL_PS_FLUSH_REQ */ - - 0xc0016800, - 0x0000060c, - 0x82000000, /* DB_DEBUG */ - - 0xc0016800, - 0x0000060e, - 0x01020204, /* DB_WATERMARKS */ - - 0xc0026f00, - 0x00000000, - 0x00000000, /* SQ_VTX_BASE_VTX_LOC */ - 0x00000000, /* SQ_VTX_START_INST_LOC */ - - 0xc0096900, - 0x0000022a, - 0x00000000, /* SQ_ESGS_RING_ITEMSIZE */ - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - - 0xc0016900, - 0x00000004, - 0x00000000, /* DB_DEPTH_INFO */ - - 0xc0026900, - 0x0000000a, - 0x00000000, /* DB_STENCIL_CLEAR */ - 0x00000000, /* DB_DEPTH_CLEAR */ - - 0xc0016900, - 0x00000200, - 0x00000000, /* DB_DEPTH_CONTROL */ - - 0xc0026900, - 0x00000343, - 0x00000060, /* DB_RENDER_CONTROL */ - 0x00000040, /* DB_RENDER_OVERRIDE */ - - 0xc0016900, - 0x00000351, - 0x0000aa00, /* DB_ALPHA_TO_MASK */ - - 0xc00f6900, - 0x00000100, - 0x00000800, /* VGT_MAX_VTX_INDX */ - 0x00000000, /* VGT_MIN_VTX_INDX */ - 0x00000000, /* VGT_INDX_OFFSET */ - 0x00000000, /* VGT_MULTI_PRIM_IB_RESET_INDX */ - 0x00000000, /* SX_ALPHA_TEST_CONTROL */ - 0x00000000, /* CB_BLEND_RED */ - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, /* CB_FOG_RED */ - 0x00000000, - 0x00000000, - 0x00000000, /* DB_STENCILREFMASK */ - 0x00000000, /* DB_STENCILREFMASK_BF */ - 0x00000000, /* SX_ALPHA_REF */ - - 0xc0046900, - 0x0000030c, - 0x01000000, /* CB_CLRCMP_CNTL */ - 0x00000000, - 0x00000000, - 0x00000000, - - 0xc0046900, - 0x00000048, - 0x3f800000, /* CB_CLEAR_RED */ - 0x00000000, - 0x3f800000, - 0x3f800000, - - 0xc0016900, - 0x00000080, - 0x00000000, /* PA_SC_WINDOW_OFFSET */ - - 0xc00a6900, - 0x00000083, - 0x0000ffff, /* PA_SC_CLIP_RECT_RULE */ - 0x00000000, /* PA_SC_CLIPRECT_0_TL */ - 0x20002000, - 0x00000000, - 0x20002000, - 0x00000000, - 0x20002000, - 0x00000000, - 0x20002000, - 0x00000000, /* PA_SC_EDGERULE */ - - 0xc0406900, - 0x00000094, - 0x80000000, /* PA_SC_VPORT_SCISSOR_0_TL */ - 0x20002000, /* PA_SC_VPORT_SCISSOR_0_BR */ - 0x80000000, /* PA_SC_VPORT_SCISSOR_1_TL */ - 0x20002000, - 0x80000000, - 0x20002000, - 0x80000000, - 0x20002000, - 0x80000000, - 0x20002000, - 0x80000000, - 0x20002000, - 0x80000000, - 0x20002000, - 0x80000000, - 0x20002000, - 0x80000000, - 0x20002000, - 0x80000000, - 0x20002000, - 0x80000000, - 0x20002000, - 0x80000000, - 0x20002000, - 0x80000000, - 0x20002000, - 0x80000000, - 0x20002000, - 0x80000000, - 0x20002000, - 0x80000000, - 0x20002000, - 0x00000000, /* PA_SC_VPORT_ZMIN_0 */ - 0x3f800000, - 0x00000000, - 0x3f800000, - 0x00000000, - 0x3f800000, - 0x00000000, - 0x3f800000, - 0x00000000, - 0x3f800000, - 0x00000000, - 0x3f800000, - 0x00000000, - 0x3f800000, - 0x00000000, - 0x3f800000, - 0x00000000, - 0x3f800000, - 0x00000000, - 0x3f800000, - 0x00000000, - 0x3f800000, - 0x00000000, - 0x3f800000, - 0x00000000, - 0x3f800000, - 0x00000000, - 0x3f800000, - 0x00000000, - 0x3f800000, - 0x00000000, - 0x3f800000, - - 0xc0026900, - 0x00000292, - 0x00000000, /* PA_SC_MPASS_PS_CNTL */ - 0x00004010, /* PA_SC_MODE_CNTL */ - - 0xc0096900, - 0x00000300, - 0x00000000, /* PA_SC_LINE_CNTL */ - 0x00000000, /* PA_SC_AA_CONFIG */ - 0x0000002d, /* PA_SU_VTX_CNTL */ - 0x3f800000, /* PA_CL_GB_VERT_CLIP_ADJ */ - 0x3f800000, - 0x3f800000, - 0x3f800000, - 0x00000000, /* PA_SC_SAMPLE_LOCS_MCTX */ - 0x00000000, - - 0xc0016900, - 0x00000312, - 0xffffffff, /* PA_SC_AA_MASK */ - - 0xc0066900, - 0x0000037e, - 0x00000000, /* PA_SU_POLY_OFFSET_DB_FMT_CNTL */ - 0x00000000, /* PA_SU_POLY_OFFSET_CLAMP */ - 0x00000000, /* PA_SU_POLY_OFFSET_FRONT_SCALE */ - 0x00000000, /* PA_SU_POLY_OFFSET_FRONT_OFFSET */ - 0x00000000, /* PA_SU_POLY_OFFSET_BACK_SCALE */ - 0x00000000, /* PA_SU_POLY_OFFSET_BACK_OFFSET */ - - 0xc0046900, - 0x000001b6, - 0x00000000, /* SPI_INPUT_Z */ - 0x00000000, /* SPI_FOG_CNTL */ - 0x00000000, /* SPI_FOG_FUNC_SCALE */ - 0x00000000, /* SPI_FOG_FUNC_BIAS */ - - 0xc0016900, - 0x00000225, - 0x00000000, /* SQ_PGM_START_FS */ - - 0xc0016900, - 0x00000229, - 0x00000000, /* SQ_PGM_RESOURCES_FS */ - - 0xc0016900, - 0x00000237, - 0x00000000, /* SQ_PGM_CF_OFFSET_FS */ - - 0xc0026900, - 0x000002a8, - 0x00000000, /* VGT_INSTANCE_STEP_RATE_0 */ - 0x00000000, /* VGT_INSTANCE_STEP_RATE_1 */ - - 0xc0116900, - 0x00000280, - 0x00000000, /* PA_SU_POINT_SIZE */ - 0x00000000, /* PA_SU_POINT_MINMAX */ - 0x00000008, /* PA_SU_LINE_CNTL */ - 0x00000000, /* PA_SC_LINE_STIPPLE */ - 0x00000000, /* VGT_OUTPUT_PATH_CNTL */ - 0x00000000, /* VGT_HOS_CNTL */ - 0x00000000, /* VGT_HOS_MAX_TESS_LEVEL */ - 0x00000000, /* VGT_HOS_MIN_TESS_LEVEL */ - 0x00000000, /* VGT_HOS_REUSE_DEPTH */ - 0x00000000, /* VGT_GROUP_PRIM_TYPE */ - 0x00000000, /* VGT_GROUP_FIRST_DECR */ - 0x00000000, /* VGT_GROUP_DECR */ - 0x00000000, /* VGT_GROUP_VECT_0_CNTL */ - 0x00000000, /* VGT_GROUP_VECT_1_CNTL */ - 0x00000000, /* VGT_GROUP_VECT_0_FMT_CNTL */ - 0x00000000, /* VGT_GROUP_VECT_1_FMT_CNTL */ - 0x00000000, /* VGT_GS_MODE */ - - 0xc0016900, - 0x000002a1, - 0x00000000, /* VGT_PRIMITIVEID_EN */ - - 0xc0016900, - 0x000002a5, - 0x00000000, /* VGT_MULTI_PRIM_ID_RESET_EN */ - - 0xc0036900, - 0x000002ac, - 0x00000000, /* VGT_STRMOUT_EN */ - 0x00000000, /* VGT_REUSE_OFF */ - 0x00000000, /* VGT_VTX_CNT_EN */ - - 0xc0016900, - 0x000000d4, - 0x00000000, /* SX_MISC */ - - 0xc0016900, - 0x000002c8, - 0x00000000, /* VGT_STRMOUT_BUFFER_EN */ - - 0xc0076900, - 0x00000202, - 0x00cc0000, /* CB_COLOR_CONTROL */ - 0x00000210, /* DB_SHADER_CNTL */ - 0x00010000, /* PA_CL_CLIP_CNTL */ - 0x00000244, /* PA_SU_SC_MODE_CNTL */ - 0x00000100, /* PA_CL_VTE_CNTL */ - 0x00000000, /* PA_CL_VS_OUT_CNTL */ - 0x00000000, /* PA_CL_NANINF_CNTL */ - - 0xc0026900, - 0x0000008e, - 0x0000000f, /* CB_TARGET_MASK */ - 0x0000000f, /* CB_SHADER_MASK */ - - 0xc0016900, - 0x000001e8, - 0x00000001, /* CB_SHADER_CONTROL */ - - 0xc0016900, - 0x00000185, - 0x00000000, /* SPI_VS_OUT_ID_0 */ - - 0xc0016900, - 0x00000191, - 0x00000b00, /* SPI_PS_INPUT_CNTL_0 */ - - 0xc0056900, - 0x000001b1, - 0x00000000, /* SPI_VS_OUT_CONFIG */ - 0x00000000, /* SPI_THREAD_GROUPING */ - 0x00000001, /* SPI_PS_IN_CONTROL_0 */ - 0x00000000, /* SPI_PS_IN_CONTROL_1 */ - 0x00000000, /* SPI_INTERP_CONTROL_0 */ - - 0xc0036e00, /* SET_SAMPLER */ - 0x00000000, - 0x00000012, - 0x00000000, - 0x00000000, -}; - -const u32 r7xx_default_state[] = -{ - 0xc0012800, /* CONTEXT_CONTROL */ - 0x80000000, - 0x80000000, - - 0xc0016800, - 0x00000010, - 0x00008000, /* WAIT_UNTIL */ - - 0xc0016800, - 0x00000542, - 0x07000002, /* TA_CNTL_AUX */ - - 0xc0016800, - 0x000005c5, - 0x00000000, /* VC_ENHANCE */ - - 0xc0016800, - 0x00000363, - 0x00004000, /* SQ_DYN_GPR_CNTL_PS_FLUSH_REQ */ - - 0xc0016800, - 0x0000060c, - 0x00000000, /* DB_DEBUG */ - - 0xc0016800, - 0x0000060e, - 0x00420204, /* DB_WATERMARKS */ - - 0xc0026f00, - 0x00000000, - 0x00000000, /* SQ_VTX_BASE_VTX_LOC */ - 0x00000000, /* SQ_VTX_START_INST_LOC */ - - 0xc0096900, - 0x0000022a, - 0x00000000, /* SQ_ESGS_RING_ITEMSIZE */ - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - - 0xc0016900, - 0x00000004, - 0x00000000, /* DB_DEPTH_INFO */ - - 0xc0026900, - 0x0000000a, - 0x00000000, /* DB_STENCIL_CLEAR */ - 0x00000000, /* DB_DEPTH_CLEAR */ - - 0xc0016900, - 0x00000200, - 0x00000000, /* DB_DEPTH_CONTROL */ - - 0xc0026900, - 0x00000343, - 0x00000060, /* DB_RENDER_CONTROL */ - 0x00000000, /* DB_RENDER_OVERRIDE */ - - 0xc0016900, - 0x00000351, - 0x0000aa00, /* DB_ALPHA_TO_MASK */ - - 0xc0096900, - 0x00000100, - 0x00000800, /* VGT_MAX_VTX_INDX */ - 0x00000000, /* VGT_MIN_VTX_INDX */ - 0x00000000, /* VGT_INDX_OFFSET */ - 0x00000000, /* VGT_MULTI_PRIM_IB_RESET_INDX */ - 0x00000000, /* SX_ALPHA_TEST_CONTROL */ - 0x00000000, /* CB_BLEND_RED */ - 0x00000000, - 0x00000000, - 0x00000000, - - 0xc0036900, - 0x0000010c, - 0x00000000, /* DB_STENCILREFMASK */ - 0x00000000, /* DB_STENCILREFMASK_BF */ - 0x00000000, /* SX_ALPHA_REF */ - - 0xc0046900, - 0x0000030c, /* CB_CLRCMP_CNTL */ - 0x01000000, - 0x00000000, - 0x00000000, - 0x00000000, - - 0xc0016900, - 0x00000080, - 0x00000000, /* PA_SC_WINDOW_OFFSET */ - - 0xc00a6900, - 0x00000083, - 0x0000ffff, /* PA_SC_CLIP_RECT_RULE */ - 0x00000000, /* PA_SC_CLIPRECT_0_TL */ - 0x20002000, - 0x00000000, - 0x20002000, - 0x00000000, - 0x20002000, - 0x00000000, - 0x20002000, - 0xaaaaaaaa, /* PA_SC_EDGERULE */ - - 0xc0406900, - 0x00000094, - 0x80000000, /* PA_SC_VPORT_SCISSOR_0_TL */ - 0x20002000, /* PA_SC_VPORT_SCISSOR_0_BR */ - 0x80000000, /* PA_SC_VPORT_SCISSOR_1_TL */ - 0x20002000, - 0x80000000, - 0x20002000, - 0x80000000, - 0x20002000, - 0x80000000, - 0x20002000, - 0x80000000, - 0x20002000, - 0x80000000, - 0x20002000, - 0x80000000, - 0x20002000, - 0x80000000, - 0x20002000, - 0x80000000, - 0x20002000, - 0x80000000, - 0x20002000, - 0x80000000, - 0x20002000, - 0x80000000, - 0x20002000, - 0x80000000, - 0x20002000, - 0x80000000, - 0x20002000, - 0x80000000, - 0x20002000, - 0x00000000, /* PA_SC_VPORT_ZMIN_0 */ - 0x3f800000, - 0x00000000, - 0x3f800000, - 0x00000000, - 0x3f800000, - 0x00000000, - 0x3f800000, - 0x00000000, - 0x3f800000, - 0x00000000, - 0x3f800000, - 0x00000000, - 0x3f800000, - 0x00000000, - 0x3f800000, - 0x00000000, - 0x3f800000, - 0x00000000, - 0x3f800000, - 0x00000000, - 0x3f800000, - 0x00000000, - 0x3f800000, - 0x00000000, - 0x3f800000, - 0x00000000, - 0x3f800000, - 0x00000000, - 0x3f800000, - 0x00000000, - 0x3f800000, - - 0xc0026900, - 0x00000292, - 0x00000000, /* PA_SC_MPASS_PS_CNTL */ - 0x00514000, /* PA_SC_MODE_CNTL */ - - 0xc0096900, - 0x00000300, - 0x00000000, /* PA_SC_LINE_CNTL */ - 0x00000000, /* PA_SC_AA_CONFIG */ - 0x0000002d, /* PA_SU_VTX_CNTL */ - 0x3f800000, /* PA_CL_GB_VERT_CLIP_ADJ */ - 0x3f800000, - 0x3f800000, - 0x3f800000, - 0x00000000, /* PA_SC_SAMPLE_LOCS_MCTX */ - 0x00000000, - - 0xc0016900, - 0x00000312, - 0xffffffff, /* PA_SC_AA_MASK */ - - 0xc0066900, - 0x0000037e, - 0x00000000, /* PA_SU_POLY_OFFSET_DB_FMT_CNTL */ - 0x00000000, /* PA_SU_POLY_OFFSET_CLAMP */ - 0x00000000, /* PA_SU_POLY_OFFSET_FRONT_SCALE */ - 0x00000000, /* PA_SU_POLY_OFFSET_FRONT_OFFSET */ - 0x00000000, /* PA_SU_POLY_OFFSET_BACK_SCALE */ - 0x00000000, /* PA_SU_POLY_OFFSET_BACK_OFFSET */ - - 0xc0046900, - 0x000001b6, - 0x00000000, /* SPI_INPUT_Z */ - 0x00000000, /* SPI_FOG_CNTL */ - 0x00000000, /* SPI_FOG_FUNC_SCALE */ - 0x00000000, /* SPI_FOG_FUNC_BIAS */ - - 0xc0016900, - 0x00000225, - 0x00000000, /* SQ_PGM_START_FS */ - - 0xc0016900, - 0x00000229, - 0x00000000, /* SQ_PGM_RESOURCES_FS */ - - 0xc0016900, - 0x00000237, - 0x00000000, /* SQ_PGM_CF_OFFSET_FS */ - - 0xc0026900, - 0x000002a8, - 0x00000000, /* VGT_INSTANCE_STEP_RATE_0 */ - 0x00000000, /* VGT_INSTANCE_STEP_RATE_1 */ - - 0xc0116900, - 0x00000280, - 0x00000000, /* PA_SU_POINT_SIZE */ - 0x00000000, /* PA_SU_POINT_MINMAX */ - 0x00000008, /* PA_SU_LINE_CNTL */ - 0x00000000, /* PA_SC_LINE_STIPPLE */ - 0x00000000, /* VGT_OUTPUT_PATH_CNTL */ - 0x00000000, /* VGT_HOS_CNTL */ - 0x00000000, /* VGT_HOS_MAX_TESS_LEVEL */ - 0x00000000, /* VGT_HOS_MIN_TESS_LEVEL */ - 0x00000000, /* VGT_HOS_REUSE_DEPTH */ - 0x00000000, /* VGT_GROUP_PRIM_TYPE */ - 0x00000000, /* VGT_GROUP_FIRST_DECR */ - 0x00000000, /* VGT_GROUP_DECR */ - 0x00000000, /* VGT_GROUP_VECT_0_CNTL */ - 0x00000000, /* VGT_GROUP_VECT_1_CNTL */ - 0x00000000, /* VGT_GROUP_VECT_0_FMT_CNTL */ - 0x00000000, /* VGT_GROUP_VECT_1_FMT_CNTL */ - 0x00000000, /* VGT_GS_MODE */ - - 0xc0016900, - 0x000002a1, - 0x00000000, /* VGT_PRIMITIVEID_EN */ - - 0xc0016900, - 0x000002a5, - 0x00000000, /* VGT_MULTI_PRIM_ID_RESET_EN */ - - 0xc0036900, - 0x000002ac, - 0x00000000, /* VGT_STRMOUT_EN */ - 0x00000000, /* VGT_REUSE_OFF */ - 0x00000000, /* VGT_VTX_CNT_EN */ - - 0xc0016900, - 0x000000d4, - 0x00000000, /* SX_MISC */ - - 0xc0016900, - 0x000002c8, - 0x00000000, /* VGT_STRMOUT_BUFFER_EN */ - - 0xc0076900, - 0x00000202, - 0x00cc0000, /* CB_COLOR_CONTROL */ - 0x00000210, /* DB_SHADER_CNTL */ - 0x00010000, /* PA_CL_CLIP_CNTL */ - 0x00000244, /* PA_SU_SC_MODE_CNTL */ - 0x00000100, /* PA_CL_VTE_CNTL */ - 0x00000000, /* PA_CL_VS_OUT_CNTL */ - 0x00000000, /* PA_CL_NANINF_CNTL */ - - 0xc0026900, - 0x0000008e, - 0x0000000f, /* CB_TARGET_MASK */ - 0x0000000f, /* CB_SHADER_MASK */ - - 0xc0016900, - 0x000001e8, - 0x00000001, /* CB_SHADER_CONTROL */ - - 0xc0016900, - 0x00000185, - 0x00000000, /* SPI_VS_OUT_ID_0 */ - - 0xc0016900, - 0x00000191, - 0x00000b00, /* SPI_PS_INPUT_CNTL_0 */ - - 0xc0056900, - 0x000001b1, - 0x00000000, /* SPI_VS_OUT_CONFIG */ - 0x00000001, /* SPI_THREAD_GROUPING */ - 0x00000001, /* SPI_PS_IN_CONTROL_0 */ - 0x00000000, /* SPI_PS_IN_CONTROL_1 */ - 0x00000000, /* SPI_INTERP_CONTROL_0 */ - - 0xc0036e00, /* SET_SAMPLER */ - 0x00000000, - 0x00000012, - 0x00000000, - 0x00000000, -}; - -/* same for r6xx/r7xx */ -const u32 r6xx_vs[] = -{ - 0x00000004, - 0x81000000, - 0x0000203c, - 0x94000b08, - 0x00004000, - 0x14200b1a, - 0x00000000, - 0x00000000, - 0x3c000000, - 0x68cd1000, -#ifdef __BIG_ENDIAN - 0x000a0000, -#else - 0x00080000, -#endif - 0x00000000, -}; - -const u32 r6xx_ps[] = -{ - 0x00000002, - 0x80800000, - 0x00000000, - 0x94200688, - 0x00000010, - 0x000d1000, - 0xb0800000, - 0x00000000, -}; - -const u32 r6xx_ps_size = ARRAY_SIZE(r6xx_ps); -const u32 r6xx_vs_size = ARRAY_SIZE(r6xx_vs); -const u32 r6xx_default_size = ARRAY_SIZE(r6xx_default_state); -const u32 r7xx_default_size = ARRAY_SIZE(r7xx_default_state); diff --git a/sys/dev/pci/drm/radeon/r600_blit_shaders.h b/sys/dev/pci/drm/radeon/r600_blit_shaders.h deleted file mode 100644 index f437d36dd98..00000000000 --- a/sys/dev/pci/drm/radeon/r600_blit_shaders.h +++ /dev/null @@ -1,38 +0,0 @@ -/* - * Copyright 2009 Advanced Micro Devices, Inc. - * Copyright 2009 Red Hat Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice (including the next - * paragraph) shall be included in all copies or substantial portions of the - * Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - * - */ - -#ifndef R600_BLIT_SHADERS_H -#define R600_BLIT_SHADERS_H - -extern const u32 r6xx_ps[]; -extern const u32 r6xx_vs[]; -extern const u32 r7xx_default_state[]; -extern const u32 r6xx_default_state[]; - - -extern const u32 r6xx_ps_size, r6xx_vs_size; -extern const u32 r6xx_default_size, r7xx_default_size; - -#endif diff --git a/sys/dev/pci/drm/radeon/r600_cs.c b/sys/dev/pci/drm/radeon/r600_cs.c index 8be4799a98e..638f861af80 100644 --- a/sys/dev/pci/drm/radeon/r600_cs.c +++ b/sys/dev/pci/drm/radeon/r600_cs.c @@ -34,8 +34,6 @@ #include "r600_reg_safe.h" static int r600_nomm; -extern void r600_cs_legacy_get_tiling_conf(struct drm_device *dev, u32 *npipes, u32 *nbanks, u32 *group_size); - struct r600_cs_track { /* configuration we mirror so that we use same code btw kms/ums */ diff --git a/sys/dev/pci/drm/radeon/r600_dpm.c b/sys/dev/pci/drm/radeon/r600_dpm.c index 35b77c94470..9d2bcb9551e 100644 --- a/sys/dev/pci/drm/radeon/r600_dpm.c +++ b/sys/dev/pci/drm/radeon/r600_dpm.c @@ -820,12 +820,12 @@ union fan_info { static int r600_parse_clk_voltage_dep_table(struct radeon_clock_voltage_dependency_table *radeon_table, ATOM_PPLIB_Clock_Voltage_Dependency_Table *atom_table) { - u32 size = atom_table->ucNumEntries * - sizeof(struct radeon_clock_voltage_dependency_entry); int i; ATOM_PPLIB_Clock_Voltage_Dependency_Record *entry; - radeon_table->entries = kzalloc(size, GFP_KERNEL); + radeon_table->entries = kcalloc(atom_table->ucNumEntries, + sizeof(struct radeon_clock_voltage_dependency_entry), + GFP_KERNEL); if (!radeon_table->entries) return -ENOMEM; @@ -1361,7 +1361,9 @@ u16 r600_get_pcie_lane_support(struct radeon_device *rdev, u8 r600_encode_pci_lane_width(u32 lanes) { - u8 encoded_lanes[] = { 0, 1, 2, 0, 3, 0, 0, 0, 4, 0, 0, 0, 5, 0, 0, 0, 6 }; + static const u8 encoded_lanes[] = { + 0, 1, 2, 0, 3, 0, 0, 0, 4, 0, 0, 0, 5, 0, 0, 0, 6 + }; if (lanes > 16) return 0; diff --git a/sys/dev/pci/drm/radeon/radeon.h b/sys/dev/pci/drm/radeon/radeon.h index 7d79c1a1703..c68292e3bb6 100644 --- a/sys/dev/pci/drm/radeon/radeon.h +++ b/sys/dev/pci/drm/radeon/radeon.h @@ -127,7 +127,6 @@ extern int radeon_use_pflipirq; extern int radeon_bapm; extern int radeon_backlight; extern int radeon_auxch; -extern int radeon_mst; extern int radeon_uvd; extern int radeon_vce; extern int radeon_si_support; @@ -2508,8 +2507,6 @@ struct radeon_device { struct radeon_vm_manager vm_manager; struct rwlock gpu_clock_mutex; /* memory stats */ - atomic64_t vram_usage; - atomic64_t gtt_usage; atomic64_t num_bytes_moved; atomic_t gpu_reset_counter; /* ACPI interface */ @@ -2998,8 +2995,6 @@ struct radeon_hdmi_acr { }; -extern struct radeon_hdmi_acr r600_hdmi_acr(uint32_t clock); - extern u32 r6xx_remap_render_backend(struct radeon_device *rdev, u32 tiling_pipe_num, u32 max_rb_num, diff --git a/sys/dev/pci/drm/radeon/radeon_acpi.c b/sys/dev/pci/drm/radeon/radeon_acpi.c index 1baef7b493d..b603c0b7707 100644 --- a/sys/dev/pci/drm/radeon/radeon_acpi.c +++ b/sys/dev/pci/drm/radeon/radeon_acpi.c @@ -391,7 +391,6 @@ static int radeon_atif_handler(struct radeon_device *rdev, radeon_set_backlight_level(rdev, enc, req.backlight_level); -#if defined(CONFIG_BACKLIGHT_CLASS_DEVICE) || defined(CONFIG_BACKLIGHT_CLASS_DEVICE_MODULE) if (rdev->is_atom_bios) { struct radeon_encoder_atom_dig *dig = enc->enc_priv; backlight_force_update(dig->bl_dev, @@ -401,7 +400,6 @@ static int radeon_atif_handler(struct radeon_device *rdev, backlight_force_update(dig->bl_dev, BACKLIGHT_UPDATE_HOTKEY); } -#endif } } if (req.pending & ATIF_DGPU_DISPLAY_EVENT) { diff --git a/sys/dev/pci/drm/radeon/radeon_atombios.c b/sys/dev/pci/drm/radeon/radeon_atombios.c index 29f7a3bfe97..512c5e88417 100644 --- a/sys/dev/pci/drm/radeon/radeon_atombios.c +++ b/sys/dev/pci/drm/radeon/radeon_atombios.c @@ -830,8 +830,6 @@ bool radeon_get_atom_connector_info_from_object_table(struct drm_device *dev) } radeon_link_encoder_connector(dev); - - radeon_setup_mst_connector(dev); return true; } diff --git a/sys/dev/pci/drm/radeon/radeon_bios.c b/sys/dev/pci/drm/radeon/radeon_bios.c index 799c4f02614..d850ac56479 100644 --- a/sys/dev/pci/drm/radeon/radeon_bios.c +++ b/sys/dev/pci/drm/radeon/radeon_bios.c @@ -367,6 +367,7 @@ static bool radeon_atrm_get_bios(struct radeon_device *rdev) if (!found) return false; + pci_dev_put(pdev); rdev->bios = kmalloc(size, GFP_KERNEL); if (!rdev->bios) { @@ -762,13 +763,14 @@ static bool radeon_acpi_vfct_bios(struct radeon_device *rdev) acpi_size tbl_size; UEFI_ACPI_VFCT *vfct; unsigned offset; + bool r = false; if (!ACPI_SUCCESS(acpi_get_table("VFCT", 1, &hdr))) return false; tbl_size = hdr->length; if (tbl_size < sizeof(UEFI_ACPI_VFCT)) { DRM_ERROR("ACPI VFCT table present but broken (too short #1)\n"); - return false; + goto out; } vfct = (UEFI_ACPI_VFCT *)hdr; @@ -781,13 +783,13 @@ static bool radeon_acpi_vfct_bios(struct radeon_device *rdev) offset += sizeof(VFCT_IMAGE_HEADER); if (offset > tbl_size) { DRM_ERROR("ACPI VFCT image header truncated\n"); - return false; + goto out; } offset += vhdr->ImageLength; if (offset > tbl_size) { DRM_ERROR("ACPI VFCT image truncated\n"); - return false; + goto out; } if (vhdr->ImageLength && @@ -799,15 +801,18 @@ static bool radeon_acpi_vfct_bios(struct radeon_device *rdev) rdev->bios = kmemdup(&vbios->VbiosContent, vhdr->ImageLength, GFP_KERNEL); + if (rdev->bios) + r = true; - if (!rdev->bios) - return false; - return true; + goto out; } } DRM_ERROR("ACPI VFCT table present but broken (too short #2)\n"); - return false; + +out: + acpi_put_table(hdr); + return r; } #else static inline bool radeon_acpi_vfct_bios(struct radeon_device *rdev) diff --git a/sys/dev/pci/drm/radeon/radeon_connectors.c b/sys/dev/pci/drm/radeon/radeon_connectors.c index d157bb9072e..f7431d22460 100644 --- a/sys/dev/pci/drm/radeon/radeon_connectors.c +++ b/sys/dev/pci/drm/radeon/radeon_connectors.c @@ -24,10 +24,10 @@ * Alex Deucher */ +#include <drm/display/drm_dp_mst_helper.h> #include <drm/drm_edid.h> #include <drm/drm_crtc_helper.h> #include <drm/drm_fb_helper.h> -#include <drm/drm_dp_mst_helper.h> #include <drm/drm_probe_helper.h> #include <drm/radeon_drm.h> #include "radeon.h" @@ -37,33 +37,12 @@ #include <linux/pm_runtime.h> #include <linux/vga_switcheroo.h> -static int radeon_dp_handle_hpd(struct drm_connector *connector) -{ - struct radeon_connector *radeon_connector = to_radeon_connector(connector); - int ret; - - ret = radeon_dp_mst_check_status(radeon_connector); - if (ret == -EINVAL) - return 1; - return 0; -} void radeon_connector_hotplug(struct drm_connector *connector) { struct drm_device *dev = connector->dev; struct radeon_device *rdev = dev->dev_private; struct radeon_connector *radeon_connector = to_radeon_connector(connector); - if (connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort) { - struct radeon_connector_atom_dig *dig_connector = - radeon_connector->con_priv; - - if (radeon_connector->is_mst_connector) - return; - if (dig_connector->is_mst) { - radeon_dp_handle_hpd(connector); - return; - } - } /* bail if the connector does not have hpd pin, e.g., * VGA, TV, etc. */ @@ -781,7 +760,7 @@ static void radeon_fixup_lvds_native_mode(struct drm_encoder *encoder, if (mode->type & DRM_MODE_TYPE_PREFERRED) { if (mode->hdisplay != native_mode->hdisplay || mode->vdisplay != native_mode->vdisplay) - memcpy(native_mode, mode, sizeof(*mode)); + drm_mode_copy(native_mode, mode); } } @@ -790,7 +769,7 @@ static void radeon_fixup_lvds_native_mode(struct drm_encoder *encoder, list_for_each_entry_safe(mode, t, &connector->probed_modes, head) { if (mode->hdisplay == native_mode->hdisplay && mode->vdisplay == native_mode->vdisplay) { - *native_mode = *mode; + drm_mode_copy(native_mode, mode); drm_mode_set_crtcinfo(native_mode, CRTC_INTERLACE_HALVE_V); DRM_DEBUG_KMS("Determined LVDS native mode details from EDID\n"); break; @@ -1664,9 +1643,6 @@ radeon_dp_detect(struct drm_connector *connector, bool force) struct drm_encoder *encoder = radeon_best_single_encoder(connector); int r; - if (radeon_dig_connector->is_mst) - return connector_status_disconnected; - if (!drm_kms_helper_is_poll_worker()) { r = pm_runtime_get_sync(connector->dev->dev); if (r < 0) { @@ -1729,21 +1705,12 @@ radeon_dp_detect(struct drm_connector *connector, bool force) radeon_dig_connector->dp_sink_type = radeon_dp_getsinktype(radeon_connector); if (radeon_hpd_sense(rdev, radeon_connector->hpd.hpd)) { ret = connector_status_connected; - if (radeon_dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) { + if (radeon_dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) radeon_dp_getdpcd(radeon_connector); - r = radeon_dp_mst_probe(radeon_connector); - if (r == 1) - ret = connector_status_disconnected; - } } else { if (radeon_dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) { - if (radeon_dp_getdpcd(radeon_connector)) { - r = radeon_dp_mst_probe(radeon_connector); - if (r == 1) - ret = connector_status_disconnected; - else - ret = connector_status_connected; - } + if (radeon_dp_getdpcd(radeon_connector)) + ret = connector_status_connected; } else { /* try non-aux ddc (DP to DVI/HDMI/etc. adapter) */ if (radeon_ddc_probe(radeon_connector, false)) @@ -2561,25 +2528,3 @@ radeon_add_legacy_connector(struct drm_device *dev, connector->display_info.subpixel_order = subpixel_order; drm_connector_register(connector); } - -void radeon_setup_mst_connector(struct drm_device *dev) -{ - struct radeon_device *rdev = dev->dev_private; - struct drm_connector *connector; - struct radeon_connector *radeon_connector; - - if (!ASIC_IS_DCE5(rdev)) - return; - - if (radeon_mst == 0) - return; - - list_for_each_entry(connector, &dev->mode_config.connector_list, head) { - radeon_connector = to_radeon_connector(connector); - - if (connector->connector_type != DRM_MODE_CONNECTOR_DisplayPort) - continue; - - radeon_dp_mst_init(radeon_connector); - } -} diff --git a/sys/dev/pci/drm/radeon/radeon_cs.c b/sys/dev/pci/drm/radeon/radeon_cs.c index 3d3054d280b..820d50c3ca5 100644 --- a/sys/dev/pci/drm/radeon/radeon_cs.c +++ b/sys/dev/pci/drm/radeon/radeon_cs.c @@ -539,6 +539,10 @@ static int radeon_bo_vm_update_pte(struct radeon_cs_parser *p, return r; radeon_sync_fence(&p->ib.sync, bo_va->last_pt_update); + + r = dma_resv_reserve_fences(bo->tbo.base.resv, 1); + if (r) + return r; } return radeon_vm_clear_invalids(rdev, vm); diff --git a/sys/dev/pci/drm/radeon/radeon_device.c b/sys/dev/pci/drm/radeon/radeon_device.c index de1220779d0..d60e79f1c70 100644 --- a/sys/dev/pci/drm/radeon/radeon_device.c +++ b/sys/dev/pci/drm/radeon/radeon_device.c @@ -38,6 +38,7 @@ #include <drm/drm_crtc_helper.h> #include <drm/drm_device.h> #include <drm/drm_file.h> +#include <drm/drm_framebuffer.h> #include <drm/drm_probe_helper.h> #include <drm/radeon_drm.h> @@ -1099,19 +1100,6 @@ static unsigned int radeon_vga_set_decode(struct pci_dev *pdev, bool state) } /** - * radeon_check_pot_argument - check that argument is a power of two - * - * @arg: value to check - * - * Validates that a certain argument is a power of two (all asics). - * Returns true if argument is valid. - */ -static bool radeon_check_pot_argument(int arg) -{ - return (arg & (arg - 1)) == 0; -} - -/** * radeon_gart_size_auto - Determine a sensible default GART size * according to ASIC family. * @@ -1139,7 +1127,7 @@ static int radeon_gart_size_auto(enum radeon_family family) static void radeon_check_arguments(struct radeon_device *rdev) { /* vramlimit must be a power of two */ - if (!radeon_check_pot_argument(radeon_vram_limit)) { + if (radeon_vram_limit != 0 && !is_power_of_2(radeon_vram_limit)) { dev_warn(rdev->dev, "vram limit (%d) must be a power of 2\n", radeon_vram_limit); radeon_vram_limit = 0; @@ -1153,7 +1141,7 @@ static void radeon_check_arguments(struct radeon_device *rdev) dev_warn(rdev->dev, "gart size (%d) too small\n", radeon_gart_size); radeon_gart_size = radeon_gart_size_auto(rdev->family); - } else if (!radeon_check_pot_argument(radeon_gart_size)) { + } else if (!is_power_of_2(radeon_gart_size)) { dev_warn(rdev->dev, "gart size (%d) must be a power of 2\n", radeon_gart_size); radeon_gart_size = radeon_gart_size_auto(rdev->family); @@ -1176,7 +1164,7 @@ static void radeon_check_arguments(struct radeon_device *rdev) break; } - if (!radeon_check_pot_argument(radeon_vm_size)) { + if (!is_power_of_2(radeon_vm_size)) { dev_warn(rdev->dev, "VM size (%d) must be a power of 2\n", radeon_vm_size); radeon_vm_size = 4; @@ -1471,7 +1459,6 @@ int radeon_device_init(struct radeon_device *rdev, goto failed; radeon_gem_debugfs_init(rdev); - radeon_mst_debugfs_init(rdev); if (rdev->flags & RADEON_IS_AGP && !rdev->accel_working) { /* Acceleration not working on AGP card try again diff --git a/sys/dev/pci/drm/radeon/radeon_display.c b/sys/dev/pci/drm/radeon/radeon_display.c index cc1dee52d28..d794fe7b9c8 100644 --- a/sys/dev/pci/drm/radeon/radeon_display.c +++ b/sys/dev/pci/drm/radeon/radeon_display.c @@ -36,8 +36,8 @@ #include <drm/drm_edid.h> #include <drm/drm_fb_helper.h> #include <drm/drm_fourcc.h> +#include <drm/drm_framebuffer.h> #include <drm/drm_gem_framebuffer_helper.h> -#include <drm/drm_plane_helper.h> #include <drm/drm_probe_helper.h> #include <drm/drm_vblank.h> #include <drm/radeon_drm.h> @@ -533,7 +533,13 @@ static int radeon_crtc_page_flip_target(struct drm_crtc *crtc, DRM_ERROR("failed to pin new rbo buffer before flip\n"); goto cleanup; } - work->fence = dma_fence_get(dma_resv_excl_fence(new_rbo->tbo.base.resv)); + r = dma_resv_get_singleton(new_rbo->tbo.base.resv, DMA_RESV_USAGE_WRITE, + &work->fence); + if (r) { + radeon_bo_unreserve(new_rbo); + DRM_ERROR("failed to get new rbo buffer fences\n"); + goto cleanup; + } radeon_bo_get_tiling_flags(new_rbo, &tiling_flags, NULL); radeon_bo_unreserve(new_rbo); @@ -1596,6 +1602,8 @@ int radeon_modeset_init(struct radeon_device *rdev) rdev->ddev->mode_config.preferred_depth = 24; rdev->ddev->mode_config.prefer_shadow = 1; + rdev->ddev->mode_config.fb_modifiers_not_supported = true; + rdev->ddev->mode_config.fb_base = rdev->mc.aper_base; ret = radeon_modeset_create_props(rdev); diff --git a/sys/dev/pci/drm/radeon/radeon_dp_mst.c b/sys/dev/pci/drm/radeon/radeon_dp_mst.c deleted file mode 100644 index ec867fa880a..00000000000 --- a/sys/dev/pci/drm/radeon/radeon_dp_mst.c +++ /dev/null @@ -1,778 +0,0 @@ -// SPDX-License-Identifier: MIT - -#include <drm/drm_dp_mst_helper.h> -#include <drm/drm_fb_helper.h> -#include <drm/drm_file.h> -#include <drm/drm_probe_helper.h> - -#include "atom.h" -#include "ni_reg.h" -#include "radeon.h" - -static struct radeon_encoder *radeon_dp_create_fake_mst_encoder(struct radeon_connector *connector); - -static int radeon_atom_set_enc_offset(int id) -{ - static const int offsets[] = { EVERGREEN_CRTC0_REGISTER_OFFSET, - EVERGREEN_CRTC1_REGISTER_OFFSET, - EVERGREEN_CRTC2_REGISTER_OFFSET, - EVERGREEN_CRTC3_REGISTER_OFFSET, - EVERGREEN_CRTC4_REGISTER_OFFSET, - EVERGREEN_CRTC5_REGISTER_OFFSET, - 0x13830 - 0x7030 }; - - return offsets[id]; -} - -static int radeon_dp_mst_set_be_cntl(struct radeon_encoder *primary, - struct radeon_encoder_mst *mst_enc, - enum radeon_hpd_id hpd, bool enable) -{ - struct drm_device *dev = primary->base.dev; - struct radeon_device *rdev = dev->dev_private; - uint32_t reg; - int retries = 0; - uint32_t temp; - - reg = RREG32(NI_DIG_BE_CNTL + primary->offset); - - /* set MST mode */ - reg &= ~NI_DIG_FE_DIG_MODE(7); - reg |= NI_DIG_FE_DIG_MODE(NI_DIG_MODE_DP_MST); - - if (enable) - reg |= NI_DIG_FE_SOURCE_SELECT(1 << mst_enc->fe); - else - reg &= ~NI_DIG_FE_SOURCE_SELECT(1 << mst_enc->fe); - - reg |= NI_DIG_HPD_SELECT(hpd); - DRM_DEBUG_KMS("writing 0x%08x 0x%08x\n", NI_DIG_BE_CNTL + primary->offset, reg); - WREG32(NI_DIG_BE_CNTL + primary->offset, reg); - - if (enable) { - uint32_t offset = radeon_atom_set_enc_offset(mst_enc->fe); - - do { - temp = RREG32(NI_DIG_FE_CNTL + offset); - } while ((temp & NI_DIG_SYMCLK_FE_ON) && retries++ < 10000); - if (retries == 10000) - DRM_ERROR("timed out waiting for FE %d %d\n", primary->offset, mst_enc->fe); - } - return 0; -} - -static int radeon_dp_mst_set_stream_attrib(struct radeon_encoder *primary, - int stream_number, - int fe, - int slots) -{ - struct drm_device *dev = primary->base.dev; - struct radeon_device *rdev = dev->dev_private; - u32 temp, val; - int retries = 0; - int satreg, satidx; - - satreg = stream_number >> 1; - satidx = stream_number & 1; - - temp = RREG32(NI_DP_MSE_SAT0 + satreg + primary->offset); - - val = NI_DP_MSE_SAT_SLOT_COUNT0(slots) | NI_DP_MSE_SAT_SRC0(fe); - - val <<= (16 * satidx); - - temp &= ~(0xffff << (16 * satidx)); - - temp |= val; - - DRM_DEBUG_KMS("writing 0x%08x 0x%08x\n", NI_DP_MSE_SAT0 + satreg + primary->offset, temp); - WREG32(NI_DP_MSE_SAT0 + satreg + primary->offset, temp); - - WREG32(NI_DP_MSE_SAT_UPDATE + primary->offset, 1); - - do { - unsigned value1, value2; - udelay(10); - temp = RREG32(NI_DP_MSE_SAT_UPDATE + primary->offset); - - value1 = temp & NI_DP_MSE_SAT_UPDATE_MASK; - value2 = temp & NI_DP_MSE_16_MTP_KEEPOUT; - - if (!value1 && !value2) - break; - } while (retries++ < 50); - - if (retries == 10000) - DRM_ERROR("timed out waitin for SAT update %d\n", primary->offset); - - /* MTP 16 ? */ - return 0; -} - -static int radeon_dp_mst_update_stream_attribs(struct radeon_connector *mst_conn, - struct radeon_encoder *primary) -{ - struct drm_device *dev = mst_conn->base.dev; - struct stream_attribs new_attribs[6]; - int i; - int idx = 0; - struct radeon_connector *radeon_connector; - struct drm_connector *connector; - - memset(new_attribs, 0, sizeof(new_attribs)); - list_for_each_entry(connector, &dev->mode_config.connector_list, head) { - struct radeon_encoder *subenc; - struct radeon_encoder_mst *mst_enc; - - radeon_connector = to_radeon_connector(connector); - if (!radeon_connector->is_mst_connector) - continue; - - if (radeon_connector->mst_port != mst_conn) - continue; - - subenc = radeon_connector->mst_encoder; - mst_enc = subenc->enc_priv; - - if (!mst_enc->enc_active) - continue; - - new_attribs[idx].fe = mst_enc->fe; - new_attribs[idx].slots = drm_dp_mst_get_vcpi_slots(&mst_conn->mst_mgr, mst_enc->port); - idx++; - } - - for (i = 0; i < idx; i++) { - if (new_attribs[i].fe != mst_conn->cur_stream_attribs[i].fe || - new_attribs[i].slots != mst_conn->cur_stream_attribs[i].slots) { - radeon_dp_mst_set_stream_attrib(primary, i, new_attribs[i].fe, new_attribs[i].slots); - mst_conn->cur_stream_attribs[i].fe = new_attribs[i].fe; - mst_conn->cur_stream_attribs[i].slots = new_attribs[i].slots; - } - } - - for (i = idx; i < mst_conn->enabled_attribs; i++) { - radeon_dp_mst_set_stream_attrib(primary, i, 0, 0); - mst_conn->cur_stream_attribs[i].fe = 0; - mst_conn->cur_stream_attribs[i].slots = 0; - } - mst_conn->enabled_attribs = idx; - return 0; -} - -static int radeon_dp_mst_set_vcp_size(struct radeon_encoder *mst, s64 avg_time_slots_per_mtp) -{ - struct drm_device *dev = mst->base.dev; - struct radeon_device *rdev = dev->dev_private; - struct radeon_encoder_mst *mst_enc = mst->enc_priv; - uint32_t val, temp; - uint32_t offset = radeon_atom_set_enc_offset(mst_enc->fe); - int retries = 0; - uint32_t x = drm_fixp2int(avg_time_slots_per_mtp); - uint32_t y = drm_fixp2int_ceil((avg_time_slots_per_mtp - x) << 26); - - val = NI_DP_MSE_RATE_X(x) | NI_DP_MSE_RATE_Y(y); - - WREG32(NI_DP_MSE_RATE_CNTL + offset, val); - - do { - temp = RREG32(NI_DP_MSE_RATE_UPDATE + offset); - udelay(10); - } while ((temp & 0x1) && (retries++ < 10000)); - - if (retries >= 10000) - DRM_ERROR("timed out wait for rate cntl %d\n", mst_enc->fe); - return 0; -} - -static int radeon_dp_mst_get_ddc_modes(struct drm_connector *connector) -{ - struct radeon_connector *radeon_connector = to_radeon_connector(connector); - struct radeon_connector *master = radeon_connector->mst_port; - struct edid *edid; - int ret = 0; - - edid = drm_dp_mst_get_edid(connector, &master->mst_mgr, radeon_connector->port); - radeon_connector->edid = edid; - DRM_DEBUG_KMS("edid retrieved %p\n", edid); - if (radeon_connector->edid) { - drm_connector_update_edid_property(&radeon_connector->base, radeon_connector->edid); - ret = drm_add_edid_modes(&radeon_connector->base, radeon_connector->edid); - return ret; - } - drm_connector_update_edid_property(&radeon_connector->base, NULL); - - return ret; -} - -static int radeon_dp_mst_get_modes(struct drm_connector *connector) -{ - return radeon_dp_mst_get_ddc_modes(connector); -} - -static enum drm_mode_status -radeon_dp_mst_mode_valid(struct drm_connector *connector, - struct drm_display_mode *mode) -{ - /* TODO - validate mode against available PBN for link */ - if (mode->clock < 10000) - return MODE_CLOCK_LOW; - - if (mode->flags & DRM_MODE_FLAG_DBLCLK) - return MODE_H_ILLEGAL; - - return MODE_OK; -} - -static struct -drm_encoder *radeon_mst_best_encoder(struct drm_connector *connector) -{ - struct radeon_connector *radeon_connector = to_radeon_connector(connector); - - return &radeon_connector->mst_encoder->base; -} - -static int -radeon_dp_mst_detect(struct drm_connector *connector, - struct drm_modeset_acquire_ctx *ctx, - bool force) -{ - struct radeon_connector *radeon_connector = - to_radeon_connector(connector); - struct radeon_connector *master = radeon_connector->mst_port; - - if (drm_connector_is_unregistered(connector)) - return connector_status_disconnected; - - return drm_dp_mst_detect_port(connector, ctx, &master->mst_mgr, - radeon_connector->port); -} - -static const struct drm_connector_helper_funcs radeon_dp_mst_connector_helper_funcs = { - .get_modes = radeon_dp_mst_get_modes, - .mode_valid = radeon_dp_mst_mode_valid, - .best_encoder = radeon_mst_best_encoder, - .detect_ctx = radeon_dp_mst_detect, -}; - -static void -radeon_dp_mst_connector_destroy(struct drm_connector *connector) -{ - struct radeon_connector *radeon_connector = to_radeon_connector(connector); - struct radeon_encoder *radeon_encoder = radeon_connector->mst_encoder; - - drm_encoder_cleanup(&radeon_encoder->base); - kfree(radeon_encoder); - drm_connector_cleanup(connector); - kfree(radeon_connector); -} - -static const struct drm_connector_funcs radeon_dp_mst_connector_funcs = { - .dpms = drm_helper_connector_dpms, - .fill_modes = drm_helper_probe_single_connector_modes, - .destroy = radeon_dp_mst_connector_destroy, -}; - -static struct drm_connector *radeon_dp_add_mst_connector(struct drm_dp_mst_topology_mgr *mgr, - struct drm_dp_mst_port *port, - const char *pathprop) -{ - struct radeon_connector *master = container_of(mgr, struct radeon_connector, mst_mgr); - struct drm_device *dev = master->base.dev; - struct radeon_connector *radeon_connector; - struct drm_connector *connector; - - radeon_connector = kzalloc(sizeof(*radeon_connector), GFP_KERNEL); - if (!radeon_connector) - return NULL; - - radeon_connector->is_mst_connector = true; - connector = &radeon_connector->base; - radeon_connector->port = port; - radeon_connector->mst_port = master; - DRM_DEBUG_KMS("\n"); - - drm_connector_init(dev, connector, &radeon_dp_mst_connector_funcs, DRM_MODE_CONNECTOR_DisplayPort); - drm_connector_helper_add(connector, &radeon_dp_mst_connector_helper_funcs); - radeon_connector->mst_encoder = radeon_dp_create_fake_mst_encoder(master); - - drm_object_attach_property(&connector->base, dev->mode_config.path_property, 0); - drm_object_attach_property(&connector->base, dev->mode_config.tile_property, 0); - drm_connector_set_path_property(connector, pathprop); - - return connector; -} - -static const struct drm_dp_mst_topology_cbs mst_cbs = { - .add_connector = radeon_dp_add_mst_connector, -}; - -static struct -radeon_connector *radeon_mst_find_connector(struct drm_encoder *encoder) -{ - struct drm_device *dev = encoder->dev; - struct drm_connector *connector; - - list_for_each_entry(connector, &dev->mode_config.connector_list, head) { - struct radeon_connector *radeon_connector = to_radeon_connector(connector); - if (!connector->encoder) - continue; - if (!radeon_connector->is_mst_connector) - continue; - - DRM_DEBUG_KMS("checking %p vs %p\n", connector->encoder, encoder); - if (connector->encoder == encoder) - return radeon_connector; - } - return NULL; -} - -void radeon_dp_mst_prepare_pll(struct drm_crtc *crtc, struct drm_display_mode *mode) -{ - struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); - struct drm_device *dev = crtc->dev; - struct radeon_device *rdev = dev->dev_private; - struct radeon_encoder *radeon_encoder = to_radeon_encoder(radeon_crtc->encoder); - struct radeon_encoder_mst *mst_enc = radeon_encoder->enc_priv; - struct radeon_connector *radeon_connector = radeon_mst_find_connector(&radeon_encoder->base); - int dp_clock; - struct radeon_connector_atom_dig *dig_connector = mst_enc->connector->con_priv; - - if (radeon_connector) { - radeon_connector->pixelclock_for_modeset = mode->clock; - if (radeon_connector->base.display_info.bpc) - radeon_crtc->bpc = radeon_connector->base.display_info.bpc; - else - radeon_crtc->bpc = 8; - } - - DRM_DEBUG_KMS("dp_clock %p %d\n", dig_connector, dig_connector->dp_clock); - dp_clock = dig_connector->dp_clock; - radeon_crtc->ss_enabled = - radeon_atombios_get_asic_ss_info(rdev, &radeon_crtc->ss, - ASIC_INTERNAL_SS_ON_DP, - dp_clock); -} - -static void -radeon_mst_encoder_dpms(struct drm_encoder *encoder, int mode) -{ - struct drm_device *dev = encoder->dev; - struct radeon_device *rdev = dev->dev_private; - struct radeon_encoder *radeon_encoder, *primary; - struct radeon_encoder_mst *mst_enc; - struct radeon_encoder_atom_dig *dig_enc; - struct radeon_connector *radeon_connector; - struct drm_crtc *crtc; - struct radeon_crtc *radeon_crtc; - int slots; - s64 fixed_pbn, fixed_pbn_per_slot, avg_time_slots_per_mtp; - if (!ASIC_IS_DCE5(rdev)) { - DRM_ERROR("got mst dpms on non-DCE5\n"); - return; - } - - radeon_connector = radeon_mst_find_connector(encoder); - if (!radeon_connector) - return; - - radeon_encoder = to_radeon_encoder(encoder); - - mst_enc = radeon_encoder->enc_priv; - - primary = mst_enc->primary; - - dig_enc = primary->enc_priv; - - crtc = encoder->crtc; - DRM_DEBUG_KMS("got connector %d\n", dig_enc->active_mst_links); - - switch (mode) { - case DRM_MODE_DPMS_ON: - dig_enc->active_mst_links++; - - radeon_crtc = to_radeon_crtc(crtc); - - if (dig_enc->active_mst_links == 1) { - mst_enc->fe = dig_enc->dig_encoder; - mst_enc->fe_from_be = true; - atombios_set_mst_encoder_crtc_source(encoder, mst_enc->fe); - - atombios_dig_encoder_setup(&primary->base, ATOM_ENCODER_CMD_SETUP, 0); - atombios_dig_transmitter_setup2(&primary->base, ATOM_TRANSMITTER_ACTION_ENABLE, - 0, 0, dig_enc->dig_encoder); - - if (radeon_dp_needs_link_train(mst_enc->connector) || - dig_enc->active_mst_links == 1) { - radeon_dp_link_train(&primary->base, &mst_enc->connector->base); - } - - } else { - mst_enc->fe = radeon_atom_pick_dig_encoder(encoder, radeon_crtc->crtc_id); - if (mst_enc->fe == -1) - DRM_ERROR("failed to get frontend for dig encoder\n"); - mst_enc->fe_from_be = false; - atombios_set_mst_encoder_crtc_source(encoder, mst_enc->fe); - } - - DRM_DEBUG_KMS("dig encoder is %d %d %d\n", dig_enc->dig_encoder, - dig_enc->linkb, radeon_crtc->crtc_id); - - slots = drm_dp_find_vcpi_slots(&radeon_connector->mst_port->mst_mgr, - mst_enc->pbn); - drm_dp_mst_allocate_vcpi(&radeon_connector->mst_port->mst_mgr, - radeon_connector->port, - mst_enc->pbn, slots); - drm_dp_update_payload_part1(&radeon_connector->mst_port->mst_mgr); - - radeon_dp_mst_set_be_cntl(primary, mst_enc, - radeon_connector->mst_port->hpd.hpd, true); - - mst_enc->enc_active = true; - radeon_dp_mst_update_stream_attribs(radeon_connector->mst_port, primary); - - fixed_pbn = drm_int2fixp(mst_enc->pbn); - fixed_pbn_per_slot = drm_int2fixp(radeon_connector->mst_port->mst_mgr.pbn_div); - avg_time_slots_per_mtp = drm_fixp_div(fixed_pbn, fixed_pbn_per_slot); - radeon_dp_mst_set_vcp_size(radeon_encoder, avg_time_slots_per_mtp); - - atombios_dig_encoder_setup2(&primary->base, ATOM_ENCODER_CMD_DP_VIDEO_ON, 0, - mst_enc->fe); - drm_dp_check_act_status(&radeon_connector->mst_port->mst_mgr); - - drm_dp_update_payload_part2(&radeon_connector->mst_port->mst_mgr); - - break; - case DRM_MODE_DPMS_STANDBY: - case DRM_MODE_DPMS_SUSPEND: - case DRM_MODE_DPMS_OFF: - DRM_ERROR("DPMS OFF %d\n", dig_enc->active_mst_links); - - if (!mst_enc->enc_active) - return; - - drm_dp_mst_reset_vcpi_slots(&radeon_connector->mst_port->mst_mgr, mst_enc->port); - drm_dp_update_payload_part1(&radeon_connector->mst_port->mst_mgr); - - drm_dp_check_act_status(&radeon_connector->mst_port->mst_mgr); - /* and this can also fail */ - drm_dp_update_payload_part2(&radeon_connector->mst_port->mst_mgr); - - drm_dp_mst_deallocate_vcpi(&radeon_connector->mst_port->mst_mgr, mst_enc->port); - - mst_enc->enc_active = false; - radeon_dp_mst_update_stream_attribs(radeon_connector->mst_port, primary); - - radeon_dp_mst_set_be_cntl(primary, mst_enc, - radeon_connector->mst_port->hpd.hpd, false); - atombios_dig_encoder_setup2(&primary->base, ATOM_ENCODER_CMD_DP_VIDEO_OFF, 0, - mst_enc->fe); - - if (!mst_enc->fe_from_be) - radeon_atom_release_dig_encoder(rdev, mst_enc->fe); - - mst_enc->fe_from_be = false; - dig_enc->active_mst_links--; - if (dig_enc->active_mst_links == 0) { - /* drop link */ - } - - break; - } - -} - -static bool radeon_mst_mode_fixup(struct drm_encoder *encoder, - const struct drm_display_mode *mode, - struct drm_display_mode *adjusted_mode) -{ - struct radeon_encoder_mst *mst_enc; - struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); - struct radeon_connector_atom_dig *dig_connector; - int bpp = 24; - - mst_enc = radeon_encoder->enc_priv; - - mst_enc->pbn = drm_dp_calc_pbn_mode(adjusted_mode->clock, bpp, false); - - mst_enc->primary->active_device = mst_enc->primary->devices & mst_enc->connector->devices; - DRM_DEBUG_KMS("setting active device to %08x from %08x %08x for encoder %d\n", - mst_enc->primary->active_device, mst_enc->primary->devices, - mst_enc->connector->devices, mst_enc->primary->base.encoder_type); - - - drm_mode_set_crtcinfo(adjusted_mode, 0); - dig_connector = mst_enc->connector->con_priv; - dig_connector->dp_lane_count = drm_dp_max_lane_count(dig_connector->dpcd); - dig_connector->dp_clock = drm_dp_max_link_rate(dig_connector->dpcd); - DRM_DEBUG_KMS("dig clock %p %d %d\n", dig_connector, - dig_connector->dp_lane_count, dig_connector->dp_clock); - return true; -} - -static void radeon_mst_encoder_prepare(struct drm_encoder *encoder) -{ - struct radeon_connector *radeon_connector; - struct radeon_encoder *radeon_encoder, *primary; - struct radeon_encoder_mst *mst_enc; - struct radeon_encoder_atom_dig *dig_enc; - - radeon_connector = radeon_mst_find_connector(encoder); - if (!radeon_connector) { - DRM_DEBUG_KMS("failed to find connector %p\n", encoder); - return; - } - radeon_encoder = to_radeon_encoder(encoder); - - radeon_mst_encoder_dpms(encoder, DRM_MODE_DPMS_OFF); - - mst_enc = radeon_encoder->enc_priv; - - primary = mst_enc->primary; - - dig_enc = primary->enc_priv; - - mst_enc->port = radeon_connector->port; - - if (dig_enc->dig_encoder == -1) { - dig_enc->dig_encoder = radeon_atom_pick_dig_encoder(&primary->base, -1); - primary->offset = radeon_atom_set_enc_offset(dig_enc->dig_encoder); - atombios_set_mst_encoder_crtc_source(encoder, dig_enc->dig_encoder); - - - } - DRM_DEBUG_KMS("%d %d\n", dig_enc->dig_encoder, primary->offset); -} - -static void -radeon_mst_encoder_mode_set(struct drm_encoder *encoder, - struct drm_display_mode *mode, - struct drm_display_mode *adjusted_mode) -{ - DRM_DEBUG_KMS("\n"); -} - -static void radeon_mst_encoder_commit(struct drm_encoder *encoder) -{ - radeon_mst_encoder_dpms(encoder, DRM_MODE_DPMS_ON); - DRM_DEBUG_KMS("\n"); -} - -static const struct drm_encoder_helper_funcs radeon_mst_helper_funcs = { - .dpms = radeon_mst_encoder_dpms, - .mode_fixup = radeon_mst_mode_fixup, - .prepare = radeon_mst_encoder_prepare, - .mode_set = radeon_mst_encoder_mode_set, - .commit = radeon_mst_encoder_commit, -}; - -static void radeon_dp_mst_encoder_destroy(struct drm_encoder *encoder) -{ - drm_encoder_cleanup(encoder); - kfree(encoder); -} - -static const struct drm_encoder_funcs radeon_dp_mst_enc_funcs = { - .destroy = radeon_dp_mst_encoder_destroy, -}; - -static struct radeon_encoder * -radeon_dp_create_fake_mst_encoder(struct radeon_connector *connector) -{ - struct drm_device *dev = connector->base.dev; - struct radeon_device *rdev = dev->dev_private; - struct radeon_encoder *radeon_encoder; - struct radeon_encoder_mst *mst_enc; - struct drm_encoder *encoder; - const struct drm_connector_helper_funcs *connector_funcs = connector->base.helper_private; - struct drm_encoder *enc_master = connector_funcs->best_encoder(&connector->base); - - DRM_DEBUG_KMS("enc master is %p\n", enc_master); - radeon_encoder = kzalloc(sizeof(*radeon_encoder), GFP_KERNEL); - if (!radeon_encoder) - return NULL; - - radeon_encoder->enc_priv = kzalloc(sizeof(*mst_enc), GFP_KERNEL); - if (!radeon_encoder->enc_priv) { - kfree(radeon_encoder); - return NULL; - } - encoder = &radeon_encoder->base; - switch (rdev->num_crtc) { - case 1: - encoder->possible_crtcs = 0x1; - break; - case 2: - default: - encoder->possible_crtcs = 0x3; - break; - case 4: - encoder->possible_crtcs = 0xf; - break; - case 6: - encoder->possible_crtcs = 0x3f; - break; - } - - drm_encoder_init(dev, &radeon_encoder->base, &radeon_dp_mst_enc_funcs, - DRM_MODE_ENCODER_DPMST, NULL); - drm_encoder_helper_add(encoder, &radeon_mst_helper_funcs); - - mst_enc = radeon_encoder->enc_priv; - mst_enc->connector = connector; - mst_enc->primary = to_radeon_encoder(enc_master); - radeon_encoder->is_mst_encoder = true; - return radeon_encoder; -} - -int -radeon_dp_mst_init(struct radeon_connector *radeon_connector) -{ - struct drm_device *dev = radeon_connector->base.dev; - int max_link_rate; - - if (!radeon_connector->ddc_bus->has_aux) - return 0; - - if (radeon_connector_is_dp12_capable(&radeon_connector->base)) - max_link_rate = 0x14; - else - max_link_rate = 0x0a; - - radeon_connector->mst_mgr.cbs = &mst_cbs; - return drm_dp_mst_topology_mgr_init(&radeon_connector->mst_mgr, dev, - &radeon_connector->ddc_bus->aux, 16, 6, - 4, drm_dp_bw_code_to_link_rate(max_link_rate), - radeon_connector->base.base.id); -} - -int -radeon_dp_mst_probe(struct radeon_connector *radeon_connector) -{ - struct radeon_connector_atom_dig *dig_connector = radeon_connector->con_priv; - struct drm_device *dev = radeon_connector->base.dev; - struct radeon_device *rdev = dev->dev_private; - int ret; - u8 msg[1]; - - if (!radeon_mst) - return 0; - - if (!ASIC_IS_DCE5(rdev)) - return 0; - - if (dig_connector->dpcd[DP_DPCD_REV] < 0x12) - return 0; - - ret = drm_dp_dpcd_read(&radeon_connector->ddc_bus->aux, DP_MSTM_CAP, msg, - 1); - if (ret) { - if (msg[0] & DP_MST_CAP) { - DRM_DEBUG_KMS("Sink is MST capable\n"); - dig_connector->is_mst = true; - } else { - DRM_DEBUG_KMS("Sink is not MST capable\n"); - dig_connector->is_mst = false; - } - - } - drm_dp_mst_topology_mgr_set_mst(&radeon_connector->mst_mgr, - dig_connector->is_mst); - return dig_connector->is_mst; -} - -int -radeon_dp_mst_check_status(struct radeon_connector *radeon_connector) -{ - struct radeon_connector_atom_dig *dig_connector = radeon_connector->con_priv; - int retry; - - if (dig_connector->is_mst) { - u8 esi[16] = { 0 }; - int dret; - int ret = 0; - bool handled; - - dret = drm_dp_dpcd_read(&radeon_connector->ddc_bus->aux, - DP_SINK_COUNT_ESI, esi, 8); -go_again: - if (dret == 8) { - DRM_DEBUG_KMS("got esi %3ph\n", esi); - ret = drm_dp_mst_hpd_irq(&radeon_connector->mst_mgr, esi, &handled); - - if (handled) { - for (retry = 0; retry < 3; retry++) { - int wret; - wret = drm_dp_dpcd_write(&radeon_connector->ddc_bus->aux, - DP_SINK_COUNT_ESI + 1, &esi[1], 3); - if (wret == 3) - break; - } - - dret = drm_dp_dpcd_read(&radeon_connector->ddc_bus->aux, - DP_SINK_COUNT_ESI, esi, 8); - if (dret == 8) { - DRM_DEBUG_KMS("got esi2 %3ph\n", esi); - goto go_again; - } - } else - ret = 0; - - return ret; - } else { - DRM_DEBUG_KMS("failed to get ESI - device may have failed %d\n", ret); - dig_connector->is_mst = false; - drm_dp_mst_topology_mgr_set_mst(&radeon_connector->mst_mgr, - dig_connector->is_mst); - /* send a hotplug event */ - } - } - return -EINVAL; -} - -#if defined(CONFIG_DEBUG_FS) - -static int radeon_debugfs_mst_info_show(struct seq_file *m, void *unused) -{ - struct radeon_device *rdev = (struct radeon_device *)m->private; - struct drm_device *dev = rdev->ddev; - struct drm_connector *connector; - struct radeon_connector *radeon_connector; - struct radeon_connector_atom_dig *dig_connector; - int i; - - drm_modeset_lock_all(dev); - list_for_each_entry(connector, &dev->mode_config.connector_list, head) { - if (connector->connector_type != DRM_MODE_CONNECTOR_DisplayPort) - continue; - - radeon_connector = to_radeon_connector(connector); - dig_connector = radeon_connector->con_priv; - if (radeon_connector->is_mst_connector) - continue; - if (!dig_connector->is_mst) - continue; - drm_dp_mst_dump_topology(m, &radeon_connector->mst_mgr); - - for (i = 0; i < radeon_connector->enabled_attribs; i++) - seq_printf(m, "attrib %d: %d %d\n", i, - radeon_connector->cur_stream_attribs[i].fe, - radeon_connector->cur_stream_attribs[i].slots); - } - drm_modeset_unlock_all(dev); - return 0; -} - -DEFINE_SHOW_ATTRIBUTE(radeon_debugfs_mst_info); -#endif - -void radeon_mst_debugfs_init(struct radeon_device *rdev) -{ -#if defined(CONFIG_DEBUG_FS) - struct dentry *root = rdev->ddev->primary->debugfs_root; - - debugfs_create_file("radeon_mst_info", 0444, root, rdev, - &radeon_debugfs_mst_info_fops); - -#endif -} diff --git a/sys/dev/pci/drm/radeon/radeon_drv.c b/sys/dev/pci/drm/radeon/radeon_drv.c index be89fa6b553..8d3e97f1ef5 100644 --- a/sys/dev/pci/drm/radeon/radeon_drv.c +++ b/sys/dev/pci/drm/radeon/radeon_drv.c @@ -31,7 +31,6 @@ #include <linux/compat.h> -#include <linux/console.h> #include <linux/module.h> #include <linux/pm_runtime.h> #include <linux/vga_switcheroo.h> @@ -175,7 +174,6 @@ int radeon_use_pflipirq = 2; int radeon_bapm = -1; int radeon_backlight = -1; int radeon_auxch = -1; -int radeon_mst = 0; int radeon_uvd = 1; int radeon_vce = 1; @@ -266,9 +264,6 @@ module_param_named(backlight, radeon_backlight, int, 0444); MODULE_PARM_DESC(auxch, "Use native auxch experimental support (1 = enable, 0 = disable, -1 = auto)"); module_param_named(auxch, radeon_auxch, int, 0444); -MODULE_PARM_DESC(mst, "DisplayPort MST experimental support (1 = enable, 0 = disable)"); -module_param_named(mst, radeon_mst, int, 0444); - MODULE_PARM_DESC(uvd, "uvd enable/disable uvd support (1 = enable, 0 = disable)"); module_param_named(uvd, radeon_uvd, int, 0444); @@ -283,15 +278,13 @@ int radeon_cik_support = 1; MODULE_PARM_DESC(cik_support, "CIK support (1 = enabled (default), 0 = disabled)"); module_param_named(cik_support, radeon_cik_support, int, 0444); -const struct pci_device_id radeondrm_pciidlist[] = { +static const struct pci_device_id pciidlist[] = { radeon_PCI_IDS }; MODULE_DEVICE_TABLE(pci, pciidlist); -#ifdef notyet static const struct drm_driver kms_driver; -#endif #ifdef __linux__ static int radeon_pci_probe(struct pci_dev *pdev, @@ -522,14 +515,11 @@ long radeon_drm_ioctl(struct file *filp, static long radeon_kms_compat_ioctl(struct file *filp, unsigned int cmd, unsigned long arg) { unsigned int nr = DRM_IOCTL_NR(cmd); - int ret; if (nr < DRM_COMMAND_BASE) return drm_compat_ioctl(filp, cmd, arg); - ret = radeon_drm_ioctl(filp, cmd, arg); - - return ret; + return radeon_drm_ioctl(filp, cmd, arg); } #endif @@ -606,7 +596,7 @@ static const struct drm_ioctl_desc radeon_ioctls_kms[] = { DRM_IOCTL_DEF_DRV(RADEON_GEM_USERPTR, radeon_gem_userptr_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), }; -const struct drm_driver kms_driver = { +static const struct drm_driver kms_driver = { .driver_features = DRIVER_GEM | DRIVER_RENDER | DRIVER_MODESET, #ifdef notyet @@ -661,15 +651,11 @@ static struct pci_driver radeon_kms_pci_driver = { #ifdef notyet static int __init radeon_module_init(void) { - if (vgacon_text_force() && radeon_modeset == -1) { - DRM_INFO("VGACON disable radeon kernel modesetting.\n"); + if (drm_firmware_drivers_only() && radeon_modeset == -1) radeon_modeset = 0; - } - if (radeon_modeset == 0) { - DRM_ERROR("No UMS support in radeon module!\n"); + if (radeon_modeset == 0) return -EINVAL; - } DRM_INFO("radeon kernel modesetting enabled.\n"); radeon_register_atpx_handler(); @@ -691,3 +677,708 @@ module_exit(radeon_module_exit); MODULE_AUTHOR(DRIVER_AUTHOR); MODULE_DESCRIPTION(DRIVER_DESC); MODULE_LICENSE("GPL and additional rights"); + +#if defined(CONFIG_VGA_SWITCHEROO) +bool radeon_has_atpx(void); +#else +static inline bool radeon_has_atpx(void) { return false; } +#endif + +#include <drm/drm_drv.h> +#include "vga.h" + +#if NVGA > 0 +#include <dev/ic/mc6845reg.h> +#include <dev/ic/pcdisplayvar.h> +#include <dev/ic/vgareg.h> +#include <dev/ic/vgavar.h> + +extern int vga_console_attached; +#endif + +#ifdef __amd64__ +#include "efifb.h" +#include <machine/biosvar.h> +#endif + +#if NEFIFB > 0 +#include <machine/efifbvar.h> +#endif + +int radeondrm_probe(struct device *, void *, void *); +void radeondrm_attach_kms(struct device *, struct device *, void *); +int radeondrm_detach_kms(struct device *, int); +int radeondrm_activate_kms(struct device *, int); +void radeondrm_attachhook(struct device *); +int radeondrm_forcedetach(struct radeon_device *); + +bool radeon_msi_ok(struct radeon_device *); +irqreturn_t radeon_driver_irq_handler_kms(void *); + +/* + * set if the mountroot hook has a fatal error + * such as not being able to find the firmware on newer cards + */ +int radeon_fatal_error; + +const struct cfattach radeondrm_ca = { + sizeof (struct radeon_device), radeondrm_probe, radeondrm_attach_kms, + radeondrm_detach_kms, radeondrm_activate_kms +}; + +struct cfdriver radeondrm_cd = { + NULL, "radeondrm", DV_DULL +}; + +int +radeondrm_probe(struct device *parent, void *match, void *aux) +{ + if (radeon_fatal_error) + return 0; + if (drm_pciprobe(aux, pciidlist)) + return 20; + return 0; +} + +int +radeondrm_detach_kms(struct device *self, int flags) +{ + struct radeon_device *rdev = (struct radeon_device *)self; + + if (rdev == NULL) + return 0; + + pci_intr_disestablish(rdev->pc, rdev->irqh); + +#ifdef notyet + pm_runtime_get_sync(dev->dev); + + radeon_kfd_device_fini(rdev); +#endif + + radeon_acpi_fini(rdev); + + radeon_modeset_fini(rdev); + radeon_device_fini(rdev); + + if (rdev->ddev != NULL) { + config_detach(rdev->ddev->dev, flags); + rdev->ddev = NULL; + } + + return 0; +} + +void radeondrm_burner(void *, u_int, u_int); +int radeondrm_wsioctl(void *, u_long, caddr_t, int, struct proc *); +paddr_t radeondrm_wsmmap(void *, off_t, int); +int radeondrm_alloc_screen(void *, const struct wsscreen_descr *, + void **, int *, int *, uint32_t *); +void radeondrm_free_screen(void *, void *); +int radeondrm_show_screen(void *, void *, int, + void (*)(void *, int, int), void *); +void radeondrm_doswitch(void *); +void radeondrm_enter_ddb(void *, void *); +#ifdef __sparc64__ +void radeondrm_setcolor(void *, u_int, u_int8_t, u_int8_t, u_int8_t); +#endif +void radeondrm_setpal(struct radeon_device *, struct rasops_info *); + +struct wsscreen_descr radeondrm_stdscreen = { + "std", + 0, 0, + 0, + 0, 0, + WSSCREEN_UNDERLINE | WSSCREEN_HILIT | + WSSCREEN_REVERSE | WSSCREEN_WSCOLORS +}; + +const struct wsscreen_descr *radeondrm_scrlist[] = { + &radeondrm_stdscreen, +}; + +struct wsscreen_list radeondrm_screenlist = { + nitems(radeondrm_scrlist), radeondrm_scrlist +}; + +struct wsdisplay_accessops radeondrm_accessops = { + .ioctl = radeondrm_wsioctl, + .mmap = radeondrm_wsmmap, + .alloc_screen = radeondrm_alloc_screen, + .free_screen = radeondrm_free_screen, + .show_screen = radeondrm_show_screen, + .enter_ddb = radeondrm_enter_ddb, + .getchar = rasops_getchar, + .load_font = rasops_load_font, + .list_font = rasops_list_font, + .scrollback = rasops_scrollback, + .burn_screen = radeondrm_burner +}; + +int +radeondrm_wsioctl(void *v, u_long cmd, caddr_t data, int flag, struct proc *p) +{ + struct rasops_info *ri = v; + struct wsdisplay_fbinfo *wdf; + struct wsdisplay_param *dp = (struct wsdisplay_param *)data; + + switch (cmd) { + case WSDISPLAYIO_GTYPE: + *(u_int *)data = WSDISPLAY_TYPE_RADEONDRM; + return 0; + case WSDISPLAYIO_GINFO: + wdf = (struct wsdisplay_fbinfo *)data; + wdf->width = ri->ri_width; + wdf->height = ri->ri_height; + wdf->depth = ri->ri_depth; + wdf->stride = ri->ri_stride; + wdf->offset = 0; + wdf->cmsize = 0; + return 0; + case WSDISPLAYIO_GETPARAM: + if (ws_get_param == NULL) + return 0; + return ws_get_param(dp); + case WSDISPLAYIO_SETPARAM: + if (ws_set_param == NULL) + return 0; + return ws_set_param(dp); + default: + return -1; + } +} + +paddr_t +radeondrm_wsmmap(void *v, off_t off, int prot) +{ + return (-1); +} + +int +radeondrm_alloc_screen(void *v, const struct wsscreen_descr *type, + void **cookiep, int *curxp, int *curyp, uint32_t *attrp) +{ + return rasops_alloc_screen(v, cookiep, curxp, curyp, attrp); +} + +void +radeondrm_free_screen(void *v, void *cookie) +{ + return rasops_free_screen(v, cookie); +} + +int +radeondrm_show_screen(void *v, void *cookie, int waitok, + void (*cb)(void *, int, int), void *cbarg) +{ + struct rasops_info *ri = v; + struct radeon_device *rdev = ri->ri_hw; + + if (cookie == ri->ri_active) + return (0); + + rdev->switchcb = cb; + rdev->switchcbarg = cbarg; + rdev->switchcookie = cookie; + if (cb) { + task_add(systq, &rdev->switchtask); + return (EAGAIN); + } + + radeondrm_doswitch(v); + + return (0); +} + +void +radeondrm_doswitch(void *v) +{ + struct rasops_info *ri = v; + struct radeon_device *rdev = ri->ri_hw; + + rasops_show_screen(ri, rdev->switchcookie, 0, NULL, NULL); +#ifdef __sparc64__ + fbwscons_setcolormap(&rdev->sf, radeondrm_setcolor); +#else + radeondrm_setpal(rdev, ri); +#endif + drm_fb_helper_restore_fbdev_mode_unlocked((void *)rdev->mode_info.rfbdev); + + if (rdev->switchcb) + (rdev->switchcb)(rdev->switchcbarg, 0, 0); +} + +void +radeondrm_enter_ddb(void *v, void *cookie) +{ + struct rasops_info *ri = v; + struct radeon_device *rdev = ri->ri_hw; + struct drm_fb_helper *fb_helper = (void *)rdev->mode_info.rfbdev; + + if (cookie == ri->ri_active) + return; + + rasops_show_screen(ri, cookie, 0, NULL, NULL); + drm_fb_helper_debug_enter(fb_helper->fbdev); +} + +#ifdef __sparc64__ +void +radeondrm_setcolor(void *v, u_int index, u_int8_t r, u_int8_t g, u_int8_t b) +{ + struct sunfb *sf = v; + struct radeon_device *rdev = sf->sf_ro.ri_hw; + + /* see legacy_crtc_load_lut() */ + if (rdev->family < CHIP_RS600) { + WREG8(RADEON_PALETTE_INDEX, index); + WREG32(RADEON_PALETTE_30_DATA, + (r << 22) | (g << 12) | (b << 2)); + } else { + printf("%s: setcolor family %d not handled\n", + rdev->self.dv_xname, rdev->family); + } +} +#endif + +void +radeondrm_setpal(struct radeon_device *rdev, struct rasops_info *ri) +{ + struct drm_device *dev = rdev->ddev; + struct drm_crtc *crtc; + uint16_t *r_base, *g_base, *b_base; + int i, index, ret = 0; + const u_char *p; + + if (ri->ri_depth != 8) + return; + + for (i = 0; i < rdev->num_crtc; i++) { + struct drm_modeset_acquire_ctx ctx; + crtc = &rdev->mode_info.crtcs[i]->base; + + r_base = crtc->gamma_store; + g_base = r_base + crtc->gamma_size; + b_base = g_base + crtc->gamma_size; + + DRM_MODESET_LOCK_ALL_BEGIN(dev, ctx, 0, ret); + + p = rasops_cmap; + for (index = 0; index < 256; index++) { + r_base[index] = *p++ << 8; + g_base[index] = *p++ << 8; + b_base[index] = *p++ << 8; + } + + crtc->funcs->gamma_set(crtc, NULL, NULL, NULL, 0, NULL); + + DRM_MODESET_LOCK_ALL_END(dev, ctx, ret); + } +} + +void +radeondrm_attach_kms(struct device *parent, struct device *self, void *aux) +{ + struct radeon_device *rdev = (struct radeon_device *)self; + struct drm_device *dev; + struct pci_attach_args *pa = aux; + const struct pci_device_id *id_entry; + int is_agp; + pcireg_t type; + int i; + uint8_t rmmio_bar; + paddr_t fb_aper; + pcireg_t addr, mask; + int s; + +#if defined(__sparc64__) || defined(__macppc__) + extern int fbnode; +#endif + + id_entry = drm_find_description(PCI_VENDOR(pa->pa_id), + PCI_PRODUCT(pa->pa_id), pciidlist); + rdev->flags = id_entry->driver_data; + rdev->family = rdev->flags & RADEON_FAMILY_MASK; + rdev->pc = pa->pa_pc; + rdev->pa_tag = pa->pa_tag; + rdev->iot = pa->pa_iot; + rdev->memt = pa->pa_memt; + rdev->dmat = pa->pa_dmat; + +#if defined(__sparc64__) || defined(__macppc__) + if (fbnode == PCITAG_NODE(rdev->pa_tag)) + rdev->console = rdev->primary = 1; +#else + if (PCI_CLASS(pa->pa_class) == PCI_CLASS_DISPLAY && + PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_DISPLAY_VGA && + (pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG) + & (PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE)) + == (PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE)) { + rdev->primary = 1; +#if NVGA > 0 + rdev->console = vga_is_console(pa->pa_iot, -1); + vga_console_attached = 1; +#endif + } + +#if NEFIFB > 0 + if (efifb_is_primary(pa)) { + rdev->primary = 1; + rdev->console = efifb_is_console(pa); + efifb_detach(); + } +#endif +#endif + +#define RADEON_PCI_MEM 0x10 + + type = pci_mapreg_type(pa->pa_pc, pa->pa_tag, RADEON_PCI_MEM); + if (PCI_MAPREG_TYPE(type) != PCI_MAPREG_TYPE_MEM || + pci_mapreg_info(pa->pa_pc, pa->pa_tag, RADEON_PCI_MEM, + type, &rdev->fb_aper_offset, &rdev->fb_aper_size, NULL)) { + printf(": can't get frambuffer info\n"); + return; + } + if (rdev->fb_aper_offset == 0) { + bus_size_t start, end; + bus_addr_t base; + + KASSERT(pa->pa_memex != NULL); + + start = max(PCI_MEM_START, pa->pa_memex->ex_start); + end = min(PCI_MEM_END, pa->pa_memex->ex_end); + if (extent_alloc_subregion(pa->pa_memex, start, end, + rdev->fb_aper_size, rdev->fb_aper_size, 0, 0, 0, &base)) { + printf(": can't reserve framebuffer space\n"); + return; + } + pci_conf_write(pa->pa_pc, pa->pa_tag, RADEON_PCI_MEM, base); + if (PCI_MAPREG_MEM_TYPE(type) == PCI_MAPREG_MEM_TYPE_64BIT) + pci_conf_write(pa->pa_pc, pa->pa_tag, + RADEON_PCI_MEM + 4, (uint64_t)base >> 32); + rdev->fb_aper_offset = base; + } + + for (i = PCI_MAPREG_START; i < PCI_MAPREG_END; i += 4) { + type = pci_mapreg_type(pa->pa_pc, pa->pa_tag, i); + if (type == PCI_MAPREG_TYPE_IO) { + pci_mapreg_map(pa, i, type, 0, NULL, + &rdev->rio_mem, NULL, &rdev->rio_mem_size, 0); + break; + } + if (type == PCI_MAPREG_MEM_TYPE_64BIT) + i += 4; + } + + if (rdev->family >= CHIP_BONAIRE) { + type = pci_mapreg_type(pa->pa_pc, pa->pa_tag, 0x18); + if (PCI_MAPREG_TYPE(type) != PCI_MAPREG_TYPE_MEM || + pci_mapreg_map(pa, 0x18, type, BUS_SPACE_MAP_LINEAR, NULL, + &rdev->doorbell.bsh, &rdev->doorbell.base, + &rdev->doorbell.size, 0)) { + printf(": can't map doorbell space\n"); + return; + } + rdev->doorbell.ptr = bus_space_vaddr(rdev->memt, + rdev->doorbell.bsh); + } + + if (rdev->family >= CHIP_BONAIRE) + rmmio_bar = 0x24; + else + rmmio_bar = 0x18; + + type = pci_mapreg_type(pa->pa_pc, pa->pa_tag, rmmio_bar); + if (PCI_MAPREG_TYPE(type) != PCI_MAPREG_TYPE_MEM || + pci_mapreg_map(pa, rmmio_bar, type, BUS_SPACE_MAP_LINEAR, NULL, + &rdev->rmmio_bsh, &rdev->rmmio_base, &rdev->rmmio_size, 0)) { + printf(": can't map rmmio space\n"); + return; + } + rdev->rmmio = bus_space_vaddr(rdev->memt, rdev->rmmio_bsh); + + /* + * Make sure we have a base address for the ROM such that we + * can map it later. + */ + s = splhigh(); + addr = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_ROM_REG); + pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_ROM_REG, ~PCI_ROM_ENABLE); + mask = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_ROM_REG); + pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_ROM_REG, addr); + splx(s); + + if (addr == 0 && PCI_ROM_SIZE(mask) != 0 && pa->pa_memex) { + bus_size_t size, start, end; + bus_addr_t base; + + size = PCI_ROM_SIZE(mask); + start = max(PCI_MEM_START, pa->pa_memex->ex_start); + end = min(PCI_MEM_END, pa->pa_memex->ex_end); + if (extent_alloc_subregion(pa->pa_memex, start, end, size, + size, 0, 0, 0, &base) == 0) + pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_ROM_REG, base); + } + + /* update BUS flag */ + if (pci_get_capability(pa->pa_pc, pa->pa_tag, PCI_CAP_AGP, NULL, NULL)) { + rdev->flags |= RADEON_IS_AGP; + } else if (pci_get_capability(pa->pa_pc, pa->pa_tag, + PCI_CAP_PCIEXPRESS, NULL, NULL)) { + rdev->flags |= RADEON_IS_PCIE; + } else { + rdev->flags |= RADEON_IS_PCI; + } + + if ((radeon_runtime_pm != 0) && + radeon_has_atpx() && + ((rdev->flags & RADEON_IS_IGP) == 0)) + rdev->flags |= RADEON_IS_PX; + + DRM_DEBUG("%s card detected\n", + ((rdev->flags & RADEON_IS_AGP) ? "AGP" : + (((rdev->flags & RADEON_IS_PCIE) ? "PCIE" : "PCI")))); + + is_agp = pci_get_capability(pa->pa_pc, pa->pa_tag, PCI_CAP_AGP, + NULL, NULL); + + printf("\n"); + + dev = drm_attach_pci(&kms_driver, pa, is_agp, rdev->primary, + self, NULL); + if (dev == NULL) { + printf("%s: drm attach failed\n", rdev->self.dv_xname); + return; + } + rdev->ddev = dev; + rdev->pdev = dev->pdev; + + if (!radeon_msi_ok(rdev)) + pa->pa_flags &= ~PCI_FLAGS_MSI_ENABLED; + + rdev->msi_enabled = 0; + if (pci_intr_map_msi(pa, &rdev->intrh) == 0) + rdev->msi_enabled = 1; + else if (pci_intr_map(pa, &rdev->intrh) != 0) { + printf("%s: couldn't map interrupt\n", rdev->self.dv_xname); + return; + } + printf("%s: %s\n", rdev->self.dv_xname, + pci_intr_string(pa->pa_pc, rdev->intrh)); + + rdev->irqh = pci_intr_establish(pa->pa_pc, rdev->intrh, IPL_TTY, + radeon_driver_irq_handler_kms, rdev->ddev, rdev->self.dv_xname); + if (rdev->irqh == NULL) { + printf("%s: couldn't establish interrupt\n", + rdev->self.dv_xname); + return; + } + rdev->pdev->irq = -1; + +#ifdef __sparc64__ +{ + struct rasops_info *ri; + int node, console; + + node = PCITAG_NODE(pa->pa_tag); + console = (fbnode == node); + + fb_setsize(&rdev->sf, 8, 1152, 900, node, 0); + + /* + * The firmware sets up the framebuffer such that it starts at + * an offset from the start of video memory. + */ + rdev->fb_offset = + bus_space_read_4(rdev->memt, rdev->rmmio_bsh, RADEON_CRTC_OFFSET); + if (bus_space_map(rdev->memt, rdev->fb_aper_offset + rdev->fb_offset, + rdev->sf.sf_fbsize, BUS_SPACE_MAP_LINEAR, &rdev->memh)) { + printf("%s: can't map video memory\n", rdev->self.dv_xname); + return; + } + + ri = &rdev->sf.sf_ro; + ri->ri_bits = bus_space_vaddr(rdev->memt, rdev->memh); + ri->ri_hw = rdev; + ri->ri_updatecursor = NULL; + + fbwscons_init(&rdev->sf, RI_VCONS | RI_WRONLY | RI_BSWAP, console); + if (console) + fbwscons_console_init(&rdev->sf, -1); +} +#endif + + fb_aper = bus_space_mmap(rdev->memt, rdev->fb_aper_offset, 0, 0, 0); + if (fb_aper != -1) + rasops_claim_framebuffer(fb_aper, rdev->fb_aper_size, self); + + rdev->shutdown = true; + config_mountroot(self, radeondrm_attachhook); +} + +int +radeondrm_forcedetach(struct radeon_device *rdev) +{ + struct pci_softc *sc = (struct pci_softc *)rdev->self.dv_parent; + pcitag_t tag = rdev->pa_tag; + +#if NVGA > 0 + if (rdev->primary) + vga_console_attached = 0; +#endif + + /* reprobe pci device for non efi systems */ +#if NEFIFB > 0 + if (bios_efiinfo == NULL && !efifb_cb_found()) { +#endif + config_detach(&rdev->self, 0); + return pci_probe_device(sc, tag, NULL, NULL); +#if NEFIFB > 0 + } else if (rdev->primary) { + efifb_reattach(); + } +#endif + + return 0; +} + +void +radeondrm_attachhook(struct device *self) +{ + struct radeon_device *rdev = (struct radeon_device *)self; + struct drm_device *dev = rdev->ddev; + int r, acpi_status; + + /* radeon_device_init should report only fatal error + * like memory allocation failure or iomapping failure, + * or memory manager initialization failure, it must + * properly initialize the GPU MC controller and permit + * VRAM allocation + */ + r = radeon_device_init(rdev, rdev->ddev, rdev->ddev->pdev, rdev->flags); + if (r) { + dev_err(&dev->pdev->dev, "Fatal error during GPU init\n"); + radeon_fatal_error = 1; + radeondrm_forcedetach(rdev); + return; + } + + /* Again modeset_init should fail only on fatal error + * otherwise it should provide enough functionalities + * for shadowfb to run + */ + r = radeon_modeset_init(rdev); + if (r) + dev_err(&dev->pdev->dev, "Fatal error during modeset init\n"); + + /* Call ACPI methods: require modeset init + * but failure is not fatal + */ + if (!r) { + acpi_status = radeon_acpi_init(rdev); + if (acpi_status) + DRM_DEBUG("Error during ACPI methods call\n"); + } + +#ifdef notyet + radeon_kfd_device_probe(rdev); + radeon_kfd_device_init(rdev); +#endif + + if (radeon_is_px(rdev->ddev)) { + pm_runtime_use_autosuspend(dev->dev); + pm_runtime_set_autosuspend_delay(dev->dev, 5000); + pm_runtime_set_active(dev->dev); + pm_runtime_allow(dev->dev); + pm_runtime_mark_last_busy(dev->dev); + pm_runtime_put_autosuspend(dev->dev); + } + +{ + struct wsemuldisplaydev_attach_args aa; + struct rasops_info *ri = &rdev->ro; + + task_set(&rdev->switchtask, radeondrm_doswitch, ri); + + if (ri->ri_bits == NULL) + return; + +#ifdef __sparc64__ + fbwscons_setcolormap(&rdev->sf, radeondrm_setcolor); + ri = &rdev->sf.sf_ro; +#else + radeondrm_setpal(rdev, ri); + ri->ri_flg = RI_CENTER | RI_VCONS | RI_WRONLY; + rasops_init(ri, 160, 160); + + ri->ri_hw = rdev; +#endif + + radeondrm_stdscreen.capabilities = ri->ri_caps; + radeondrm_stdscreen.nrows = ri->ri_rows; + radeondrm_stdscreen.ncols = ri->ri_cols; + radeondrm_stdscreen.textops = &ri->ri_ops; + radeondrm_stdscreen.fontwidth = ri->ri_font->fontwidth; + radeondrm_stdscreen.fontheight = ri->ri_font->fontheight; + + aa.console = rdev->console; + aa.primary = rdev->primary; + aa.scrdata = &radeondrm_screenlist; + aa.accessops = &radeondrm_accessops; + aa.accesscookie = ri; + aa.defaultscreens = 0; + + if (rdev->console) { + uint32_t defattr; + + ri->ri_ops.pack_attr(ri->ri_active, 0, 0, 0, &defattr); + wsdisplay_cnattach(&radeondrm_stdscreen, ri->ri_active, + ri->ri_ccol, ri->ri_crow, defattr); + } + + /* + * Now that we've taken over the console, disable decoding of + * VGA legacy addresses, and opt out of arbitration. + */ + radeon_vga_set_state(rdev, false); + pci_disable_legacy_vga(&rdev->self); + + printf("%s: %dx%d, %dbpp\n", rdev->self.dv_xname, + ri->ri_width, ri->ri_height, ri->ri_depth); + + config_found_sm(&rdev->self, &aa, wsemuldisplaydevprint, + wsemuldisplaydevsubmatch); + + /* + * in linux via radeon_pci_probe -> drm_get_pci_dev -> drm_dev_register + */ + drm_dev_register(rdev->ddev, rdev->flags); +} +} + +int +radeondrm_activate_kms(struct device *self, int act) +{ + struct radeon_device *rdev = (struct radeon_device *)self; + int rv = 0; + + if (rdev->ddev == NULL || radeon_fatal_error) + return (0); + + switch (act) { + case DVACT_QUIESCE: + rv = config_activate_children(self, act); + radeon_suspend_kms(rdev->ddev, true, true, false); + break; + case DVACT_SUSPEND: + break; + case DVACT_RESUME: + break; + case DVACT_WAKEUP: + radeon_resume_kms(rdev->ddev, true, true); + rv = config_activate_children(self, act); + break; + } + + return (rv); +} diff --git a/sys/dev/pci/drm/radeon/radeon_encoders.c b/sys/dev/pci/drm/radeon/radeon_encoders.c index 46549d5179e..fbc0a218231 100644 --- a/sys/dev/pci/drm/radeon/radeon_encoders.c +++ b/sys/dev/pci/drm/radeon/radeon_encoders.c @@ -30,6 +30,8 @@ #include <drm/drm_device.h> #include <drm/radeon_drm.h> +#include <acpi/video.h> + #include "radeon.h" #include "radeon_atombios.h" #include "radeon_legacy_encoders.h" @@ -167,7 +169,7 @@ static void radeon_encoder_add_backlight(struct radeon_encoder *radeon_encoder, return; if (radeon_backlight == 0) { - return; + use_bl = false; } else if (radeon_backlight == 1) { use_bl = true; } else if (radeon_backlight == -1) { @@ -193,6 +195,13 @@ static void radeon_encoder_add_backlight(struct radeon_encoder *radeon_encoder, else radeon_legacy_backlight_init(radeon_encoder, connector); } + + /* + * If there is no native backlight device (which may happen even when + * use_bl==true) try registering an ACPI video backlight device instead. + */ + if (!rdev->mode_info.bl_encoder) + acpi_video_register_backlight(); } void @@ -244,16 +253,7 @@ radeon_get_connector_for_encoder(struct drm_encoder *encoder) list_for_each_entry(connector, &dev->mode_config.connector_list, head) { radeon_connector = to_radeon_connector(connector); - if (radeon_encoder->is_mst_encoder) { - struct radeon_encoder_mst *mst_enc; - - if (!radeon_connector->is_mst_connector) - continue; - - mst_enc = radeon_encoder->enc_priv; - if (mst_enc->connector == radeon_connector->mst_port) - return connector; - } else if (radeon_encoder->active_device & radeon_connector->devices) + if (radeon_encoder->active_device & radeon_connector->devices) return connector; } return NULL; @@ -399,9 +399,6 @@ bool radeon_dig_monitor_is_duallink(struct drm_encoder *encoder, case DRM_MODE_CONNECTOR_DVID: case DRM_MODE_CONNECTOR_HDMIA: case DRM_MODE_CONNECTOR_DisplayPort: - if (radeon_connector->is_mst_connector) - return false; - dig_connector = radeon_connector->con_priv; if ((dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) || (dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_eDP)) diff --git a/sys/dev/pci/drm/radeon/radeon_fb.c b/sys/dev/pci/drm/radeon/radeon_fb.c index 84ecdea9ca8..7be71b281f8 100644 --- a/sys/dev/pci/drm/radeon/radeon_fb.c +++ b/sys/dev/pci/drm/radeon/radeon_fb.c @@ -34,6 +34,7 @@ #include <drm/drm_crtc_helper.h> #include <drm/drm_fb_helper.h> #include <drm/drm_fourcc.h> +#include <drm/drm_framebuffer.h> #include <drm/radeon_drm.h> #include "radeon.h" diff --git a/sys/dev/pci/drm/radeon/radeon_fence.c b/sys/dev/pci/drm/radeon/radeon_fence.c index 77158033568..70ccf92c86c 100644 --- a/sys/dev/pci/drm/radeon/radeon_fence.c +++ b/sys/dev/pci/drm/radeon/radeon_fence.c @@ -176,18 +176,11 @@ static int radeon_fence_check_signaled(wait_queue_entry_t *wait, unsigned mode, */ seq = atomic64_read(&fence->rdev->fence_drv[fence->ring].last_seq); if (seq >= fence->seq) { - int ret = dma_fence_signal_locked(&fence->base); - - if (!ret) - DMA_FENCE_TRACE(&fence->base, "signaled from irq context\n"); - else - DMA_FENCE_TRACE(&fence->base, "was already signaled\n"); - + dma_fence_signal_locked(&fence->base); radeon_irq_kms_sw_irq_put(fence->rdev, fence->ring); __remove_wait_queue(&fence->rdev->fence_queue, &fence->fence_wake); dma_fence_put(&fence->base); - } else - DMA_FENCE_TRACE(&fence->base, "pending\n"); + } return 0; } @@ -422,8 +415,6 @@ static bool radeon_fence_enable_signaling(struct dma_fence *f) fence->fence_wake.func = radeon_fence_check_signaled; __add_wait_queue(&rdev->fence_queue, &fence->fence_wake); dma_fence_get(f); - - DMA_FENCE_TRACE(&fence->base, "armed on ring %i!\n", fence->ring); return true; } @@ -441,11 +432,7 @@ bool radeon_fence_signaled(struct radeon_fence *fence) return true; if (radeon_fence_seq_signaled(fence->rdev, fence->seq, fence->ring)) { - int ret; - - ret = dma_fence_signal(&fence->base); - if (!ret) - DMA_FENCE_TRACE(&fence->base, "signaled from radeon_fence_signaled\n"); + dma_fence_signal(&fence->base); return true; } return false; @@ -550,7 +537,6 @@ long radeon_fence_wait_timeout(struct radeon_fence *fence, bool intr, long timeo { uint64_t seq[RADEON_NUM_RINGS] = {}; long r; - int r_sig; /* * This function should not be called on !radeon fences. @@ -567,9 +553,7 @@ long radeon_fence_wait_timeout(struct radeon_fence *fence, bool intr, long timeo return r; } - r_sig = dma_fence_signal(&fence->base); - if (!r_sig) - DMA_FENCE_TRACE(&fence->base, "signaled from fence_wait\n"); + dma_fence_signal(&fence->base); return r; } diff --git a/sys/dev/pci/drm/radeon/radeon_gem.c b/sys/dev/pci/drm/radeon/radeon_gem.c index 264e7bff803..2b87603671d 100644 --- a/sys/dev/pci/drm/radeon/radeon_gem.c +++ b/sys/dev/pci/drm/radeon/radeon_gem.c @@ -26,6 +26,7 @@ * Jerome Glisse */ +#include <linux/iosys-map.h> #include <linux/pci.h> #include <drm/drm_device.h> @@ -236,7 +237,9 @@ static int radeon_gem_set_domain(struct drm_gem_object *gobj, } if (domain == RADEON_GEM_DOMAIN_CPU) { /* Asking for cpu access wait for object idle */ - r = dma_resv_wait_timeout(robj->tbo.base.resv, true, true, 30 * HZ); + r = dma_resv_wait_timeout(robj->tbo.base.resv, + DMA_RESV_USAGE_BOOKKEEP, + true, 30 * HZ); if (!r) r = -EBUSY; @@ -616,7 +619,7 @@ int radeon_gem_busy_ioctl(struct drm_device *dev, void *data, } robj = gem_to_radeon_bo(gobj); - r = dma_resv_test_signaled(robj->tbo.base.resv, true); + r = dma_resv_test_signaled(robj->tbo.base.resv, DMA_RESV_USAGE_READ); if (r == 0) r = -EBUSY; else @@ -645,7 +648,8 @@ int radeon_gem_wait_idle_ioctl(struct drm_device *dev, void *data, } robj = gem_to_radeon_bo(gobj); - ret = dma_resv_wait_timeout(robj->tbo.base.resv, true, true, 30 * HZ); + ret = dma_resv_wait_timeout(robj->tbo.base.resv, DMA_RESV_USAGE_READ, + true, 30 * HZ); if (ret == 0) r = -EBUSY; else if (ret < 0) @@ -782,7 +786,7 @@ int radeon_gem_va_ioctl(struct drm_device *dev, void *data, } /* !! DONT REMOVE !! - * We don't support vm_id yet, to be sure we don't have have broken + * We don't support vm_id yet, to be sure we don't have broken * userspace, reject anyone trying to use non 0 value thus moving * forward we can use those fields without breaking existant userspace */ @@ -922,7 +926,7 @@ int radeon_mode_dumb_create(struct drm_file *file_priv, args->pitch = radeon_align_pitch(rdev, args->width, DIV_ROUND_UP(args->bpp, 8), 0); - args->size = args->pitch * args->height; + args->size = (u64)args->pitch * args->height; args->size = roundup2(args->size, PAGE_SIZE); r = radeon_gem_object_create(rdev, args->size, 0, diff --git a/sys/dev/pci/drm/radeon/radeon_irq_kms.c b/sys/dev/pci/drm/radeon/radeon_irq_kms.c index 05a2facc65e..8121903fa95 100644 --- a/sys/dev/pci/drm/radeon/radeon_irq_kms.c +++ b/sys/dev/pci/drm/radeon/radeon_irq_kms.c @@ -103,16 +103,8 @@ static void radeon_hotplug_work_func(struct work_struct *work) static void radeon_dp_work_func(struct work_struct *work) { - struct radeon_device *rdev = container_of(work, struct radeon_device, - dp_work); - struct drm_device *dev = rdev->ddev; - struct drm_mode_config *mode_config = &dev->mode_config; - struct drm_connector *connector; - - /* this should take a mutex */ - list_for_each_entry(connector, &mode_config->connector_list, head) - radeon_connector_hotplug(connector); } + /** * radeon_driver_irq_preinstall_kms - drm irq preinstall callback * diff --git a/sys/dev/pci/drm/radeon/radeon_kms.c b/sys/dev/pci/drm/radeon/radeon_kms.c index 10dca3c6acf..9dad9417aa5 100644 --- a/sys/dev/pci/drm/radeon/radeon_kms.c +++ b/sys/dev/pci/drm/radeon/radeon_kms.c @@ -36,7 +36,6 @@ #include <drm/drm_file.h> #include <drm/drm_ioctl.h> #include <drm/radeon_drm.h> -#include <drm/drm_drv.h> #include "radeon.h" #include "radeon_asic.h" @@ -49,64 +48,6 @@ bool radeon_has_atpx(void); static inline bool radeon_has_atpx(void) { return false; } #endif -#include "vga.h" - -#if NVGA > 0 -#include <dev/ic/mc6845reg.h> -#include <dev/ic/pcdisplayvar.h> -#include <dev/ic/vgareg.h> -#include <dev/ic/vgavar.h> - -extern int vga_console_attached; -#endif - -#ifdef __amd64__ -#include "efifb.h" -#include <machine/biosvar.h> -#endif - -#if NEFIFB > 0 -#include <machine/efifbvar.h> -#endif - -int radeondrm_probe(struct device *, void *, void *); -void radeondrm_attach_kms(struct device *, struct device *, void *); -int radeondrm_detach_kms(struct device *, int); -int radeondrm_activate_kms(struct device *, int); -void radeondrm_attachhook(struct device *); -int radeondrm_forcedetach(struct radeon_device *); - -bool radeon_msi_ok(struct radeon_device *); -irqreturn_t radeon_driver_irq_handler_kms(void *); - -extern const struct pci_device_id radeondrm_pciidlist[]; -extern const struct drm_driver kms_driver; - -/* - * set if the mountroot hook has a fatal error - * such as not being able to find the firmware on newer cards - */ -int radeon_fatal_error; - -const struct cfattach radeondrm_ca = { - sizeof (struct radeon_device), radeondrm_probe, radeondrm_attach_kms, - radeondrm_detach_kms, radeondrm_activate_kms -}; - -struct cfdriver radeondrm_cd = { - NULL, "radeondrm", DV_DULL -}; - -int -radeondrm_probe(struct device *parent, void *match, void *aux) -{ - if (radeon_fatal_error) - return 0; - if (drm_pciprobe(aux, radeondrm_pciidlist)) - return 20; - return 0; -} - /** * radeon_driver_unload_kms - Main unload function for KMS. * @@ -119,19 +60,20 @@ radeondrm_probe(struct device *parent, void *match, void *aux) * Returns 0 on success. */ #ifdef __linux__ -int radeon_driver_unload_kms(struct drm_device *dev) +void radeon_driver_unload_kms(struct drm_device *dev) { struct radeon_device *rdev = dev->dev_private; if (rdev == NULL) - return 0; + return; if (rdev->rmmio == NULL) goto done_free; - pm_runtime_get_sync(dev->dev); - - radeon_kfd_device_fini(rdev); + if (radeon_is_px(dev)) { + pm_runtime_get_sync(dev->dev); + pm_runtime_forbid(dev->dev); + } radeon_acpi_fini(rdev); @@ -146,247 +88,8 @@ int radeon_driver_unload_kms(struct drm_device *dev) done_free: kfree(rdev); dev->dev_private = NULL; - return 0; -} -#else -int -radeondrm_detach_kms(struct device *self, int flags) -{ - struct radeon_device *rdev = (struct radeon_device *)self; - - if (rdev == NULL) - return 0; - - pci_intr_disestablish(rdev->pc, rdev->irqh); - -#ifdef notyet - pm_runtime_get_sync(dev->dev); - - radeon_kfd_device_fini(rdev); -#endif - - radeon_acpi_fini(rdev); - - radeon_modeset_fini(rdev); - radeon_device_fini(rdev); - - if (rdev->ddev != NULL) { - config_detach(rdev->ddev->dev, flags); - rdev->ddev = NULL; - } - - return 0; -} -#endif - -void radeondrm_burner(void *, u_int, u_int); -int radeondrm_wsioctl(void *, u_long, caddr_t, int, struct proc *); -paddr_t radeondrm_wsmmap(void *, off_t, int); -int radeondrm_alloc_screen(void *, const struct wsscreen_descr *, - void **, int *, int *, uint32_t *); -void radeondrm_free_screen(void *, void *); -int radeondrm_show_screen(void *, void *, int, - void (*)(void *, int, int), void *); -void radeondrm_doswitch(void *); -void radeondrm_enter_ddb(void *, void *); -#ifdef __sparc64__ -void radeondrm_setcolor(void *, u_int, u_int8_t, u_int8_t, u_int8_t); -#endif -void radeondrm_setpal(struct radeon_device *, struct rasops_info *); - -struct wsscreen_descr radeondrm_stdscreen = { - "std", - 0, 0, - 0, - 0, 0, - WSSCREEN_UNDERLINE | WSSCREEN_HILIT | - WSSCREEN_REVERSE | WSSCREEN_WSCOLORS -}; - -const struct wsscreen_descr *radeondrm_scrlist[] = { - &radeondrm_stdscreen, -}; - -struct wsscreen_list radeondrm_screenlist = { - nitems(radeondrm_scrlist), radeondrm_scrlist -}; - -struct wsdisplay_accessops radeondrm_accessops = { - .ioctl = radeondrm_wsioctl, - .mmap = radeondrm_wsmmap, - .alloc_screen = radeondrm_alloc_screen, - .free_screen = radeondrm_free_screen, - .show_screen = radeondrm_show_screen, - .enter_ddb = radeondrm_enter_ddb, - .getchar = rasops_getchar, - .load_font = rasops_load_font, - .list_font = rasops_list_font, - .scrollback = rasops_scrollback, - .burn_screen = radeondrm_burner -}; - -int -radeondrm_wsioctl(void *v, u_long cmd, caddr_t data, int flag, struct proc *p) -{ - struct rasops_info *ri = v; - struct wsdisplay_fbinfo *wdf; - struct wsdisplay_param *dp = (struct wsdisplay_param *)data; - - switch (cmd) { - case WSDISPLAYIO_GTYPE: - *(u_int *)data = WSDISPLAY_TYPE_RADEONDRM; - return 0; - case WSDISPLAYIO_GINFO: - wdf = (struct wsdisplay_fbinfo *)data; - wdf->width = ri->ri_width; - wdf->height = ri->ri_height; - wdf->depth = ri->ri_depth; - wdf->stride = ri->ri_stride; - wdf->offset = 0; - wdf->cmsize = 0; - return 0; - case WSDISPLAYIO_GETPARAM: - if (ws_get_param == NULL) - return 0; - return ws_get_param(dp); - case WSDISPLAYIO_SETPARAM: - if (ws_set_param == NULL) - return 0; - return ws_set_param(dp); - default: - return -1; - } -} - -paddr_t -radeondrm_wsmmap(void *v, off_t off, int prot) -{ - return (-1); -} - -int -radeondrm_alloc_screen(void *v, const struct wsscreen_descr *type, - void **cookiep, int *curxp, int *curyp, uint32_t *attrp) -{ - return rasops_alloc_screen(v, cookiep, curxp, curyp, attrp); -} - -void -radeondrm_free_screen(void *v, void *cookie) -{ - return rasops_free_screen(v, cookie); -} - -int -radeondrm_show_screen(void *v, void *cookie, int waitok, - void (*cb)(void *, int, int), void *cbarg) -{ - struct rasops_info *ri = v; - struct radeon_device *rdev = ri->ri_hw; - - if (cookie == ri->ri_active) - return (0); - - rdev->switchcb = cb; - rdev->switchcbarg = cbarg; - rdev->switchcookie = cookie; - if (cb) { - task_add(systq, &rdev->switchtask); - return (EAGAIN); - } - - radeondrm_doswitch(v); - - return (0); -} - -void -radeondrm_doswitch(void *v) -{ - struct rasops_info *ri = v; - struct radeon_device *rdev = ri->ri_hw; - - rasops_show_screen(ri, rdev->switchcookie, 0, NULL, NULL); -#ifdef __sparc64__ - fbwscons_setcolormap(&rdev->sf, radeondrm_setcolor); -#else - radeondrm_setpal(rdev, ri); -#endif - drm_fb_helper_restore_fbdev_mode_unlocked((void *)rdev->mode_info.rfbdev); - - if (rdev->switchcb) - (rdev->switchcb)(rdev->switchcbarg, 0, 0); } -void -radeondrm_enter_ddb(void *v, void *cookie) -{ - struct rasops_info *ri = v; - struct radeon_device *rdev = ri->ri_hw; - struct drm_fb_helper *fb_helper = (void *)rdev->mode_info.rfbdev; - - if (cookie == ri->ri_active) - return; - - rasops_show_screen(ri, cookie, 0, NULL, NULL); - drm_fb_helper_debug_enter(fb_helper->fbdev); -} - -#ifdef __sparc64__ -void -radeondrm_setcolor(void *v, u_int index, u_int8_t r, u_int8_t g, u_int8_t b) -{ - struct sunfb *sf = v; - struct radeon_device *rdev = sf->sf_ro.ri_hw; - - /* see legacy_crtc_load_lut() */ - if (rdev->family < CHIP_RS600) { - WREG8(RADEON_PALETTE_INDEX, index); - WREG32(RADEON_PALETTE_30_DATA, - (r << 22) | (g << 12) | (b << 2)); - } else { - printf("%s: setcolor family %d not handled\n", - rdev->self.dv_xname, rdev->family); - } -} -#endif - -void -radeondrm_setpal(struct radeon_device *rdev, struct rasops_info *ri) -{ - struct drm_device *dev = rdev->ddev; - struct drm_crtc *crtc; - uint16_t *r_base, *g_base, *b_base; - int i, index, ret = 0; - const u_char *p; - - if (ri->ri_depth != 8) - return; - - for (i = 0; i < rdev->num_crtc; i++) { - struct drm_modeset_acquire_ctx ctx; - crtc = &rdev->mode_info.crtcs[i]->base; - - r_base = crtc->gamma_store; - g_base = r_base + crtc->gamma_size; - b_base = g_base + crtc->gamma_size; - - DRM_MODESET_LOCK_ALL_BEGIN(dev, ctx, 0, ret); - - p = rasops_cmap; - for (index = 0; index < 256; index++) { - r_base[index] = *p++ << 8; - g_base[index] = *p++ << 8; - b_base[index] = *p++ << 8; - } - - crtc->funcs->gamma_set(crtc, NULL, NULL, NULL, 0, NULL); - - DRM_MODESET_LOCK_ALL_END(dev, ctx, ret); - } -} - -#ifdef __linux__ /** * radeon_driver_load_kms - Main load function for KMS. * @@ -466,7 +169,7 @@ int radeon_driver_load_kms(struct drm_device *dev, unsigned long flags) if (!r) { acpi_status = radeon_acpi_init(rdev); if (acpi_status) - dev_dbg(dev->dev, "Error during ACPI methods call\n"); + dev_dbg(dev->dev, "Error during ACPI methods call\n"); } if (radeon_is_px(dev)) { @@ -488,414 +191,6 @@ out: } #endif -void -radeondrm_attach_kms(struct device *parent, struct device *self, void *aux) -{ - struct radeon_device *rdev = (struct radeon_device *)self; - struct drm_device *dev; - struct pci_attach_args *pa = aux; - const struct pci_device_id *id_entry; - int is_agp; - pcireg_t type; - int i; - uint8_t rmmio_bar; - paddr_t fb_aper; - pcireg_t addr, mask; - int s; - -#if defined(__sparc64__) || defined(__macppc__) - extern int fbnode; -#endif - - id_entry = drm_find_description(PCI_VENDOR(pa->pa_id), - PCI_PRODUCT(pa->pa_id), radeondrm_pciidlist); - rdev->flags = id_entry->driver_data; - rdev->family = rdev->flags & RADEON_FAMILY_MASK; - rdev->pc = pa->pa_pc; - rdev->pa_tag = pa->pa_tag; - rdev->iot = pa->pa_iot; - rdev->memt = pa->pa_memt; - rdev->dmat = pa->pa_dmat; - -#if defined(__sparc64__) || defined(__macppc__) - if (fbnode == PCITAG_NODE(rdev->pa_tag)) - rdev->console = rdev->primary = 1; -#else - if (PCI_CLASS(pa->pa_class) == PCI_CLASS_DISPLAY && - PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_DISPLAY_VGA && - (pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG) - & (PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE)) - == (PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE)) { - rdev->primary = 1; -#if NVGA > 0 - rdev->console = vga_is_console(pa->pa_iot, -1); - vga_console_attached = 1; -#endif - } - -#if NEFIFB > 0 - if (efifb_is_primary(pa)) { - rdev->primary = 1; - rdev->console = efifb_is_console(pa); - efifb_detach(); - } -#endif -#endif - -#define RADEON_PCI_MEM 0x10 - - type = pci_mapreg_type(pa->pa_pc, pa->pa_tag, RADEON_PCI_MEM); - if (PCI_MAPREG_TYPE(type) != PCI_MAPREG_TYPE_MEM || - pci_mapreg_info(pa->pa_pc, pa->pa_tag, RADEON_PCI_MEM, - type, &rdev->fb_aper_offset, &rdev->fb_aper_size, NULL)) { - printf(": can't get frambuffer info\n"); - return; - } - if (rdev->fb_aper_offset == 0) { - bus_size_t start, end; - bus_addr_t base; - - KASSERT(pa->pa_memex != NULL); - - start = max(PCI_MEM_START, pa->pa_memex->ex_start); - end = min(PCI_MEM_END, pa->pa_memex->ex_end); - if (extent_alloc_subregion(pa->pa_memex, start, end, - rdev->fb_aper_size, rdev->fb_aper_size, 0, 0, 0, &base)) { - printf(": can't reserve framebuffer space\n"); - return; - } - pci_conf_write(pa->pa_pc, pa->pa_tag, RADEON_PCI_MEM, base); - if (PCI_MAPREG_MEM_TYPE(type) == PCI_MAPREG_MEM_TYPE_64BIT) - pci_conf_write(pa->pa_pc, pa->pa_tag, - RADEON_PCI_MEM + 4, (uint64_t)base >> 32); - rdev->fb_aper_offset = base; - } - - for (i = PCI_MAPREG_START; i < PCI_MAPREG_END; i += 4) { - type = pci_mapreg_type(pa->pa_pc, pa->pa_tag, i); - if (type == PCI_MAPREG_TYPE_IO) { - pci_mapreg_map(pa, i, type, 0, NULL, - &rdev->rio_mem, NULL, &rdev->rio_mem_size, 0); - break; - } - if (type == PCI_MAPREG_MEM_TYPE_64BIT) - i += 4; - } - - if (rdev->family >= CHIP_BONAIRE) { - type = pci_mapreg_type(pa->pa_pc, pa->pa_tag, 0x18); - if (PCI_MAPREG_TYPE(type) != PCI_MAPREG_TYPE_MEM || - pci_mapreg_map(pa, 0x18, type, BUS_SPACE_MAP_LINEAR, NULL, - &rdev->doorbell.bsh, &rdev->doorbell.base, - &rdev->doorbell.size, 0)) { - printf(": can't map doorbell space\n"); - return; - } - rdev->doorbell.ptr = bus_space_vaddr(rdev->memt, - rdev->doorbell.bsh); - } - - if (rdev->family >= CHIP_BONAIRE) - rmmio_bar = 0x24; - else - rmmio_bar = 0x18; - - type = pci_mapreg_type(pa->pa_pc, pa->pa_tag, rmmio_bar); - if (PCI_MAPREG_TYPE(type) != PCI_MAPREG_TYPE_MEM || - pci_mapreg_map(pa, rmmio_bar, type, BUS_SPACE_MAP_LINEAR, NULL, - &rdev->rmmio_bsh, &rdev->rmmio_base, &rdev->rmmio_size, 0)) { - printf(": can't map rmmio space\n"); - return; - } - rdev->rmmio = bus_space_vaddr(rdev->memt, rdev->rmmio_bsh); - - /* - * Make sure we have a base address for the ROM such that we - * can map it later. - */ - s = splhigh(); - addr = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_ROM_REG); - pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_ROM_REG, ~PCI_ROM_ENABLE); - mask = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_ROM_REG); - pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_ROM_REG, addr); - splx(s); - - if (addr == 0 && PCI_ROM_SIZE(mask) != 0 && pa->pa_memex) { - bus_size_t size, start, end; - bus_addr_t base; - - size = PCI_ROM_SIZE(mask); - start = max(PCI_MEM_START, pa->pa_memex->ex_start); - end = min(PCI_MEM_END, pa->pa_memex->ex_end); - if (extent_alloc_subregion(pa->pa_memex, start, end, size, - size, 0, 0, 0, &base) == 0) - pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_ROM_REG, base); - } - - /* update BUS flag */ - if (pci_get_capability(pa->pa_pc, pa->pa_tag, PCI_CAP_AGP, NULL, NULL)) { - rdev->flags |= RADEON_IS_AGP; - } else if (pci_get_capability(pa->pa_pc, pa->pa_tag, - PCI_CAP_PCIEXPRESS, NULL, NULL)) { - rdev->flags |= RADEON_IS_PCIE; - } else { - rdev->flags |= RADEON_IS_PCI; - } - - if ((radeon_runtime_pm != 0) && - radeon_has_atpx() && - ((rdev->flags & RADEON_IS_IGP) == 0)) - rdev->flags |= RADEON_IS_PX; - - DRM_DEBUG("%s card detected\n", - ((rdev->flags & RADEON_IS_AGP) ? "AGP" : - (((rdev->flags & RADEON_IS_PCIE) ? "PCIE" : "PCI")))); - - is_agp = pci_get_capability(pa->pa_pc, pa->pa_tag, PCI_CAP_AGP, - NULL, NULL); - - printf("\n"); - - dev = drm_attach_pci(&kms_driver, pa, is_agp, rdev->primary, - self, NULL); - if (dev == NULL) { - printf("%s: drm attach failed\n", rdev->self.dv_xname); - return; - } - rdev->ddev = dev; - rdev->pdev = dev->pdev; - - if (!radeon_msi_ok(rdev)) - pa->pa_flags &= ~PCI_FLAGS_MSI_ENABLED; - - rdev->msi_enabled = 0; - if (pci_intr_map_msi(pa, &rdev->intrh) == 0) - rdev->msi_enabled = 1; - else if (pci_intr_map(pa, &rdev->intrh) != 0) { - printf("%s: couldn't map interrupt\n", rdev->self.dv_xname); - return; - } - printf("%s: %s\n", rdev->self.dv_xname, - pci_intr_string(pa->pa_pc, rdev->intrh)); - - rdev->irqh = pci_intr_establish(pa->pa_pc, rdev->intrh, IPL_TTY, - radeon_driver_irq_handler_kms, rdev->ddev, rdev->self.dv_xname); - if (rdev->irqh == NULL) { - printf("%s: couldn't establish interrupt\n", - rdev->self.dv_xname); - return; - } - rdev->pdev->irq = -1; - -#ifdef __sparc64__ -{ - struct rasops_info *ri; - int node, console; - - node = PCITAG_NODE(pa->pa_tag); - console = (fbnode == node); - - fb_setsize(&rdev->sf, 8, 1152, 900, node, 0); - - /* - * The firmware sets up the framebuffer such that it starts at - * an offset from the start of video memory. - */ - rdev->fb_offset = - bus_space_read_4(rdev->memt, rdev->rmmio_bsh, RADEON_CRTC_OFFSET); - if (bus_space_map(rdev->memt, rdev->fb_aper_offset + rdev->fb_offset, - rdev->sf.sf_fbsize, BUS_SPACE_MAP_LINEAR, &rdev->memh)) { - printf("%s: can't map video memory\n", rdev->self.dv_xname); - return; - } - - ri = &rdev->sf.sf_ro; - ri->ri_bits = bus_space_vaddr(rdev->memt, rdev->memh); - ri->ri_hw = rdev; - ri->ri_updatecursor = NULL; - - fbwscons_init(&rdev->sf, RI_VCONS | RI_WRONLY | RI_BSWAP, console); - if (console) - fbwscons_console_init(&rdev->sf, -1); -} -#endif - - fb_aper = bus_space_mmap(rdev->memt, rdev->fb_aper_offset, 0, 0, 0); - if (fb_aper != -1) - rasops_claim_framebuffer(fb_aper, rdev->fb_aper_size, self); - - rdev->shutdown = true; - config_mountroot(self, radeondrm_attachhook); -} - -int -radeondrm_forcedetach(struct radeon_device *rdev) -{ - struct pci_softc *sc = (struct pci_softc *)rdev->self.dv_parent; - pcitag_t tag = rdev->pa_tag; - -#if NVGA > 0 - if (rdev->primary) - vga_console_attached = 0; -#endif - - /* reprobe pci device for non efi systems */ -#if NEFIFB > 0 - if (bios_efiinfo == NULL && !efifb_cb_found()) { -#endif - config_detach(&rdev->self, 0); - return pci_probe_device(sc, tag, NULL, NULL); -#if NEFIFB > 0 - } else if (rdev->primary) { - efifb_reattach(); - } -#endif - - return 0; -} - -void -radeondrm_attachhook(struct device *self) -{ - struct radeon_device *rdev = (struct radeon_device *)self; - struct drm_device *dev = rdev->ddev; - int r, acpi_status; - - /* radeon_device_init should report only fatal error - * like memory allocation failure or iomapping failure, - * or memory manager initialization failure, it must - * properly initialize the GPU MC controller and permit - * VRAM allocation - */ - r = radeon_device_init(rdev, rdev->ddev, rdev->ddev->pdev, rdev->flags); - if (r) { - dev_err(&dev->pdev->dev, "Fatal error during GPU init\n"); - radeon_fatal_error = 1; - radeondrm_forcedetach(rdev); - return; - } - - /* Again modeset_init should fail only on fatal error - * otherwise it should provide enough functionalities - * for shadowfb to run - */ - r = radeon_modeset_init(rdev); - if (r) - dev_err(&dev->pdev->dev, "Fatal error during modeset init\n"); - - /* Call ACPI methods: require modeset init - * but failure is not fatal - */ - if (!r) { - acpi_status = radeon_acpi_init(rdev); - if (acpi_status) - DRM_DEBUG("Error during ACPI methods call\n"); - } - -#ifdef notyet - radeon_kfd_device_probe(rdev); - radeon_kfd_device_init(rdev); -#endif - - if (radeon_is_px(rdev->ddev)) { - pm_runtime_use_autosuspend(dev->dev); - pm_runtime_set_autosuspend_delay(dev->dev, 5000); - pm_runtime_set_active(dev->dev); - pm_runtime_allow(dev->dev); - pm_runtime_mark_last_busy(dev->dev); - pm_runtime_put_autosuspend(dev->dev); - } - -{ - struct wsemuldisplaydev_attach_args aa; - struct rasops_info *ri = &rdev->ro; - - task_set(&rdev->switchtask, radeondrm_doswitch, ri); - - if (ri->ri_bits == NULL) - return; - -#ifdef __sparc64__ - fbwscons_setcolormap(&rdev->sf, radeondrm_setcolor); - ri = &rdev->sf.sf_ro; -#else - radeondrm_setpal(rdev, ri); - ri->ri_flg = RI_CENTER | RI_VCONS | RI_WRONLY; - rasops_init(ri, 160, 160); - - ri->ri_hw = rdev; -#endif - - radeondrm_stdscreen.capabilities = ri->ri_caps; - radeondrm_stdscreen.nrows = ri->ri_rows; - radeondrm_stdscreen.ncols = ri->ri_cols; - radeondrm_stdscreen.textops = &ri->ri_ops; - radeondrm_stdscreen.fontwidth = ri->ri_font->fontwidth; - radeondrm_stdscreen.fontheight = ri->ri_font->fontheight; - - aa.console = rdev->console; - aa.primary = rdev->primary; - aa.scrdata = &radeondrm_screenlist; - aa.accessops = &radeondrm_accessops; - aa.accesscookie = ri; - aa.defaultscreens = 0; - - if (rdev->console) { - uint32_t defattr; - - ri->ri_ops.pack_attr(ri->ri_active, 0, 0, 0, &defattr); - wsdisplay_cnattach(&radeondrm_stdscreen, ri->ri_active, - ri->ri_ccol, ri->ri_crow, defattr); - } - - /* - * Now that we've taken over the console, disable decoding of - * VGA legacy addresses, and opt out of arbitration. - */ - radeon_vga_set_state(rdev, false); - pci_disable_legacy_vga(&rdev->self); - - printf("%s: %dx%d, %dbpp\n", rdev->self.dv_xname, - ri->ri_width, ri->ri_height, ri->ri_depth); - - config_found_sm(&rdev->self, &aa, wsemuldisplaydevprint, - wsemuldisplaydevsubmatch); - - /* - * in linux via radeon_pci_probe -> drm_get_pci_dev -> drm_dev_register - */ - drm_dev_register(rdev->ddev, rdev->flags); -} -} - -int -radeondrm_activate_kms(struct device *self, int act) -{ - struct radeon_device *rdev = (struct radeon_device *)self; - int rv = 0; - - if (rdev->ddev == NULL || radeon_fatal_error) - return (0); - - switch (act) { - case DVACT_QUIESCE: - rv = config_activate_children(self, act); - radeon_suspend_kms(rdev->ddev, true, true, false); - break; - case DVACT_SUSPEND: - break; - case DVACT_RESUME: - break; - case DVACT_WAKEUP: - radeon_resume_kms(rdev->ddev, true, true); - rv = config_activate_children(self, act); - break; - } - - return (rv); -} - - /** * radeon_set_filp_rights - Set filp right. * @@ -948,6 +243,7 @@ int radeon_info_ioctl(struct drm_device *dev, void *data, struct drm_file *filp) struct drm_radeon_info *info = data; struct radeon_mode_info *minfo = &rdev->mode_info; uint32_t *value, value_tmp, *value_ptr, value_size; + struct ttm_resource_manager *man; uint64_t value64; struct drm_crtc *crtc; int i, found; @@ -1261,12 +557,14 @@ int radeon_info_ioctl(struct drm_device *dev, void *data, struct drm_file *filp) case RADEON_INFO_VRAM_USAGE: value = (uint32_t*)&value64; value_size = sizeof(uint64_t); - value64 = atomic64_read(&rdev->vram_usage); + man = ttm_manager_type(&rdev->mman.bdev, TTM_PL_VRAM); + value64 = ttm_resource_manager_usage(man); break; case RADEON_INFO_GTT_USAGE: value = (uint32_t*)&value64; value_size = sizeof(uint64_t); - value64 = atomic64_read(&rdev->gtt_usage); + man = ttm_manager_type(&rdev->mman.bdev, TTM_PL_TT); + value64 = ttm_resource_manager_usage(man); break; case RADEON_INFO_ACTIVE_CU_COUNT: if (rdev->family >= CHIP_BONAIRE) @@ -1330,6 +628,9 @@ int radeon_info_ioctl(struct drm_device *dev, void *data, struct drm_file *filp) return 0; } +#ifdef __sparc64__ +void radeondrm_setcolor(void *, u_int, u_int8_t, u_int8_t, u_int8_t); +#endif /* * Outdated mess for old drm with Xorg being in charge (void function now). diff --git a/sys/dev/pci/drm/radeon/radeon_legacy_crtc.c b/sys/dev/pci/drm/radeon/radeon_legacy_crtc.c index 8817fd033cd..6072ed5f2dd 100644 --- a/sys/dev/pci/drm/radeon/radeon_legacy_crtc.c +++ b/sys/dev/pci/drm/radeon/radeon_legacy_crtc.c @@ -28,6 +28,7 @@ #include <drm/drm_fb_helper.h> #include <drm/drm_fixed.h> #include <drm/drm_fourcc.h> +#include <drm/drm_framebuffer.h> #include <drm/drm_vblank.h> #include <drm/radeon_drm.h> diff --git a/sys/dev/pci/drm/radeon/radeon_legacy_encoders.c b/sys/dev/pci/drm/radeon/radeon_legacy_encoders.c index 735a60b6c9e..ef2478b7329 100644 --- a/sys/dev/pci/drm/radeon/radeon_legacy_encoders.c +++ b/sys/dev/pci/drm/radeon/radeon_legacy_encoders.c @@ -33,6 +33,8 @@ #include <drm/drm_util.h> #include <drm/radeon_drm.h> +#include <acpi/video.h> + #include "radeon.h" #include "radeon_asic.h" #include "radeon_legacy_encoders.h" @@ -318,8 +320,6 @@ radeon_legacy_set_backlight_level(struct radeon_encoder *radeon_encoder, u8 leve radeon_legacy_lvds_update(&radeon_encoder->base, dpms_mode); } -#if defined(CONFIG_BACKLIGHT_CLASS_DEVICE) || defined(CONFIG_BACKLIGHT_CLASS_DEVICE_MODULE) - static uint8_t radeon_legacy_lvds_level(struct backlight_device *bd) { struct radeon_backlight_privdata *pdata = bl_get_data(bd); @@ -389,6 +389,11 @@ void radeon_legacy_backlight_init(struct radeon_encoder *radeon_encoder, return; #endif + if (!acpi_video_backlight_use_native()) { + drm_info(dev, "Skipping radeon legacy LVDS backlight registration\n"); + return; + } + pdata = kmalloc(sizeof(struct radeon_backlight_privdata), GFP_KERNEL); if (!pdata) { DRM_ERROR("Memory allocation failed\n"); @@ -488,19 +493,6 @@ static void radeon_legacy_backlight_exit(struct radeon_encoder *radeon_encoder) } } -#else /* !CONFIG_BACKLIGHT_CLASS_DEVICE */ - -void radeon_legacy_backlight_init(struct radeon_encoder *encoder) -{ -} - -static void radeon_legacy_backlight_exit(struct radeon_encoder *encoder) -{ -} - -#endif - - static void radeon_lvds_enc_destroy(struct drm_encoder *encoder) { struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); diff --git a/sys/dev/pci/drm/radeon/radeon_mn.c b/sys/dev/pci/drm/radeon/radeon_mn.c index 9fa88549c89..29fe8423bd9 100644 --- a/sys/dev/pci/drm/radeon/radeon_mn.c +++ b/sys/dev/pci/drm/radeon/radeon_mn.c @@ -66,8 +66,8 @@ static bool radeon_mn_invalidate(struct mmu_interval_notifier *mn, return true; } - r = dma_resv_wait_timeout(bo->tbo.base.resv, true, false, - MAX_SCHEDULE_TIMEOUT); + r = dma_resv_wait_timeout(bo->tbo.base.resv, DMA_RESV_USAGE_BOOKKEEP, + false, MAX_SCHEDULE_TIMEOUT); if (r <= 0) DRM_ERROR("(%ld) failed to wait for user bo\n", r); diff --git a/sys/dev/pci/drm/radeon/radeon_mode.h b/sys/dev/pci/drm/radeon/radeon_mode.h index 721413614ad..30ddf05659e 100644 --- a/sys/dev/pci/drm/radeon/radeon_mode.h +++ b/sys/dev/pci/drm/radeon/radeon_mode.h @@ -30,11 +30,10 @@ #ifndef RADEON_MODE_H #define RADEON_MODE_H +#include <drm/display/drm_dp_helper.h> #include <drm/drm_crtc.h> #include <drm/drm_edid.h> #include <drm/drm_encoder.h> -#include <drm/drm_dp_helper.h> -#include <drm/drm_dp_mst_helper.h> #include <drm/drm_fixed.h> #include <drm/drm_crtc_helper.h> #include <linux/i2c.h> @@ -281,15 +280,11 @@ struct radeon_mode_info { #define RADEON_MAX_BL_LEVEL 0xFF -#if defined(CONFIG_BACKLIGHT_CLASS_DEVICE) || defined(CONFIG_BACKLIGHT_CLASS_DEVICE_MODULE) - struct radeon_backlight_privdata { struct radeon_encoder *encoder; uint8_t negative; }; -#endif - #define MAX_H_CODE_TIMING_LEN 32 #define MAX_V_CODE_TIMING_LEN 32 @@ -440,24 +435,12 @@ struct radeon_encoder_atom_dig { int panel_mode; struct radeon_afmt *afmt; struct r600_audio_pin *pin; - int active_mst_links; }; struct radeon_encoder_atom_dac { enum radeon_tv_std tv_std; }; -struct radeon_encoder_mst { - int crtc; - struct radeon_encoder *primary; - struct radeon_connector *connector; - struct drm_dp_mst_port *port; - int pbn; - int fe; - bool fe_from_be; - bool enc_active; -}; - struct radeon_encoder { struct drm_encoder base; uint32_t encoder_enum; @@ -479,8 +462,6 @@ struct radeon_encoder { enum radeon_output_csc output_csc; bool can_mst; uint32_t offset; - bool is_mst_encoder; - /* front end for this mst encoder */ }; struct radeon_connector_atom_dig { @@ -491,7 +472,6 @@ struct radeon_connector_atom_dig { int dp_clock; int dp_lane_count; bool edp_on; - bool is_mst; }; struct radeon_gpio_rec { @@ -535,11 +515,6 @@ enum radeon_connector_dither { RADEON_FMT_DITHER_ENABLE = 1, }; -struct stream_attribs { - uint16_t fe; - uint16_t slots; -}; - struct radeon_connector { struct drm_connector base; uint32_t connector_id; @@ -562,14 +537,6 @@ struct radeon_connector { enum radeon_connector_audio audio; enum radeon_connector_dither dither; int pixelclock_for_modeset; - bool is_mst_connector; - struct radeon_connector *mst_port; - struct drm_dp_mst_port *port; - struct drm_dp_mst_topology_mgr mst_mgr; - - struct radeon_encoder *mst_encoder; - struct stream_attribs cur_stream_attribs[6]; - int enabled_attribs; }; #define ENCODER_MODE_IS_DP(em) (((em) == ATOM_ENCODER_MODE_DP) || \ @@ -771,8 +738,6 @@ extern void atombios_dig_transmitter_setup(struct drm_encoder *encoder, extern void atombios_dig_transmitter_setup2(struct drm_encoder *encoder, int action, uint8_t lane_num, uint8_t lane_set, int fe); -extern void atombios_set_mst_encoder_crtc_source(struct drm_encoder *encoder, - int fe); extern void radeon_atom_ext_encoder_setup_ddc(struct drm_encoder *encoder); extern struct drm_encoder *radeon_get_external_encoder(struct drm_encoder *encoder); void radeon_atom_copy_swap(u8 *dst, u8 *src, u8 num_bytes, bool to_le); @@ -909,7 +874,6 @@ extern struct radeon_encoder_tv_dac * radeon_atombios_get_tv_dac_info(struct radeon_encoder *encoder); extern struct radeon_encoder_lvds * radeon_combios_get_lvds_info(struct radeon_encoder *encoder); -extern void radeon_combios_get_ext_tmds_info(struct radeon_encoder *encoder); extern struct radeon_encoder_tv_dac * radeon_combios_get_tv_dac_info(struct radeon_encoder *encoder); extern struct radeon_encoder_primary_dac * @@ -990,15 +954,6 @@ void radeon_crtc_handle_flip(struct radeon_device *rdev, int crtc_id); int radeon_align_pitch(struct radeon_device *rdev, int width, int bpp, bool tiled); -/* mst */ -int radeon_dp_mst_init(struct radeon_connector *radeon_connector); -int radeon_dp_mst_probe(struct radeon_connector *radeon_connector); -int radeon_dp_mst_check_status(struct radeon_connector *radeon_connector); -void radeon_mst_debugfs_init(struct radeon_device *rdev); -void radeon_dp_mst_prepare_pll(struct drm_crtc *crtc, struct drm_display_mode *mode); - -void radeon_setup_mst_connector(struct drm_device *dev); - int radeon_atom_pick_dig_encoder(struct drm_encoder *encoder, int fe_idx); void radeon_atom_release_dig_encoder(struct radeon_device *rdev, int enc_idx); #endif diff --git a/sys/dev/pci/drm/radeon/radeon_object.c b/sys/dev/pci/drm/radeon/radeon_object.c index d95f84e0f22..342a51dabb8 100644 --- a/sys/dev/pci/drm/radeon/radeon_object.c +++ b/sys/dev/pci/drm/radeon/radeon_object.c @@ -49,27 +49,6 @@ static void radeon_bo_clear_surface_reg(struct radeon_bo *bo); * function are calling it. */ -static void radeon_update_memory_usage(struct ttm_buffer_object *bo, - unsigned int mem_type, int sign) -{ - struct radeon_device *rdev = radeon_get_rdev(bo->bdev); - - switch (mem_type) { - case TTM_PL_TT: - if (sign > 0) - atomic64_add(bo->base.size, &rdev->gtt_usage); - else - atomic64_sub(bo->base.size, &rdev->gtt_usage); - break; - case TTM_PL_VRAM: - if (sign > 0) - atomic64_add(bo->base.size, &rdev->vram_usage); - else - atomic64_sub(bo->base.size, &rdev->vram_usage); - break; - } -} - static void radeon_ttm_bo_destroy(struct ttm_buffer_object *tbo) { struct radeon_bo *bo; @@ -223,9 +202,9 @@ int radeon_bo_create(struct radeon_device *rdev, radeon_ttm_placement_from_domain(bo, domain); /* Kernel allocation are uninterruptible */ down_read(&rdev->pm.mclk_lock); - r = ttm_bo_init(&rdev->mman.bdev, &bo->tbo, size, type, - &bo->placement, page_align, !kernel, sg, resv, - &radeon_ttm_bo_destroy); + r = ttm_bo_init_validate(&rdev->mman.bdev, &bo->tbo, type, + &bo->placement, page_align, !kernel, sg, resv, + &radeon_ttm_bo_destroy); up_read(&rdev->pm.mclk_lock); if (unlikely(r != 0)) { return r; @@ -240,7 +219,12 @@ int radeon_bo_create(struct radeon_device *rdev, int radeon_bo_kmap(struct radeon_bo *bo, void **ptr) { bool is_iomem; - int r; + long r; + + r = dma_resv_wait_timeout(bo->tbo.base.resv, DMA_RESV_USAGE_KERNEL, + false, MAX_SCHEDULE_TIMEOUT); + if (r < 0) + return r; if (bo->kptr) { if (ptr) { @@ -453,7 +437,9 @@ void radeon_bo_fini(struct radeon_device *rdev) static u64 radeon_bo_get_threshold_for_moves(struct radeon_device *rdev) { u64 real_vram_size = rdev->mc.real_vram_size; - u64 vram_usage = atomic64_read(&rdev->vram_usage); + struct ttm_resource_manager *man = + ttm_manager_type(&rdev->mman.bdev, TTM_PL_VRAM); + u64 vram_usage = ttm_resource_manager_usage(man); /* This function is based on the current VRAM usage. * @@ -586,7 +572,6 @@ int radeon_bo_get_surface_reg(struct radeon_bo *bo) return 0; if (bo->surface_reg >= 0) { - reg = &rdev->surface_regs[bo->surface_reg]; i = bo->surface_reg; goto out; } @@ -743,16 +728,10 @@ int radeon_bo_check_tiling(struct radeon_bo *bo, bool has_moved, return radeon_bo_get_surface_reg(bo); } -void radeon_bo_move_notify(struct ttm_buffer_object *bo, - unsigned int old_type, - struct ttm_resource *new_mem) +void radeon_bo_move_notify(struct ttm_buffer_object *bo) { struct radeon_bo *rbo; - radeon_update_memory_usage(bo, old_type, -1); - if (new_mem) - radeon_update_memory_usage(bo, new_mem->mem_type, 1); - if (!radeon_ttm_bo_is_radeon_bo(bo)) return; @@ -827,9 +806,15 @@ void radeon_bo_fence(struct radeon_bo *bo, struct radeon_fence *fence, bool shared) { struct dma_resv *resv = bo->tbo.base.resv; + int r; + + r = dma_resv_reserve_fences(resv, 1); + if (r) { + /* As last resort on OOM we block for the fence */ + dma_fence_wait(&fence->base, false); + return; + } - if (shared) - dma_resv_add_shared_fence(resv, &fence->base); - else - dma_resv_add_excl_fence(resv, &fence->base); + dma_resv_add_fence(resv, &fence->base, shared ? + DMA_RESV_USAGE_READ : DMA_RESV_USAGE_WRITE); } diff --git a/sys/dev/pci/drm/radeon/radeon_object.h b/sys/dev/pci/drm/radeon/radeon_object.h index 1afc7992ef9..0a6ef49e990 100644 --- a/sys/dev/pci/drm/radeon/radeon_object.h +++ b/sys/dev/pci/drm/radeon/radeon_object.h @@ -160,9 +160,7 @@ extern void radeon_bo_get_tiling_flags(struct radeon_bo *bo, u32 *tiling_flags, u32 *pitch); extern int radeon_bo_check_tiling(struct radeon_bo *bo, bool has_moved, bool force_drop); -extern void radeon_bo_move_notify(struct ttm_buffer_object *bo, - unsigned int old_type, - struct ttm_resource *new_mem); +extern void radeon_bo_move_notify(struct ttm_buffer_object *bo); extern vm_fault_t radeon_bo_fault_reserve_notify(struct ttm_buffer_object *bo); extern int radeon_bo_get_surface_reg(struct radeon_bo *bo); extern void radeon_bo_fence(struct radeon_bo *bo, struct radeon_fence *fence, diff --git a/sys/dev/pci/drm/radeon/radeon_pm.c b/sys/dev/pci/drm/radeon/radeon_pm.c index 4ed477c3441..db388419a04 100644 --- a/sys/dev/pci/drm/radeon/radeon_pm.c +++ b/sys/dev/pci/drm/radeon/radeon_pm.c @@ -1650,7 +1650,7 @@ int radeon_pm_late_init(struct radeon_device *rdev) ret = device_create_file(rdev->dev, &dev_attr_power_method); if (ret) DRM_ERROR("failed to create device file for power method\n"); - if (!ret) + else rdev->pm.sysfs_initialized = true; } #endif @@ -1921,7 +1921,7 @@ static void radeon_dynpm_idle_work_handler(struct work_struct *work) * to false since we want to wait for vbl to avoid flicker. */ if (rdev->pm.dynpm_planned_action != DYNPM_ACTION_NONE && - jiffies > rdev->pm.dynpm_action_timeout) { + time_after(jiffies, rdev->pm.dynpm_action_timeout)) { radeon_pm_get_dynpm_state(rdev); radeon_pm_set_clocks(rdev); } diff --git a/sys/dev/pci/drm/radeon/radeon_prime.c b/sys/dev/pci/drm/radeon/radeon_prime.c index 5331ab3bc99..c3f2030a436 100644 --- a/sys/dev/pci/drm/radeon/radeon_prime.c +++ b/sys/dev/pci/drm/radeon/radeon_prime.c @@ -80,19 +80,9 @@ int radeon_gem_prime_pin(struct drm_gem_object *obj) /* pin buffer into GTT */ ret = radeon_bo_pin(bo, RADEON_GEM_DOMAIN_GTT, NULL); - if (unlikely(ret)) - goto error; - - if (bo->tbo.moving) { - ret = dma_fence_wait(bo->tbo.moving, false); - if (unlikely(ret)) { - radeon_bo_unpin(bo); - goto error; - } - } - - bo->prime_shared_count++; -error: + if (likely(ret == 0)) + bo->prime_shared_count++; + radeon_bo_unreserve(bo); return ret; } diff --git a/sys/dev/pci/drm/radeon/radeon_sa.c b/sys/dev/pci/drm/radeon/radeon_sa.c index 310c322c711..0981948bd9e 100644 --- a/sys/dev/pci/drm/radeon/radeon_sa.c +++ b/sys/dev/pci/drm/radeon/radeon_sa.c @@ -267,6 +267,8 @@ static bool radeon_sa_bo_next_hole(struct radeon_sa_manager *sa_manager, for (i = 0; i < RADEON_NUM_RINGS; ++i) { struct radeon_sa_bo *sa_bo; + fences[i] = NULL; + if (list_empty(&sa_manager->flist[i])) { continue; } @@ -332,10 +334,8 @@ int radeon_sa_bo_new(struct radeon_device *rdev, spin_lock(&sa_manager->wq.lock); do { - for (i = 0; i < RADEON_NUM_RINGS; ++i) { - fences[i] = NULL; + for (i = 0; i < RADEON_NUM_RINGS; ++i) tries[i] = 0; - } do { radeon_sa_bo_try_free(sa_manager); diff --git a/sys/dev/pci/drm/radeon/radeon_sync.c b/sys/dev/pci/drm/radeon/radeon_sync.c index 9257b60144c..6416f129e09 100644 --- a/sys/dev/pci/drm/radeon/radeon_sync.c +++ b/sys/dev/pci/drm/radeon/radeon_sync.c @@ -91,33 +91,17 @@ int radeon_sync_resv(struct radeon_device *rdev, struct dma_resv *resv, bool shared) { - struct dma_resv_list *flist; - struct dma_fence *f; + struct dma_resv_iter cursor; struct radeon_fence *fence; - unsigned i; + struct dma_fence *f; int r = 0; - /* always sync to the exclusive fence */ - f = dma_resv_excl_fence(resv); - fence = f ? to_radeon_fence(f) : NULL; - if (fence && fence->rdev == rdev) - radeon_sync_fence(sync, fence); - else if (f) - r = dma_fence_wait(f, true); - - flist = dma_resv_shared_list(resv); - if (shared || !flist || r) - return r; - - for (i = 0; i < flist->shared_count; ++i) { - f = rcu_dereference_protected(flist->shared[i], - dma_resv_held(resv)); + dma_resv_for_each_fence(&cursor, resv, dma_resv_usage_rw(!shared), f) { fence = to_radeon_fence(f); if (fence && fence->rdev == rdev) radeon_sync_fence(sync, fence); else r = dma_fence_wait(f, true); - if (r) break; } diff --git a/sys/dev/pci/drm/radeon/radeon_ttm.c b/sys/dev/pci/drm/radeon/radeon_ttm.c index a21a27e3aee..94ec0117111 100644 --- a/sys/dev/pci/drm/radeon/radeon_ttm.c +++ b/sys/dev/pci/drm/radeon/radeon_ttm.c @@ -207,7 +207,7 @@ static int radeon_bo_move(struct ttm_buffer_object *bo, bool evict, struct ttm_resource *old_mem = bo->resource; struct radeon_device *rdev; struct radeon_bo *rbo; - int r, old_type; + int r; if (new_mem->mem_type == TTM_PL_TT) { r = radeon_ttm_tt_bind(bo->bdev, bo->ttm, new_mem); @@ -224,9 +224,6 @@ static int radeon_bo_move(struct ttm_buffer_object *bo, bool evict, if (WARN_ON_ONCE(rbo->tbo.pin_count > 0)) return -EINVAL; - /* Save old type for statistics update */ - old_type = old_mem->mem_type; - rdev = radeon_get_rdev(bo->bdev); if (old_mem->mem_type == TTM_PL_SYSTEM && bo->ttm == NULL) { ttm_bo_move_null(bo, new_mem); @@ -272,7 +269,7 @@ static int radeon_bo_move(struct ttm_buffer_object *bo, bool evict, out: /* update statistics */ atomic64_add(bo->base.size, &rdev->num_bytes_moved); - radeon_bo_move_notify(bo, old_type, new_mem); + radeon_bo_move_notify(bo); return 0; } @@ -503,9 +500,6 @@ static void radeon_ttm_backend_destroy(struct ttm_device *bdev, struct ttm_tt *t { struct radeon_ttm_tt *gtt = (void *)ttm; - radeon_ttm_backend_unbind(bdev, ttm); - ttm_tt_destroy_common(bdev, ttm); - ttm_tt_fini(>t->ttm); kfree(gtt); } @@ -563,14 +557,14 @@ static int radeon_ttm_tt_populate(struct ttm_device *bdev, { struct radeon_device *rdev = radeon_get_rdev(bdev); struct radeon_ttm_tt *gtt = radeon_ttm_tt_to_gtt(rdev, ttm); - bool slave = !!(ttm->page_flags & TTM_PAGE_FLAG_SG); + bool slave = !!(ttm->page_flags & TTM_TT_FLAG_EXTERNAL); if (gtt && gtt->userptr) { ttm->sg = kzalloc(sizeof(struct sg_table), GFP_KERNEL); if (!ttm->sg) return -ENOMEM; - ttm->page_flags |= TTM_PAGE_FLAG_SG; + ttm->page_flags |= TTM_TT_FLAG_EXTERNAL; return 0; } @@ -587,11 +581,13 @@ static void radeon_ttm_tt_unpopulate(struct ttm_device *bdev, struct ttm_tt *ttm { struct radeon_device *rdev = radeon_get_rdev(bdev); struct radeon_ttm_tt *gtt = radeon_ttm_tt_to_gtt(rdev, ttm); - bool slave = !!(ttm->page_flags & TTM_PAGE_FLAG_SG); + bool slave = !!(ttm->page_flags & TTM_TT_FLAG_EXTERNAL); + + radeon_ttm_tt_unbind(bdev, ttm); if (gtt && gtt->userptr) { kfree(ttm->sg); - ttm->page_flags &= ~TTM_PAGE_FLAG_SG; + ttm->page_flags &= ~TTM_TT_FLAG_EXTERNAL; return; } @@ -670,8 +666,6 @@ static void radeon_ttm_tt_destroy(struct ttm_device *bdev, struct radeon_device *rdev = radeon_get_rdev(bdev); if (rdev->flags & RADEON_IS_AGP) { - ttm_agp_unbind(ttm); - ttm_tt_destroy_common(bdev, ttm); ttm_agp_destroy(ttm); return; } @@ -701,16 +695,6 @@ bool radeon_ttm_tt_is_readonly(struct radeon_device *rdev, return !!(gtt->userflags & RADEON_GEM_USERPTR_READONLY); } -static void -radeon_bo_delete_mem_notify(struct ttm_buffer_object *bo) -{ - unsigned int old_type = TTM_PL_SYSTEM; - - if (bo->resource) - old_type = bo->resource->mem_type; - radeon_bo_move_notify(bo, old_type, NULL); -} - static struct ttm_device_funcs radeon_bo_driver = { .ttm_tt_create = &radeon_ttm_tt_create, .ttm_tt_populate = &radeon_ttm_tt_populate, @@ -719,7 +703,6 @@ static struct ttm_device_funcs radeon_bo_driver = { .eviction_valuable = ttm_bo_eviction_valuable, .evict_flags = &radeon_evict_flags, .move = &radeon_bo_move, - .delete_mem_notify = &radeon_bo_delete_mem_notify, .io_mem_reserve = &radeon_ttm_io_mem_reserve, }; @@ -841,17 +824,6 @@ void radeon_ttm_set_active_vram_size(struct radeon_device *rdev, u64 size) #if defined(CONFIG_DEBUG_FS) -static int radeon_mm_vram_dump_table_show(struct seq_file *m, void *unused) -{ - struct radeon_device *rdev = (struct radeon_device *)m->private; - struct ttm_resource_manager *man = ttm_manager_type(&rdev->mman.bdev, - TTM_PL_VRAM); - struct drm_printer p = drm_seq_file_printer(m); - - man->func->debug(man, &p); - return 0; -} - static int radeon_ttm_page_pool_show(struct seq_file *m, void *data) { struct radeon_device *rdev = (struct radeon_device *)m->private; @@ -859,19 +831,6 @@ static int radeon_ttm_page_pool_show(struct seq_file *m, void *data) return ttm_pool_debugfs(&rdev->mman.bdev.pool, m); } -static int radeon_mm_gtt_dump_table_show(struct seq_file *m, void *unused) -{ - struct radeon_device *rdev = (struct radeon_device *)m->private; - struct ttm_resource_manager *man = ttm_manager_type(&rdev->mman.bdev, - TTM_PL_TT); - struct drm_printer p = drm_seq_file_printer(m); - - man->func->debug(man, &p); - return 0; -} - -DEFINE_SHOW_ATTRIBUTE(radeon_mm_vram_dump_table); -DEFINE_SHOW_ATTRIBUTE(radeon_mm_gtt_dump_table); DEFINE_SHOW_ATTRIBUTE(radeon_ttm_page_pool); static int radeon_ttm_vram_open(struct inode *inode, struct file *filep) @@ -990,15 +949,15 @@ static void radeon_ttm_debugfs_init(struct radeon_device *rdev) debugfs_create_file("radeon_vram", 0444, root, rdev, &radeon_ttm_vram_fops); - debugfs_create_file("radeon_gtt", 0444, root, rdev, &radeon_ttm_gtt_fops); - - debugfs_create_file("radeon_vram_mm", 0444, root, rdev, - &radeon_mm_vram_dump_table_fops); - debugfs_create_file("radeon_gtt_mm", 0444, root, rdev, - &radeon_mm_gtt_dump_table_fops); debugfs_create_file("ttm_page_pool", 0444, root, rdev, &radeon_ttm_page_pool_fops); + ttm_resource_manager_create_debugfs(ttm_manager_type(&rdev->mman.bdev, + TTM_PL_VRAM), + root, "radeon_vram_mm"); + ttm_resource_manager_create_debugfs(ttm_manager_type(&rdev->mman.bdev, + TTM_PL_TT), + root, "radeon_gtt_mm"); #endif } diff --git a/sys/dev/pci/drm/radeon/radeon_uvd.c b/sys/dev/pci/drm/radeon/radeon_uvd.c index 0ba94c140f0..78c72d301c4 100644 --- a/sys/dev/pci/drm/radeon/radeon_uvd.c +++ b/sys/dev/pci/drm/radeon/radeon_uvd.c @@ -469,9 +469,7 @@ static int radeon_uvd_cs_msg(struct radeon_cs_parser *p, struct radeon_bo *bo, { int32_t *msg, msg_type, handle; unsigned img_size = 0; - struct dma_fence *f; void *ptr; - int i, r; if (offset & 0x3F) { @@ -479,15 +477,6 @@ static int radeon_uvd_cs_msg(struct radeon_cs_parser *p, struct radeon_bo *bo, return -EINVAL; } - f = dma_resv_excl_fence(bo->tbo.base.resv); - if (f) { - r = radeon_fence_wait((struct radeon_fence *)f, false); - if (r) { - DRM_ERROR("Failed waiting for UVD message (%d)!\n", r); - return r; - } - } - r = radeon_bo_kmap(bo, &ptr); if (r) { DRM_ERROR("Failed mapping the UVD message (%d)!\n", r); @@ -500,6 +489,7 @@ static int radeon_uvd_cs_msg(struct radeon_cs_parser *p, struct radeon_bo *bo, handle = msg[2]; if (handle == 0) { + radeon_bo_kunmap(bo); DRM_ERROR("Invalid UVD handle!\n"); return -EINVAL; } @@ -562,12 +552,10 @@ static int radeon_uvd_cs_msg(struct radeon_cs_parser *p, struct radeon_bo *bo, return 0; default: - DRM_ERROR("Illegal UVD message type (%d)!\n", msg_type); - return -EINVAL; } - BUG(); + radeon_bo_kunmap(bo); return -EINVAL; } diff --git a/sys/dev/pci/drm/radeon/radeon_vce.c b/sys/dev/pci/drm/radeon/radeon_vce.c index 1b34b4172de..906fd772db1 100644 --- a/sys/dev/pci/drm/radeon/radeon_vce.c +++ b/sys/dev/pci/drm/radeon/radeon_vce.c @@ -543,7 +543,7 @@ int radeon_vce_cs_reloc(struct radeon_cs_parser *p, int lo, int hi, * @allocated: allocated a new handle? * * Validates the handle and return the found session index or -EINVAL - * we we don't have another free session index. + * we don't have another free session index. */ static int radeon_vce_validate_handle(struct radeon_cs_parser *p, uint32_t handle, bool *allocated) diff --git a/sys/dev/pci/drm/radeon/radeon_vm.c b/sys/dev/pci/drm/radeon/radeon_vm.c index d55f24155e2..a1365f99d6b 100644 --- a/sys/dev/pci/drm/radeon/radeon_vm.c +++ b/sys/dev/pci/drm/radeon/radeon_vm.c @@ -831,7 +831,7 @@ static int radeon_vm_update_ptes(struct radeon_device *rdev, int r; radeon_sync_resv(rdev, &ib->sync, pt->tbo.base.resv, true); - r = dma_resv_reserve_shared(pt->tbo.base.resv, 1); + r = dma_resv_reserve_fences(pt->tbo.base.resv, 1); if (r) return r; diff --git a/sys/dev/pci/drm/radeon/rs600.c b/sys/dev/pci/drm/radeon/rs600.c index 0096baafbc2..7c7d0f19507 100644 --- a/sys/dev/pci/drm/radeon/rs600.c +++ b/sys/dev/pci/drm/radeon/rs600.c @@ -42,6 +42,7 @@ #include <drm/drm_device.h> #include <drm/drm_vblank.h> #include <drm/drm_fourcc.h> +#include <drm/drm_framebuffer.h> #include "atom.h" #include "radeon.h" diff --git a/sys/dev/pci/drm/radeon/rv770.c b/sys/dev/pci/drm/radeon/rv770.c index 61a80a69782..c7abe8b6dcd 100644 --- a/sys/dev/pci/drm/radeon/rv770.c +++ b/sys/dev/pci/drm/radeon/rv770.c @@ -33,6 +33,7 @@ #include <drm/drm_device.h> #include <drm/radeon_drm.h> #include <drm/drm_fourcc.h> +#include <drm/drm_framebuffer.h> #include "atom.h" #include "avivod.h" @@ -1894,8 +1895,8 @@ int rv770_suspend(struct radeon_device *rdev) radeon_pm_suspend(rdev); radeon_audio_fini(rdev); if (rdev->has_uvd) { - uvd_v1_0_fini(rdev); radeon_uvd_suspend(rdev); + uvd_v1_0_fini(rdev); } r700_cp_stop(rdev); r600_dma_stop(rdev); diff --git a/sys/dev/pci/drm/radeon/si.c b/sys/dev/pci/drm/radeon/si.c index 5e723ca5e7d..4b560e22faf 100644 --- a/sys/dev/pci/drm/radeon/si.c +++ b/sys/dev/pci/drm/radeon/si.c @@ -6802,8 +6802,8 @@ int si_suspend(struct radeon_device *rdev) si_cp_enable(rdev, false); cayman_dma_stop(rdev); if (rdev->has_uvd) { - uvd_v1_0_fini(rdev); radeon_uvd_suspend(rdev); + uvd_v1_0_fini(rdev); } if (rdev->has_vce) radeon_vce_suspend(rdev); diff --git a/sys/dev/pci/drm/radeon/si_blit_shaders.c b/sys/dev/pci/drm/radeon/si_blit_shaders.c deleted file mode 100644 index ec415e7dfa4..00000000000 --- a/sys/dev/pci/drm/radeon/si_blit_shaders.c +++ /dev/null @@ -1,253 +0,0 @@ -/* - * Copyright 2011 Advanced Micro Devices, Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice (including the next - * paragraph) shall be included in all copies or substantial portions of the - * Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - * - * Authors: - * Alex Deucher <alexander.deucher@amd.com> - */ - -#include <linux/types.h> -#include <linux/bug.h> -#include <linux/kernel.h> - -const u32 si_default_state[] = -{ - 0xc0066900, - 0x00000000, - 0x00000060, /* DB_RENDER_CONTROL */ - 0x00000000, /* DB_COUNT_CONTROL */ - 0x00000000, /* DB_DEPTH_VIEW */ - 0x0000002a, /* DB_RENDER_OVERRIDE */ - 0x00000000, /* DB_RENDER_OVERRIDE2 */ - 0x00000000, /* DB_HTILE_DATA_BASE */ - - 0xc0046900, - 0x00000008, - 0x00000000, /* DB_DEPTH_BOUNDS_MIN */ - 0x00000000, /* DB_DEPTH_BOUNDS_MAX */ - 0x00000000, /* DB_STENCIL_CLEAR */ - 0x00000000, /* DB_DEPTH_CLEAR */ - - 0xc0036900, - 0x0000000f, - 0x00000000, /* DB_DEPTH_INFO */ - 0x00000000, /* DB_Z_INFO */ - 0x00000000, /* DB_STENCIL_INFO */ - - 0xc0016900, - 0x00000080, - 0x00000000, /* PA_SC_WINDOW_OFFSET */ - - 0xc00d6900, - 0x00000083, - 0x0000ffff, /* PA_SC_CLIPRECT_RULE */ - 0x00000000, /* PA_SC_CLIPRECT_0_TL */ - 0x20002000, /* PA_SC_CLIPRECT_0_BR */ - 0x00000000, - 0x20002000, - 0x00000000, - 0x20002000, - 0x00000000, - 0x20002000, - 0xaaaaaaaa, /* PA_SC_EDGERULE */ - 0x00000000, /* PA_SU_HARDWARE_SCREEN_OFFSET */ - 0x0000000f, /* CB_TARGET_MASK */ - 0x0000000f, /* CB_SHADER_MASK */ - - 0xc0226900, - 0x00000094, - 0x80000000, /* PA_SC_VPORT_SCISSOR_0_TL */ - 0x20002000, /* PA_SC_VPORT_SCISSOR_0_BR */ - 0x80000000, - 0x20002000, - 0x80000000, - 0x20002000, - 0x80000000, - 0x20002000, - 0x80000000, - 0x20002000, - 0x80000000, - 0x20002000, - 0x80000000, - 0x20002000, - 0x80000000, - 0x20002000, - 0x80000000, - 0x20002000, - 0x80000000, - 0x20002000, - 0x80000000, - 0x20002000, - 0x80000000, - 0x20002000, - 0x80000000, - 0x20002000, - 0x80000000, - 0x20002000, - 0x80000000, - 0x20002000, - 0x80000000, - 0x20002000, - 0x00000000, /* PA_SC_VPORT_ZMIN_0 */ - 0x3f800000, /* PA_SC_VPORT_ZMAX_0 */ - - 0xc0026900, - 0x000000d9, - 0x00000000, /* CP_RINGID */ - 0x00000000, /* CP_VMID */ - - 0xc0046900, - 0x00000100, - 0xffffffff, /* VGT_MAX_VTX_INDX */ - 0x00000000, /* VGT_MIN_VTX_INDX */ - 0x00000000, /* VGT_INDX_OFFSET */ - 0x00000000, /* VGT_MULTI_PRIM_IB_RESET_INDX */ - - 0xc0046900, - 0x00000105, - 0x00000000, /* CB_BLEND_RED */ - 0x00000000, /* CB_BLEND_GREEN */ - 0x00000000, /* CB_BLEND_BLUE */ - 0x00000000, /* CB_BLEND_ALPHA */ - - 0xc0016900, - 0x000001e0, - 0x00000000, /* CB_BLEND0_CONTROL */ - - 0xc00e6900, - 0x00000200, - 0x00000000, /* DB_DEPTH_CONTROL */ - 0x00000000, /* DB_EQAA */ - 0x00cc0010, /* CB_COLOR_CONTROL */ - 0x00000210, /* DB_SHADER_CONTROL */ - 0x00010000, /* PA_CL_CLIP_CNTL */ - 0x00000004, /* PA_SU_SC_MODE_CNTL */ - 0x00000100, /* PA_CL_VTE_CNTL */ - 0x00000000, /* PA_CL_VS_OUT_CNTL */ - 0x00000000, /* PA_CL_NANINF_CNTL */ - 0x00000000, /* PA_SU_LINE_STIPPLE_CNTL */ - 0x00000000, /* PA_SU_LINE_STIPPLE_SCALE */ - 0x00000000, /* PA_SU_PRIM_FILTER_CNTL */ - 0x00000000, /* */ - 0x00000000, /* */ - - 0xc0116900, - 0x00000280, - 0x00000000, /* PA_SU_POINT_SIZE */ - 0x00000000, /* PA_SU_POINT_MINMAX */ - 0x00000008, /* PA_SU_LINE_CNTL */ - 0x00000000, /* PA_SC_LINE_STIPPLE */ - 0x00000000, /* VGT_OUTPUT_PATH_CNTL */ - 0x00000000, /* VGT_HOS_CNTL */ - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, /* VGT_GS_MODE */ - - 0xc0026900, - 0x00000292, - 0x00000000, /* PA_SC_MODE_CNTL_0 */ - 0x00000000, /* PA_SC_MODE_CNTL_1 */ - - 0xc0016900, - 0x000002a1, - 0x00000000, /* VGT_PRIMITIVEID_EN */ - - 0xc0016900, - 0x000002a5, - 0x00000000, /* VGT_MULTI_PRIM_IB_RESET_EN */ - - 0xc0026900, - 0x000002a8, - 0x00000000, /* VGT_INSTANCE_STEP_RATE_0 */ - 0x00000000, - - 0xc0026900, - 0x000002ad, - 0x00000000, /* VGT_REUSE_OFF */ - 0x00000000, - - 0xc0016900, - 0x000002d5, - 0x00000000, /* VGT_SHADER_STAGES_EN */ - - 0xc0016900, - 0x000002dc, - 0x0000aa00, /* DB_ALPHA_TO_MASK */ - - 0xc0066900, - 0x000002de, - 0x00000000, /* PA_SU_POLY_OFFSET_DB_FMT_CNTL */ - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - - 0xc0026900, - 0x000002e5, - 0x00000000, /* VGT_STRMOUT_CONFIG */ - 0x00000000, - - 0xc01b6900, - 0x000002f5, - 0x76543210, /* PA_SC_CENTROID_PRIORITY_0 */ - 0xfedcba98, /* PA_SC_CENTROID_PRIORITY_1 */ - 0x00000000, /* PA_SC_LINE_CNTL */ - 0x00000000, /* PA_SC_AA_CONFIG */ - 0x00000005, /* PA_SU_VTX_CNTL */ - 0x3f800000, /* PA_CL_GB_VERT_CLIP_ADJ */ - 0x3f800000, /* PA_CL_GB_VERT_DISC_ADJ */ - 0x3f800000, /* PA_CL_GB_HORZ_CLIP_ADJ */ - 0x3f800000, /* PA_CL_GB_HORZ_DISC_ADJ */ - 0x00000000, /* PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0 */ - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0xffffffff, /* PA_SC_AA_MASK_X0Y0_X1Y0 */ - 0xffffffff, - - 0xc0026900, - 0x00000316, - 0x0000000e, /* VGT_VERTEX_REUSE_BLOCK_CNTL */ - 0x00000010, /* */ -}; - -const u32 si_default_size = ARRAY_SIZE(si_default_state); diff --git a/sys/dev/pci/drm/radeon/si_blit_shaders.h b/sys/dev/pci/drm/radeon/si_blit_shaders.h index c739e51e396..829a2b6228b 100644 --- a/sys/dev/pci/drm/radeon/si_blit_shaders.h +++ b/sys/dev/pci/drm/radeon/si_blit_shaders.h @@ -25,8 +25,227 @@ #ifndef SI_BLIT_SHADERS_H #define SI_BLIT_SHADERS_H -extern const u32 si_default_state[]; +static const u32 si_default_state[] = { + 0xc0066900, + 0x00000000, + 0x00000060, /* DB_RENDER_CONTROL */ + 0x00000000, /* DB_COUNT_CONTROL */ + 0x00000000, /* DB_DEPTH_VIEW */ + 0x0000002a, /* DB_RENDER_OVERRIDE */ + 0x00000000, /* DB_RENDER_OVERRIDE2 */ + 0x00000000, /* DB_HTILE_DATA_BASE */ -extern const u32 si_default_size; + 0xc0046900, + 0x00000008, + 0x00000000, /* DB_DEPTH_BOUNDS_MIN */ + 0x00000000, /* DB_DEPTH_BOUNDS_MAX */ + 0x00000000, /* DB_STENCIL_CLEAR */ + 0x00000000, /* DB_DEPTH_CLEAR */ + + 0xc0036900, + 0x0000000f, + 0x00000000, /* DB_DEPTH_INFO */ + 0x00000000, /* DB_Z_INFO */ + 0x00000000, /* DB_STENCIL_INFO */ + + 0xc0016900, + 0x00000080, + 0x00000000, /* PA_SC_WINDOW_OFFSET */ + + 0xc00d6900, + 0x00000083, + 0x0000ffff, /* PA_SC_CLIPRECT_RULE */ + 0x00000000, /* PA_SC_CLIPRECT_0_TL */ + 0x20002000, /* PA_SC_CLIPRECT_0_BR */ + 0x00000000, + 0x20002000, + 0x00000000, + 0x20002000, + 0x00000000, + 0x20002000, + 0xaaaaaaaa, /* PA_SC_EDGERULE */ + 0x00000000, /* PA_SU_HARDWARE_SCREEN_OFFSET */ + 0x0000000f, /* CB_TARGET_MASK */ + 0x0000000f, /* CB_SHADER_MASK */ + + 0xc0226900, + 0x00000094, + 0x80000000, /* PA_SC_VPORT_SCISSOR_0_TL */ + 0x20002000, /* PA_SC_VPORT_SCISSOR_0_BR */ + 0x80000000, + 0x20002000, + 0x80000000, + 0x20002000, + 0x80000000, + 0x20002000, + 0x80000000, + 0x20002000, + 0x80000000, + 0x20002000, + 0x80000000, + 0x20002000, + 0x80000000, + 0x20002000, + 0x80000000, + 0x20002000, + 0x80000000, + 0x20002000, + 0x80000000, + 0x20002000, + 0x80000000, + 0x20002000, + 0x80000000, + 0x20002000, + 0x80000000, + 0x20002000, + 0x80000000, + 0x20002000, + 0x80000000, + 0x20002000, + 0x00000000, /* PA_SC_VPORT_ZMIN_0 */ + 0x3f800000, /* PA_SC_VPORT_ZMAX_0 */ + + 0xc0026900, + 0x000000d9, + 0x00000000, /* CP_RINGID */ + 0x00000000, /* CP_VMID */ + + 0xc0046900, + 0x00000100, + 0xffffffff, /* VGT_MAX_VTX_INDX */ + 0x00000000, /* VGT_MIN_VTX_INDX */ + 0x00000000, /* VGT_INDX_OFFSET */ + 0x00000000, /* VGT_MULTI_PRIM_IB_RESET_INDX */ + + 0xc0046900, + 0x00000105, + 0x00000000, /* CB_BLEND_RED */ + 0x00000000, /* CB_BLEND_GREEN */ + 0x00000000, /* CB_BLEND_BLUE */ + 0x00000000, /* CB_BLEND_ALPHA */ + + 0xc0016900, + 0x000001e0, + 0x00000000, /* CB_BLEND0_CONTROL */ + + 0xc00e6900, + 0x00000200, + 0x00000000, /* DB_DEPTH_CONTROL */ + 0x00000000, /* DB_EQAA */ + 0x00cc0010, /* CB_COLOR_CONTROL */ + 0x00000210, /* DB_SHADER_CONTROL */ + 0x00010000, /* PA_CL_CLIP_CNTL */ + 0x00000004, /* PA_SU_SC_MODE_CNTL */ + 0x00000100, /* PA_CL_VTE_CNTL */ + 0x00000000, /* PA_CL_VS_OUT_CNTL */ + 0x00000000, /* PA_CL_NANINF_CNTL */ + 0x00000000, /* PA_SU_LINE_STIPPLE_CNTL */ + 0x00000000, /* PA_SU_LINE_STIPPLE_SCALE */ + 0x00000000, /* PA_SU_PRIM_FILTER_CNTL */ + 0x00000000, /* */ + 0x00000000, /* */ + + 0xc0116900, + 0x00000280, + 0x00000000, /* PA_SU_POINT_SIZE */ + 0x00000000, /* PA_SU_POINT_MINMAX */ + 0x00000008, /* PA_SU_LINE_CNTL */ + 0x00000000, /* PA_SC_LINE_STIPPLE */ + 0x00000000, /* VGT_OUTPUT_PATH_CNTL */ + 0x00000000, /* VGT_HOS_CNTL */ + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, /* VGT_GS_MODE */ + + 0xc0026900, + 0x00000292, + 0x00000000, /* PA_SC_MODE_CNTL_0 */ + 0x00000000, /* PA_SC_MODE_CNTL_1 */ + + 0xc0016900, + 0x000002a1, + 0x00000000, /* VGT_PRIMITIVEID_EN */ + + 0xc0016900, + 0x000002a5, + 0x00000000, /* VGT_MULTI_PRIM_IB_RESET_EN */ + + 0xc0026900, + 0x000002a8, + 0x00000000, /* VGT_INSTANCE_STEP_RATE_0 */ + 0x00000000, + + 0xc0026900, + 0x000002ad, + 0x00000000, /* VGT_REUSE_OFF */ + 0x00000000, + + 0xc0016900, + 0x000002d5, + 0x00000000, /* VGT_SHADER_STAGES_EN */ + + 0xc0016900, + 0x000002dc, + 0x0000aa00, /* DB_ALPHA_TO_MASK */ + + 0xc0066900, + 0x000002de, + 0x00000000, /* PA_SU_POLY_OFFSET_DB_FMT_CNTL */ + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + + 0xc0026900, + 0x000002e5, + 0x00000000, /* VGT_STRMOUT_CONFIG */ + 0x00000000, + + 0xc01b6900, + 0x000002f5, + 0x76543210, /* PA_SC_CENTROID_PRIORITY_0 */ + 0xfedcba98, /* PA_SC_CENTROID_PRIORITY_1 */ + 0x00000000, /* PA_SC_LINE_CNTL */ + 0x00000000, /* PA_SC_AA_CONFIG */ + 0x00000005, /* PA_SU_VTX_CNTL */ + 0x3f800000, /* PA_CL_GB_VERT_CLIP_ADJ */ + 0x3f800000, /* PA_CL_GB_VERT_DISC_ADJ */ + 0x3f800000, /* PA_CL_GB_HORZ_CLIP_ADJ */ + 0x3f800000, /* PA_CL_GB_HORZ_DISC_ADJ */ + 0x00000000, /* PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0 */ + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0xffffffff, /* PA_SC_AA_MASK_X0Y0_X1Y0 */ + 0xffffffff, + + 0xc0026900, + 0x00000316, + 0x0000000e, /* VGT_VERTEX_REUSE_BLOCK_CNTL */ + 0x00000010, /* */ +}; + +static const u32 si_default_size = ARRAY_SIZE(si_default_state); #endif diff --git a/sys/dev/pci/drm/radeon/si_dpm.c b/sys/dev/pci/drm/radeon/si_dpm.c index 3add39c1a68..fbf968e3f6d 100644 --- a/sys/dev/pci/drm/radeon/si_dpm.c +++ b/sys/dev/pci/drm/radeon/si_dpm.c @@ -329,7 +329,7 @@ static const struct si_dte_data dte_data_malta = true }; -struct si_cac_config_reg cac_weights_pitcairn[] = +static struct si_cac_config_reg cac_weights_pitcairn[] = { { 0x0, 0x0000ffff, 0, 0x8a, SISLANDS_CACCONFIG_CGIND }, { 0x0, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, @@ -1085,7 +1085,7 @@ static const struct si_dte_data dte_data_venus_pro = true }; -struct si_cac_config_reg cac_weights_oland[] = +static struct si_cac_config_reg cac_weights_oland[] = { { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND }, { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND }, |