diff options
| author | Kevin Lo <kevlo@cvs.openbsd.org> | 2019-03-22 15:33:31 +0000 |
|---|---|---|
| committer | Kevin Lo <kevlo@cvs.openbsd.org> | 2019-03-22 15:33:31 +0000 |
| commit | d89b93de12925c4d6601b3796d06dfa4cd49afe1 (patch) | |
| tree | 8b4100b74cee2ffaa5cf521441986bb3ba001a83 /sys/dev/pci/if_alc.c | |
| parent | 7d8cb6dd6899243e9cf862f004e150b134b5ecfe (diff) | |
Mixmerge fixup.
Some of the flag and oactive handling bits and alc_stop_queue() were
mismerged.
Pointed out by Brad, thanks!
Diffstat (limited to 'sys/dev/pci/if_alc.c')
| -rw-r--r-- | sys/dev/pci/if_alc.c | 19 |
1 files changed, 8 insertions, 11 deletions
diff --git a/sys/dev/pci/if_alc.c b/sys/dev/pci/if_alc.c index 433ab55dc9e..f44f643b2da 100644 --- a/sys/dev/pci/if_alc.c +++ b/sys/dev/pci/if_alc.c @@ -1,4 +1,4 @@ -/* $OpenBSD: if_alc.c,v 1.43 2019/03/22 09:04:46 kevlo Exp $ */ +/* $OpenBSD: if_alc.c,v 1.44 2019/03/22 15:33:30 kevlo Exp $ */ /*- * Copyright (c) 2009, Pyun YongHyeon <yongari@FreeBSD.org> * All rights reserved. @@ -3038,16 +3038,13 @@ alc_init(struct ifnet *ifp) CSR_WRITE_4(sc, ALC_INTR_STATUS, 0); ifp->if_flags |= IFF_RUNNING; - ifp->if_flags &= ~IFF_OACTIVE; + ifq_clr_oactive(&ifp->if_snd); sc->alc_flags &= ~ALC_FLAG_LINK; /* Switch to the current media. */ alc_mediachange(ifp); timeout_add_sec(&sc->alc_tick_ch, 1); - ifp->if_flags |= IFF_RUNNING; - ifp->if_flags &= ~IFF_OACTIVE; - return (0); } @@ -3182,12 +3179,6 @@ alc_stop_queue(struct alc_softc *sc) /* Disable RxQ. */ reg = CSR_READ_4(sc, ALC_RXQ_CFG); - if ((reg & RXQ_CFG_ENB) != 0) { - reg &= ~RXQ_CFG_ENB; - CSR_WRITE_4(sc, ALC_RXQ_CFG, reg); - } - /* Disable TxQ. */ - reg = CSR_READ_4(sc, ALC_TXQ_CFG); if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) == 0) { if ((reg & RXQ_CFG_ENB) != 0) { reg &= ~RXQ_CFG_ENB; @@ -3199,6 +3190,12 @@ alc_stop_queue(struct alc_softc *sc) CSR_WRITE_4(sc, ALC_RXQ_CFG, reg); } } + /* Disable TxQ. */ + reg = CSR_READ_4(sc, ALC_TXQ_CFG); + if ((reg & TXQ_CFG_ENB) != 0) { + reg &= ~TXQ_CFG_ENB; + CSR_WRITE_4(sc, ALC_TXQ_CFG, reg); + } DELAY(40); for (i = ALC_TIMEOUT; i > 0; i--) { reg = CSR_READ_4(sc, ALC_IDLE_STATUS); |