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author	Brad Smith <brad@cvs.openbsd.org>	2006-07-03 20:55:56 +0000
committer	Brad Smith <brad@cvs.openbsd.org>	2006-07-03 20:55:56 +0000
commit	12fb0dfbbd42495bd79b8697eeb9d16287e00c17 (patch)
tree	ca5b1886650c6a15d773344029c49e26994382a6 /sys/dev/pci/if_em_hw.h
parent	b3b1b954b1ec77de5b3db7d74d2816b07cf30277 (diff)

Sync up to Intel's latest FreeBSD em driver (6.0.5). Adds support

for new chipset revisions embedded in the ESB2 and ICH8 core logic chipsets. From: Intel's web-site

Diffstat (limited to 'sys/dev/pci/if_em_hw.h')

-rw-r--r--

sys/dev/pci/if_em_hw.h

421

1 files changed, 391 insertions, 30 deletions

diff --git a/sys/dev/pci/if_em_hw.h b/sys/dev/pci/if_em_hw.h
index 3a12fdc86bc..d293bfe79b6 100644
--- a/sys/dev/pci/if_em_hw.h
+++ b/sys/dev/pci/if_em_hw.h

@@ -31,7 +31,7 @@ POSSIBILITY OF SUCH DAMAGE.

*******************************************************************************/

-/* $OpenBSD: if_em_hw.h,v 1.14 2006/04/19 07:17:49 brad Exp $ */

+/* $OpenBSD: if_em_hw.h,v 1.15 2006/07/03 20:55:55 brad Exp $ */

/* $FreeBSD: if_em_hw.h,v 1.15 2005/05/26 23:32:02 tackerman Exp $ */

/* if_em_hw.h

@@ -68,6 +68,7 @@ typedef enum {

em_82572,

em_82573,

em_80003es2lan,

+ em_ich8lan,

em_num_macs

} em_mac_type;

@@ -76,6 +77,7 @@ typedef enum {

em_eeprom_spi,

em_eeprom_microwire,

em_eeprom_flash,

+ em_eeprom_ich8,

em_eeprom_none, /* No NVM support */

em_num_eeprom_types

} em_eeprom_type;

@@ -104,6 +106,11 @@ typedef enum {

em_fc_default = 0xFF

} em_fc_type;

+struct em_shadow_ram {

+ uint16_t eeprom_word;

+ boolean_t modified;

+};

/* PCI bus types */

typedef enum {

em_bus_type_unknown = 0,

@@ -224,6 +231,8 @@ typedef enum {

em_phy_igp,

em_phy_igp_2,

em_phy_gg82563,

+ em_phy_igp_3,

+ em_phy_ife,

em_phy_undefined = 0xFF

} em_phy_type;

@@ -320,6 +329,11 @@ int32_t em_read_phy_reg(struct em_hw *hw, uint32_t reg_addr, uint16_t *phy_data)

int32_t em_write_phy_reg(struct em_hw *hw, uint32_t reg_addr, uint16_t data);

int32_t em_phy_hw_reset(struct em_hw *hw);

int32_t em_phy_reset(struct em_hw *hw);

+void em_phy_powerdown_workaround(struct em_hw *hw);

+int32_t em_kumeran_lock_loss_workaround(struct em_hw *hw);

+int32_t em_duplex_reversal(struct em_hw *hw);

+int32_t em_init_lcd_from_nvm_config_region(struct em_hw *hw, uint32_t cnf_base_addr, uint32_t cnf_size);

+int32_t em_init_lcd_from_nvm(struct em_hw *hw);

int32_t em_detect_gig_phy(struct em_hw *hw);

int32_t em_phy_get_info(struct em_hw *hw, struct em_phy_info *phy_info);

int32_t em_phy_m88_get_info(struct em_hw *hw, struct em_phy_info *phy_info);

@@ -330,7 +344,6 @@ int32_t em_check_downshift(struct em_hw *hw);

int32_t em_validate_mdi_setting(struct em_hw *hw);

int32_t em_read_kmrn_reg(struct em_hw *hw, uint32_t reg_addr, uint16_t *data);

int32_t em_write_kmrn_reg(struct em_hw *hw, uint32_t reg_addr, uint16_t data);

-int32_t em_duplex_reversal(struct em_hw *hw);

/* EEPROM Functions */

int32_t em_init_eeprom_params(struct em_hw *hw);

@@ -346,9 +359,10 @@ uint32_t em_enable_mng_pass_thru(struct em_hw *hw);

#define E1000_HI_MAX_MNG_DATA_LENGTH 0x6F8 /* Host Interface data length */

#define E1000_MNG_DHCP_COMMAND_TIMEOUT 10 /* Time in ms to process MNG command */

-#define E1000_MNG_DHCP_COOKIE_OFFSET 0x6F0 /* Cookie offset */

-#define E1000_MNG_DHCP_COOKIE_LENGTH 0x10 /* Cookie length */

-#define E1000_MNG_IAMT_MODE 0x3

+#define E1000_MNG_DHCP_COOKIE_OFFSET 0x6F0 /* Cookie offset */

+#define E1000_MNG_DHCP_COOKIE_LENGTH 0x10 /* Cookie length */

+#define E1000_MNG_IAMT_MODE 0x3

+#define E1000_MNG_ICH_IAMT_MODE 0x2

#define E1000_IAMT_SIGNATURE 0x544D4149 /* Intel(R) Active Management Technology signature */

#define E1000_MNG_DHCP_COOKIE_STATUS_PARSING_SUPPORT 0x1 /* DHCP parsing enabled */

@@ -380,15 +394,15 @@ struct em_host_mng_dhcp_cookie{

uint8_t checksum;

};

-int32_t em_mng_write_dhcp_info(struct em_hw *hw, uint8_t *buffer,

- uint16_t length);

+int32_t em_mng_write_dhcp_info(struct em_hw *hw, uint8_t *buffer,

+ uint16_t length);

boolean_t em_check_mng_mode(struct em_hw *hw);

boolean_t em_enable_tx_pkt_filtering(struct em_hw *hw);

int32_t em_mng_enable_host_if(struct em_hw *hw);

int32_t em_mng_host_if_write(struct em_hw *hw, uint8_t *buffer,

uint16_t length, uint16_t offset, uint8_t *sum);

-int32_t em_mng_write_cmd_header(struct em_hw* hw,

- struct em_host_mng_command_header* hdr);

+int32_t em_mng_write_cmd_header(struct em_hw *hw,

+ struct em_host_mng_command_header *hdr);

int32_t em_mng_write_commit(struct em_hw *hw);

@@ -397,16 +411,19 @@ int32_t em_validate_eeprom_checksum(struct em_hw *hw);

int32_t em_update_eeprom_checksum(struct em_hw *hw);

int32_t em_write_eeprom(struct em_hw *hw, uint16_t reg, uint16_t words, uint16_t *data);

int32_t em_read_part_num(struct em_hw *hw, uint32_t * part_num);

-int32_t em_read_mac_addr(struct em_hw * hw);

+int32_t em_read_mac_addr(struct em_hw *hw);

int32_t em_swfw_sync_acquire(struct em_hw *hw, uint16_t mask);

void em_swfw_sync_release(struct em_hw *hw, uint16_t mask);

+void em_release_software_flag(struct em_hw *hw);

+int32_t em_get_software_flag(struct em_hw *hw);

/* Filters (multicast, vlan, receive) */

void em_init_rx_addrs(struct em_hw *hw);

-void em_mc_addr_list_update(struct em_hw *hw, uint8_t * mc_addr_list, uint32_t mc_addr_count, uint32_t pad, uint32_t rar_used_count);

-uint32_t em_hash_mc_addr(struct em_hw *hw, uint8_t * mc_addr);

+void em_mc_addr_list_update(struct em_hw *hw, uint8_t *mc_addr_list, uint32_t mc_addr_count,

+ uint32_t pad, uint32_t rar_used_count);

+uint32_t em_hash_mc_addr(struct em_hw *hw, uint8_t *mc_addr);

void em_mta_set(struct em_hw *hw, uint32_t hash_value);

-void em_rar_set(struct em_hw *hw, uint8_t * mc_addr, uint32_t rar_index);

+void em_rar_set(struct em_hw *hw, uint8_t *mc_addr, uint32_t rar_index);

void em_write_vfta(struct em_hw *hw, uint32_t offset, uint32_t value);

void em_clear_vfta(struct em_hw *hw);

@@ -415,6 +432,7 @@ int32_t em_setup_led(struct em_hw *hw);

int32_t em_cleanup_led(struct em_hw *hw);

int32_t em_led_on(struct em_hw *hw);

int32_t em_led_off(struct em_hw *hw);

+int32_t em_blink_led_start(struct em_hw *hw);

/* Adaptive IFS Functions */

@@ -422,12 +440,12 @@ int32_t em_led_off(struct em_hw *hw);

void em_clear_hw_cntrs(struct em_hw *hw);

void em_reset_adaptive(struct em_hw *hw);

void em_update_adaptive(struct em_hw *hw);

-void em_tbi_adjust_stats(struct em_hw *hw, struct em_hw_stats *stats, uint32_t frame_len, uint8_t * mac_addr);

+void em_tbi_adjust_stats(struct em_hw *hw, struct em_hw_stats *stats, uint32_t frame_len, uint8_t *mac_addr);

void em_get_bus_info(struct em_hw *hw);

void em_pci_set_mwi(struct em_hw *hw);

void em_pci_clear_mwi(struct em_hw *hw);

-void em_read_pci_cfg(struct em_hw *hw, uint32_t reg, uint16_t * value);

-void em_write_pci_cfg(struct em_hw *hw, uint32_t reg, uint16_t * value);

+void em_read_pci_cfg(struct em_hw *hw, uint32_t reg, uint16_t *value);

+void em_write_pci_cfg(struct em_hw *hw, uint32_t reg, uint16_t *value);

/* Port I/O is only supported on 82544 and newer */

uint32_t em_read_reg_io(struct em_hw *hw, uint32_t offset);

void em_write_reg_io(struct em_hw *hw, uint32_t offset, uint32_t value);

@@ -448,6 +466,32 @@ int32_t em_commit_shadow_ram(struct em_hw *hw);

uint8_t em_arc_subsystem_valid(struct em_hw *hw);

int32_t em_set_pci_ex_no_snoop(struct em_hw *hw, uint32_t no_snoop);

+int32_t em_read_ich8_byte(struct em_hw *hw, uint32_t index,

+ uint8_t *data);

+int32_t em_verify_write_ich8_byte(struct em_hw *hw, uint32_t index,

+ uint8_t byte);

+int32_t em_write_ich8_byte(struct em_hw *hw, uint32_t index,

+ uint8_t byte);

+int32_t em_read_ich8_word(struct em_hw *hw, uint32_t index,

+ uint16_t *data);

+int32_t em_write_ich8_word(struct em_hw *hw, uint32_t index,

+ uint16_t word);

+int32_t em_read_ich8_data(struct em_hw *hw, uint32_t index,

+ uint32_t size, uint16_t *data);

+int32_t em_write_ich8_data(struct em_hw *hw, uint32_t index,

+ uint32_t size, uint16_t data);

+int32_t em_read_eeprom_ich8(struct em_hw *hw, uint16_t offset,

+ uint16_t words, uint16_t *data);

+int32_t em_write_eeprom_ich8(struct em_hw *hw, uint16_t offset,

+ uint16_t words, uint16_t *data);

+int32_t em_erase_ich8_4k_segment(struct em_hw *hw, uint32_t segment);

+int32_t em_ich8_cycle_init(struct em_hw *hw);

+int32_t em_ich8_flash_cycle(struct em_hw *hw, uint32_t timeout);

+int32_t em_phy_ife_get_info(struct em_hw *hw,

+ struct em_phy_info *phy_info);

+int32_t em_ife_disable_dynamic_power_down(struct em_hw *hw);

+int32_t em_ife_enable_dynamic_power_down(struct em_hw *hw);

#ifndef E1000_READ_REG_IO

#define E1000_READ_REG_IO(a, reg) \

em_read_reg_io((a), E1000_##reg)

@@ -464,7 +508,6 @@ int32_t em_set_pci_ex_no_snoop(struct em_hw *hw, uint32_t no_snoop);

#define E1000_DEV_ID_82544GC_COPPER 0x100C

#define E1000_DEV_ID_82544GC_LOM 0x100D

#define E1000_DEV_ID_82540EM 0x100E

-#define E1000_DEV_ID_82541ER_LOM 0x1014

#define E1000_DEV_ID_82540EM_LOM 0x1015

#define E1000_DEV_ID_82540EP_LOM 0x1016

#define E1000_DEV_ID_82540EP 0x1017

@@ -479,6 +522,7 @@ int32_t em_set_pci_ex_no_snoop(struct em_hw *hw, uint32_t no_snoop);

#define E1000_DEV_ID_82546EB_QUAD_COPPER 0x101D

#define E1000_DEV_ID_82541EI 0x1013

#define E1000_DEV_ID_82541EI_MOBILE 0x1018

+#define E1000_DEV_ID_82541ER_LOM 0x1014

#define E1000_DEV_ID_82541ER 0x1078

#define E1000_DEV_ID_82547GI 0x1075

#define E1000_DEV_ID_82541GI 0x1076

@@ -512,6 +556,14 @@ int32_t em_set_pci_ex_no_snoop(struct em_hw *hw, uint32_t no_snoop);

#define E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3 0x10B5

#define E1000_DEV_ID_80003ES2LAN_COPPER_DPT 0x1096

#define E1000_DEV_ID_80003ES2LAN_SERDES_DPT 0x1098

+#define E1000_DEV_ID_80003ES2LAN_COPPER_SPT 0x10BA

+#define E1000_DEV_ID_80003ES2LAN_SERDES_SPT 0x10BB

+#define E1000_DEV_ID_ICH8_IGP_M_AMT 0x1049

+#define E1000_DEV_ID_ICH8_IGP_AMT 0x104A

+#define E1000_DEV_ID_ICH8_IGP_C 0x104B

+#define E1000_DEV_ID_ICH8_IFE 0x104C

+#define E1000_DEV_ID_ICH8_IGP_M 0x104D

#define NODE_ADDRESS_SIZE 6

#define ETH_LENGTH_OF_ADDRESS 6

@@ -545,7 +597,7 @@ int32_t em_set_pci_ex_no_snoop(struct em_hw *hw, uint32_t no_snoop);

#define MAX_JUMBO_FRAME_SIZE 0x3F00

/* 802.1q VLAN Packet Sizes */

-#define VLAN_TAG_SIZE 4 /* 802.3ac tag (not DMAed) */

+#define VLAN_TAG_SIZE 4 /* 802.3ac tag (not DMAed) */

/* Ethertype field values */

#define ETHERNET_IEEE_VLAN_TYPE 0x8100 /* 802.3ac packet */

@@ -571,6 +623,7 @@ int32_t em_set_pci_ex_no_snoop(struct em_hw *hw, uint32_t no_snoop);

* o TXDW = Transmit Descriptor Written Back

* o RXDMT0 = Receive Descriptor Minimum Threshold hit (ring 0)

* o RXSEQ = Receive Sequence Error

+ * o RXO = Receive Overrun

* o LSC = Link Status Change

#define IMS_ENABLE_MASK ( \

@@ -581,12 +634,22 @@ int32_t em_set_pci_ex_no_snoop(struct em_hw *hw, uint32_t no_snoop);

E1000_IMS_RXO | \

E1000_IMS_LSC)

+/* Additional interrupts need to be handled for em_ich8lan:

+ DSW = The FW changed the status of the DISSW bit in FWSM

+ PHYINT = The LAN connected device generates an interrupt

+ EPRST = Manageability reset event */

+#define IMS_ICH8LAN_ENABLE_MASK (\

+ E1000_IMS_DSW | \

+ E1000_IMS_PHYINT | \

+ E1000_IMS_EPRST)

/* Number of high/low register pairs in the RAR. The RAR (Receive Address

* Registers) holds the directed and multicast addresses that we monitor. We

* reserve one of these spots for our directed address, allowing us room for

* E1000_RAR_ENTRIES - 1 multicast addresses.

#define E1000_RAR_ENTRIES 15

+#define E1000_RAR_ENTRIES_ICH8LAN 7

#define MIN_NUMBER_OF_DESCRIPTORS 8

#define MAX_NUMBER_OF_DESCRIPTORS 0xFFF8

@@ -807,6 +870,9 @@ struct em_data_desc {

#define E1000_MC_TBL_SIZE 128 /* Multicast Filter Table (4096 bits) */

#define E1000_VLAN_FILTER_TBL_SIZE 128 /* VLAN Filter Table (4096 bits) */

+#define E1000_NUM_UNICAST_ICH8LAN 7

+#define E1000_MC_TBL_SIZE_ICH8LAN 32

/* Receive Address Register */

struct em_rar {

volatile uint32_t low; /* receive address low */

@@ -815,6 +881,7 @@ struct em_rar {

/* Number of entries in the Multicast Table Array (MTA). */

#define E1000_NUM_MTA_REGISTERS 128

+#define E1000_NUM_MTA_REGISTERS_ICH8LAN 32

/* IPv4 Address Table Entry */

struct em_ipv4_at_entry {

@@ -825,6 +892,7 @@ struct em_ipv4_at_entry {

/* Four wakeup IP addresses are supported */

#define E1000_WAKEUP_IP_ADDRESS_COUNT_MAX 4

#define E1000_IP4AT_SIZE E1000_WAKEUP_IP_ADDRESS_COUNT_MAX

+#define E1000_IP4AT_SIZE_ICH8LAN 3

#define E1000_IP6AT_SIZE 1

/* IPv6 Address Table Entry */

@@ -883,6 +951,7 @@ struct em_ffvt_entry {

#define E1000_FLA 0x0001C /* Flash Access - RW */

#define E1000_MDIC 0x00020 /* MDI Control - RW */

#define E1000_SCTL 0x00024 /* SerDes Control - RW */

+#define E1000_FEXTNVM 0x00028 /* Future Extended NVM register */

#define E1000_FCAL 0x00028 /* Flow Control Address Low - RW */

#define E1000_FCAH 0x0002C /* Flow Control Address High -RW */

#define E1000_FCT 0x00030 /* Flow Control Type - RW */

@@ -911,6 +980,8 @@ struct em_ffvt_entry {

#define E1000_LEDCTL 0x00E00 /* LED Control - RW */

#define E1000_EXTCNF_CTRL 0x00F00 /* Extended Configuration Control */

#define E1000_EXTCNF_SIZE 0x00F08 /* Extended Configuration Size */

+#define E1000_PHY_CTRL 0x00F10 /* PHY Control Register in CSR */

+#define FEXTNVM_SW_CONFIG 0x0001

#define E1000_PBA 0x01000 /* Packet Buffer Allocation - RW */

#define E1000_PBS 0x01008 /* Packet Buffer Size */

#define E1000_EEMNGCTL 0x01010 /* MNG EEprom Control */

@@ -938,11 +1009,13 @@ struct em_ffvt_entry {

#define E1000_RDH0 E1000_RDH /* RX Desc Head (0) - RW */

#define E1000_RDT0 E1000_RDT /* RX Desc Tail (0) - RW */

#define E1000_RDTR0 E1000_RDTR /* RX Delay Timer (0) - RW */

-#define E1000_RXDCTL 0x02828 /* RX Descriptor Control - RW */

+#define E1000_RXDCTL 0x02828 /* RX Descriptor Control queue 0 - RW */

+#define E1000_RXDCTL1 0x02928 /* RX Descriptor Control queue 1 - RW */

#define E1000_RADV 0x0282C /* RX Interrupt Absolute Delay Timer - RW */

#define E1000_RSRPD 0x02C00 /* RX Small Packet Detect - RW */

#define E1000_RAID 0x02C08 /* Receive Ack Interrupt Delay - RW */

#define E1000_TXDMAC 0x03000 /* TX DMA Control - RW */

+#define E1000_KABGTXD 0x03004 /* AFE Band Gap Transmit Ref Data */

#define E1000_TDFH 0x03410 /* TX Data FIFO Head - RW */

#define E1000_TDFT 0x03418 /* TX Data FIFO Tail - RW */

#define E1000_TDFHS 0x03420 /* TX Data FIFO Head Saved - RW */

@@ -1089,6 +1162,7 @@ struct em_ffvt_entry {

#define E1000_82542_FLA E1000_FLA

#define E1000_82542_MDIC E1000_MDIC

#define E1000_82542_SCTL E1000_SCTL

+#define E1000_82542_FEXTNVM E1000_FEXTNVM

#define E1000_82542_FCAL E1000_FCAL

#define E1000_82542_FCAH E1000_FCAH

#define E1000_82542_FCT E1000_FCT

@@ -1112,6 +1186,19 @@ struct em_ffvt_entry {

#define E1000_82542_RDLEN0 E1000_82542_RDLEN

#define E1000_82542_RDH0 E1000_82542_RDH

#define E1000_82542_RDT0 E1000_82542_RDT

+#define E1000_82542_SRRCTL(_n) (0x280C + ((_n) << 8)) /* Split and Replication

+ * RX Control - RW */

+#define E1000_82542_DCA_RXCTRL(_n) (0x02814 + ((_n) << 8))

+#define E1000_82542_RDBAH3 0x02B04 /* RX Desc Base High Queue 3 - RW */

+#define E1000_82542_RDBAL3 0x02B00 /* RX Desc Low Queue 3 - RW */

+#define E1000_82542_RDLEN3 0x02B08 /* RX Desc Length Queue 3 - RW */

+#define E1000_82542_RDH3 0x02B10 /* RX Desc Head Queue 3 - RW */

+#define E1000_82542_RDT3 0x02B18 /* RX Desc Tail Queue 3 - RW */

+#define E1000_82542_RDBAL2 0x02A00 /* RX Desc Base Low Queue 2 - RW */

+#define E1000_82542_RDBAH2 0x02A04 /* RX Desc Base High Queue 2 - RW */

+#define E1000_82542_RDLEN2 0x02A08 /* RX Desc Length Queue 2 - RW */

+#define E1000_82542_RDH2 0x02A10 /* RX Desc Head Queue 2 - RW */

+#define E1000_82542_RDT2 0x02A18 /* RX Desc Tail Queue 2 - RW */

#define E1000_82542_RDTR1 0x00130

#define E1000_82542_RDBAL1 0x00138

#define E1000_82542_RDBAH1 0x0013C

@@ -1149,11 +1236,14 @@ struct em_ffvt_entry {

#define E1000_82542_FLOP E1000_FLOP

#define E1000_82542_EXTCNF_CTRL E1000_EXTCNF_CTRL

#define E1000_82542_EXTCNF_SIZE E1000_EXTCNF_SIZE

+#define E1000_82542_PHY_CTRL E1000_PHY_CTRL

#define E1000_82542_ERT E1000_ERT

#define E1000_82542_RXDCTL E1000_RXDCTL

+#define E1000_82542_RXDCTL1 E1000_RXDCTL1

#define E1000_82542_RADV E1000_RADV

#define E1000_82542_RSRPD E1000_RSRPD

#define E1000_82542_TXDMAC E1000_TXDMAC

+#define E1000_82542_KABGTXD E1000_KABGTXD

#define E1000_82542_TDFHS E1000_TDFHS

#define E1000_82542_TDFTS E1000_TDFTS

#define E1000_82542_TDFPC E1000_TDFPC

@@ -1356,6 +1446,9 @@ struct em_hw {

uint32_t phy_init_script;

em_media_type media_type;

void *back;

+ struct em_shadow_ram *eeprom_shadow_ram;

+ uint32_t flash_bank_size;

+ uint32_t flash_base_addr;

em_fc_type fc;

em_bus_speed bus_speed;

em_bus_width bus_width;

@@ -1367,6 +1460,7 @@ struct em_hw {

uint32_t asf_firmware_present;

uint32_t eeprom_semaphore_present;

uint32_t swfw_sync_present;

+ uint32_t swfwhw_semaphore_present;

unsigned long io_base;

uint32_t phy_id;

uint32_t phy_revision;

@@ -1426,6 +1520,7 @@ struct em_hw {

boolean_t in_ifs_mode;

boolean_t mng_reg_access_disabled;

boolean_t leave_av_bit_off;

+ boolean_t kmrn_lock_loss_workaround_disabled;

};

#define E1000_EEPROM_SWDPIN0 0x0001 /* SWDPIN 0 EEPROM Value */

@@ -1473,6 +1568,7 @@ struct em_hw {

#define E1000_CTRL_RTE 0x20000000 /* Routing tag enable */

#define E1000_CTRL_VME 0x40000000 /* IEEE VLAN mode enable */

#define E1000_CTRL_PHY_RST 0x80000000 /* PHY Reset */

+#define E1000_CTRL_SW2FW_INT 0x02000000 /* Initiate an interrupt to manageability engine */

/* Device Status */

#define E1000_STATUS_FD 0x00000001 /* Full duplex.0=half,1=full */

@@ -1487,6 +1583,8 @@ struct em_hw {

#define E1000_STATUS_SPEED_10 0x00000000 /* Speed 10Mb/s */

#define E1000_STATUS_SPEED_100 0x00000040 /* Speed 100Mb/s */

#define E1000_STATUS_SPEED_1000 0x00000080 /* Speed 1000Mb/s */

+#define E1000_STATUS_LAN_INIT_DONE 0x00000200 /* Lan Init Completion

+ by EEPROM/Flash */

#define E1000_STATUS_ASDV 0x00000300 /* Auto speed detect value */

#define E1000_STATUS_DOCK_CI 0x00000800 /* Change in Dock/Undock state. Clear on write '0'. */

#define E1000_STATUS_GIO_MASTER_ENABLE 0x00080000 /* Status of Master requests. */

@@ -1544,6 +1642,10 @@ struct em_hw {

#define E1000_STM_OPCODE 0xDB00

#define E1000_HICR_FW_RESET 0xC0

+#define E1000_SHADOW_RAM_WORDS 2048

+#define E1000_ICH8_NVM_SIG_WORD 0x13

+#define E1000_ICH8_NVM_SIG_MASK 0xC0

/* EEPROM Read */

#define E1000_EERD_START 0x00000001 /* Start Read */

#define E1000_EERD_DONE 0x00000010 /* Read Done */

@@ -1589,7 +1691,6 @@ struct em_hw {

#define E1000_CTRL_EXT_WR_WMARK_320 0x01000000

#define E1000_CTRL_EXT_WR_WMARK_384 0x02000000

#define E1000_CTRL_EXT_WR_WMARK_448 0x03000000

-#define E1000_CTRL_EXT_CANC 0x04000000 /* Interrupt delay cancellation */

#define E1000_CTRL_EXT_DRV_LOAD 0x10000000 /* Driver loaded bit for FW */

#define E1000_CTRL_EXT_IAME 0x08000000 /* Interrupt acknowledge Auto-mask */

#define E1000_CTRL_EXT_INT_TIMER_CLR 0x20000000 /* Clear Interrupt timers after IMS clear */

@@ -1629,12 +1730,31 @@ struct em_hw {

#define E1000_KUMCTRLSTA_FIFO_CTRL_TX_BYPASS 0x00000800

/* In-Band Control */

+#define E1000_KUMCTRLSTA_INB_CTRL_LINK_STATUS_TX_TIMEOUT_DEFAULT 0x00000500

#define E1000_KUMCTRLSTA_INB_CTRL_DIS_PADDING 0x00000010

/* Half-Duplex Control */

#define E1000_KUMCTRLSTA_HD_CTRL_10_100_DEFAULT 0x00000004

#define E1000_KUMCTRLSTA_HD_CTRL_1000_DEFAULT 0x00000000

+#define E1000_KUMCTRLSTA_OFFSET_K0S_CTRL 0x0000001E

+#define E1000_KUMCTRLSTA_DIAG_FELPBK 0x2000

+#define E1000_KUMCTRLSTA_DIAG_NELPBK 0x1000

+#define E1000_KUMCTRLSTA_K0S_100_EN 0x2000

+#define E1000_KUMCTRLSTA_K0S_GBE_EN 0x1000

+#define E1000_KUMCTRLSTA_K0S_ENTRY_LATENCY_MASK 0x0003

+#define E1000_KABGTXD_BGSQLBIAS 0x00050000

+#define E1000_PHY_CTRL_SPD_EN 0x00000001

+#define E1000_PHY_CTRL_D0A_LPLU 0x00000002

+#define E1000_PHY_CTRL_NOND0A_LPLU 0x00000004

+#define E1000_PHY_CTRL_NOND0A_GBE_DISABLE 0x00000008

+#define E1000_PHY_CTRL_GBE_DISABLE 0x00000040

+#define E1000_PHY_CTRL_B2B_EN 0x00000080

/* LED Control */

#define E1000_LEDCTL_LED0_MODE_MASK 0x0000000F

#define E1000_LEDCTL_LED0_MODE_SHIFT 0

@@ -1704,6 +1824,9 @@ struct em_hw {

#define E1000_ICR_RXD_FIFO_PAR1 0x01000000 /* queue 1 Rx descriptor FIFO parity error */

#define E1000_ICR_TXD_FIFO_PAR1 0x02000000 /* queue 1 Tx descriptor FIFO parity error */

#define E1000_ICR_ALL_PARITY 0x03F00000 /* all parity error bits */

+#define E1000_ICR_DSW 0x00000020 /* FW changed the status of DISSW bit in the FWSM */

+#define E1000_ICR_PHYINT 0x00001000 /* LAN connected device generates an interrupt */

+#define E1000_ICR_EPRST 0x00100000 /* ME handware reset occurs */

/* Interrupt Cause Set */

#define E1000_ICS_TXDW E1000_ICR_TXDW /* Transmit desc written back */

@@ -1730,6 +1853,9 @@ struct em_hw {

#define E1000_ICS_PB_PAR E1000_ICR_PB_PAR /* packet buffer parity error */

#define E1000_ICS_RXD_FIFO_PAR1 E1000_ICR_RXD_FIFO_PAR1 /* queue 1 Rx descriptor FIFO parity error */

#define E1000_ICS_TXD_FIFO_PAR1 E1000_ICR_TXD_FIFO_PAR1 /* queue 1 Tx descriptor FIFO parity error */

+#define E1000_ICS_DSW E1000_ICR_DSW

+#define E1000_ICS_PHYINT E1000_ICR_PHYINT

+#define E1000_ICS_EPRST E1000_ICR_EPRST

/* Interrupt Mask Set */

#define E1000_IMS_TXDW E1000_ICR_TXDW /* Transmit desc written back */

@@ -1756,6 +1882,9 @@ struct em_hw {

#define E1000_IMS_PB_PAR E1000_ICR_PB_PAR /* packet buffer parity error */

#define E1000_IMS_RXD_FIFO_PAR1 E1000_ICR_RXD_FIFO_PAR1 /* queue 1 Rx descriptor FIFO parity error */

#define E1000_IMS_TXD_FIFO_PAR1 E1000_ICR_TXD_FIFO_PAR1 /* queue 1 Tx descriptor FIFO parity error */

+#define E1000_IMS_DSW E1000_ICR_DSW

+#define E1000_IMS_PHYINT E1000_ICR_PHYINT

+#define E1000_IMS_EPRST E1000_ICR_EPRST

/* Interrupt Mask Clear */

#define E1000_IMC_TXDW E1000_ICR_TXDW /* Transmit desc written back */

@@ -1782,6 +1911,9 @@ struct em_hw {

#define E1000_IMC_PB_PAR E1000_ICR_PB_PAR /* packet buffer parity error */

#define E1000_IMC_RXD_FIFO_PAR1 E1000_ICR_RXD_FIFO_PAR1 /* queue 1 Rx descriptor FIFO parity error */

#define E1000_IMC_TXD_FIFO_PAR1 E1000_ICR_TXD_FIFO_PAR1 /* queue 1 Tx descriptor FIFO parity error */

+#define E1000_IMC_DSW E1000_ICR_DSW

+#define E1000_IMC_PHYINT E1000_ICR_PHYINT

+#define E1000_IMC_EPRST E1000_ICR_EPRST

/* Receive Control */

#define E1000_RCTL_RST 0x00000001 /* Software reset */

@@ -1840,7 +1972,7 @@ struct em_hw {

* value2 = [0..64512], default=4096

* value3 = [0..64512], default=0

#define E1000_PSRCTL_BSIZE0_MASK 0x0000007F

#define E1000_PSRCTL_BSIZE1_MASK 0x00003F00

#define E1000_PSRCTL_BSIZE2_MASK 0x003F0000

@@ -1956,9 +2088,10 @@ struct em_hw {

#define E1000_MRQC_RSS_FIELD_MASK 0xFFFF0000

#define E1000_MRQC_RSS_FIELD_IPV4_TCP 0x00010000

#define E1000_MRQC_RSS_FIELD_IPV4 0x00020000

-#define E1000_MRQC_RSS_FIELD_IPV6_TCP 0x00040000

+#define E1000_MRQC_RSS_FIELD_IPV6_TCP_EX 0x00040000

#define E1000_MRQC_RSS_FIELD_IPV6_EX 0x00080000

#define E1000_MRQC_RSS_FIELD_IPV6 0x00100000

+#define E1000_MRQC_RSS_FIELD_IPV6_TCP 0x00200000

/* Definitions for power management and wakeup registers */

/* Wake Up Control */

@@ -2026,7 +2159,7 @@ struct em_hw {

#define E1000_MANC_EN_IP_ADDR_FILTER 0x00400000 /* Enable IP address

* filtering */

#define E1000_MANC_EN_XSUM_FILTER 0x00800000 /* Enable checksum filtering */

-#define E1000_MANC_BR_EN 0x01000000 /* Enable broadcast filtering */

+#define E1000_MANC_BR_EN 0x01000000 /* Enable broadcast filtering */

#define E1000_MANC_SMB_REQ 0x01000000 /* SMBus Request */

#define E1000_MANC_SMB_GNT 0x02000000 /* SMBus Grant */

#define E1000_MANC_SMB_CLK_IN 0x04000000 /* SMBus Clock In */

@@ -2048,6 +2181,15 @@ struct em_hw {

#define E1000_FWSM_MODE_SHIFT 1

#define E1000_FWSM_FW_VALID 0x00008000 /* FW established a valid mode */

+#define E1000_FWSM_RSPCIPHY 0x00000040 /* Reset PHY on PCI reset */

+#define E1000_FWSM_DISSW 0x10000000 /* FW disable SW Write Access */

+#define E1000_FWSM_SKUSEL_MASK 0x60000000 /* LAN SKU select */

+#define E1000_FWSM_SKUEL_SHIFT 29

+#define E1000_FWSM_SKUSEL_EMB 0x0 /* Embedded SKU */

+#define E1000_FWSM_SKUSEL_CONS 0x1 /* Consumer SKU */

+#define E1000_FWSM_SKUSEL_PERF_100 0x2 /* Perf & Corp 10/100 SKU */

+#define E1000_FWSM_SKUSEL_PERF_GBE 0x3 /* Perf & Copr GbE SKU */

/* FFLT Debug Register */

#define E1000_FFLT_DBG_INVC 0x00100000 /* Invalid /C/ code handling */

@@ -2120,6 +2262,8 @@ struct em_host_command_info {

E1000_GCR_TXDSCW_NO_SNOOP | \

E1000_GCR_TXDSCR_NO_SNOOP)

+#define PCI_EX_82566_SNOOP_ALL PCI_EX_NO_SNOOP_ALL

#define E1000_GCR_L1_ACT_WITHOUT_L0S_RX 0x08000000

/* Function Active and Power State to MNG */

#define E1000_FACTPS_FUNC0_POWER_STATE_MASK 0x00000003

@@ -2153,7 +2297,7 @@ struct em_host_command_info {

#define EEPROM_EWDS_OPCODE_MICROWIRE 0x10 /* EEPROM erast/write disable */

/* EEPROM Commands - SPI */

-#define EEPROM_MAX_RETRY_SPI 5000 /* Max wait of 5ms, for RDY signal */

+#define EEPROM_MAX_RETRY_SPI 5000 /* Max wait of 5ms, for RDY signal */

#define EEPROM_READ_OPCODE_SPI 0x03 /* EEPROM read opcode */

#define EEPROM_WRITE_OPCODE_SPI 0x02 /* EEPROM write opcode */

#define EEPROM_A8_OPCODE_SPI 0x08 /* opcode bit-3 = address bit-8 */

@@ -2178,8 +2322,10 @@ struct em_host_command_info {

#define EEPROM_PHY_CLASS_WORD 0x0007

#define EEPROM_INIT_CONTROL1_REG 0x000A

#define EEPROM_INIT_CONTROL2_REG 0x000F

+#define EEPROM_SWDEF_PINS_CTRL_PORT_1 0x0010

#define EEPROM_INIT_CONTROL3_PORT_B 0x0014

#define EEPROM_INIT_3GIO_3 0x001A

+#define EEPROM_SWDEF_PINS_CTRL_PORT_0 0x0020

#define EEPROM_INIT_CONTROL3_PORT_A 0x0024

#define EEPROM_CFG 0x0012

#define EEPROM_FLASH_VERSION 0x0032

@@ -2191,10 +2337,16 @@ struct em_host_command_info {

/* Word definitions for ID LED Settings */

#define ID_LED_RESERVED_0000 0x0000

#define ID_LED_RESERVED_FFFF 0xFFFF

+#define ID_LED_RESERVED_82573 0xF746

+#define ID_LED_DEFAULT_82573 0x1811

#define ID_LED_DEFAULT ((ID_LED_OFF1_ON2 << 12) | \

(ID_LED_OFF1_OFF2 << 8) | \

(ID_LED_DEF1_DEF2 << 4) | \

(ID_LED_DEF1_DEF2))

+#define ID_LED_DEFAULT_ICH8LAN ((ID_LED_DEF1_DEF2 << 12) | \

+ (ID_LED_DEF1_OFF2 << 8) | \

+ (ID_LED_DEF1_ON2 << 4) | \

+ (ID_LED_DEF1_DEF2))

#define ID_LED_DEF1_DEF2 0x1

#define ID_LED_DEF1_ON2 0x2

#define ID_LED_DEF1_OFF2 0x3

@@ -2228,6 +2380,11 @@ struct em_host_command_info {

#define EEPROM_WORD0F_ASM_DIR 0x2000

#define EEPROM_WORD0F_ANE 0x0800

#define EEPROM_WORD0F_SWPDIO_EXT 0x00F0

+#define EEPROM_WORD0F_LPLU 0x0001

+/* Mask bits for fields in Word 0x10/0x20 of the EEPROM */

+#define EEPROM_WORD1020_GIGA_DISABLE 0x0010

+#define EEPROM_WORD1020_GIGA_DISABLE_NON_D0A 0x0008

/* Mask bits for fields in Word 0x1a of the EEPROM */

#define EEPROM_WORD1A_ASPM_MASK 0x000C

@@ -2302,23 +2459,29 @@ struct em_host_command_info {

#define E1000_EXTCNF_CTRL_D_UD_OWNER 0x00000010

#define E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP 0x00000020

#define E1000_EXTCNF_CTRL_MDIO_HW_OWNERSHIP 0x00000040

-#define E1000_EXTCNF_CTRL_EXT_CNF_POINTER 0x1FFF0000

+#define E1000_EXTCNF_CTRL_EXT_CNF_POINTER 0x0FFF0000

#define E1000_EXTCNF_SIZE_EXT_PHY_LENGTH 0x000000FF

#define E1000_EXTCNF_SIZE_EXT_DOCK_LENGTH 0x0000FF00

#define E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH 0x00FF0000

+#define E1000_EXTCNF_CTRL_LCD_WRITE_ENABLE 0x00000001

+#define E1000_EXTCNF_CTRL_SWFLAG 0x00000020

/* PBA constants */

+#define E1000_PBA_8K 0x0008 /* 8KB, default Rx allocation */

#define E1000_PBA_12K 0x000C /* 12KB, default Rx allocation */

#define E1000_PBA_16K 0x0010 /* 16KB, default TX allocation */

#define E1000_PBA_22K 0x0016

#define E1000_PBA_24K 0x0018

#define E1000_PBA_30K 0x001E

#define E1000_PBA_32K 0x0020

+#define E1000_PBA_34K 0x0022

#define E1000_PBA_38K 0x0026

#define E1000_PBA_40K 0x0028

#define E1000_PBA_48K 0x0030 /* 48KB, default RX allocation */

+#define E1000_PBS_16K E1000_PBA_16K

/* Flow Control Constants */

#define FLOW_CONTROL_ADDRESS_LOW 0x00C28001

#define FLOW_CONTROL_ADDRESS_HIGH 0x00000100

@@ -2371,7 +2534,7 @@ struct em_host_command_info {

/* Number of milliseconds we wait for Eeprom auto read bit done after MAC reset */

#define AUTO_READ_DONE_TIMEOUT 10

/* Number of milliseconds we wait for PHY configuration done after MAC reset */

-#define PHY_CFG_TIMEOUT 40

+#define PHY_CFG_TIMEOUT 100

#define E1000_TX_BUFFER_SIZE ((uint32_t)1514)

@@ -2798,6 +2961,17 @@ struct em_host_command_info {

#define M88E1000_EPSCR_TX_CLK_25 0x0070 /* 25 MHz TX_CLK */

#define M88E1000_EPSCR_TX_CLK_0 0x0000 /* NO TX_CLK */

+/* M88EC018 Rev 2 specific DownShift settings */

+#define M88EC018_EPSCR_DOWNSHIFT_COUNTER_MASK 0x0E00

+#define M88EC018_EPSCR_DOWNSHIFT_COUNTER_1X 0x0000

+#define M88EC018_EPSCR_DOWNSHIFT_COUNTER_2X 0x0200

+#define M88EC018_EPSCR_DOWNSHIFT_COUNTER_3X 0x0400

+#define M88EC018_EPSCR_DOWNSHIFT_COUNTER_4X 0x0600

+#define M88EC018_EPSCR_DOWNSHIFT_COUNTER_5X 0x0800

+#define M88EC018_EPSCR_DOWNSHIFT_COUNTER_6X 0x0A00

+#define M88EC018_EPSCR_DOWNSHIFT_COUNTER_7X 0x0C00

+#define M88EC018_EPSCR_DOWNSHIFT_COUNTER_8X 0x0E00

/* IGP01E1000 Specific Port Config Register - R/W */

#define IGP01E1000_PSCFR_AUTO_MDIX_PAR_DETECT 0x0010

#define IGP01E1000_PSCFR_PRE_EN 0x0020

@@ -2977,10 +3151,10 @@ struct em_host_command_info {

/* DSP Distance Register (Page 5, Register 26) */

#define GG82563_DSPD_CABLE_LENGTH 0x0007 /* 0 = <50M;

- 1 = 50-80M;

- 2 = 80-110M;

- 3 = 110-140M;

- 4 = >140M */

+ 1 = 50-80M;

+ 2 = 80-110M;

+ 3 = 110-140M;

+ 4 = >140M */

/* Kumeran Mode Control Register (Page 193, Register 16) */

#define GG82563_KMCR_PHY_LEDS_EN 0x0020 /* 1=PHY LEDs, 0=Kumeran Inband LEDs */

@@ -3023,6 +3197,193 @@ struct em_host_command_info {

#define L1LXT971A_PHY_ID 0x001378E0

#define GG82563_E_PHY_ID 0x01410CA0

+/* Bits...

+ * 15-5: page

+ * 4-0: register offset

+ */

+#define PHY_PAGE_SHIFT 5

+#define PHY_REG(page, reg) \

+ (((page) << PHY_PAGE_SHIFT) | ((reg) & MAX_PHY_REG_ADDRESS))

+#define IGP3_PHY_PORT_CTRL \

+ PHY_REG(769, 17) /* Port General Configuration */

+#define IGP3_PHY_RATE_ADAPT_CTRL \

+ PHY_REG(769, 25) /* Rate Adapter Control Register */

+#define IGP3_KMRN_FIFO_CTRL_STATS \

+ PHY_REG(770, 16) /* KMRN FIFO's control/status register */

+#define IGP3_KMRN_POWER_MNG_CTRL \

+ PHY_REG(770, 17) /* KMRN Power Management Control Register */

+#define IGP3_KMRN_INBAND_CTRL \

+ PHY_REG(770, 18) /* KMRN Inband Control Register */

+#define IGP3_KMRN_DIAG \

+ PHY_REG(770, 19) /* KMRN Diagnostic register */

+#define IGP3_KMRN_DIAG_PCS_LOCK_LOSS 0x0002 /* RX PCS is not synced */

+#define IGP3_KMRN_ACK_TIMEOUT \

+ PHY_REG(770, 20) /* KMRN Acknowledge Timeouts register */

+#define IGP3_VR_CTRL \

+ PHY_REG(776, 18) /* Voltage regulator control register */

+#define IGP3_VR_CTRL_MODE_SHUT 0x0200 /* Enter powerdown, shutdown VRs */

+#define IGP3_CAPABILITY \

+ PHY_REG(776, 19) /* IGP3 Capability Register */

+/* Capabilities for SKU Control */

+#define IGP3_CAP_INITIATE_TEAM 0x0001 /* Able to initiate a team */

+#define IGP3_CAP_WFM 0x0002 /* Support WoL and PXE */

+#define IGP3_CAP_ASF 0x0004 /* Support ASF */

+#define IGP3_CAP_LPLU 0x0008 /* Support Low Power Link Up */

+#define IGP3_CAP_DC_AUTO_SPEED 0x0010 /* Support AC/DC Auto Link Speed */

+#define IGP3_CAP_SPD 0x0020 /* Support Smart Power Down */

+#define IGP3_CAP_MULT_QUEUE 0x0040 /* Support 2 tx & 2 rx queues */

+#define IGP3_CAP_RSS 0x0080 /* Support RSS */

+#define IGP3_CAP_8021PQ 0x0100 /* Support 802.1Q & 802.1p */

+#define IGP3_CAP_AMT_CB 0x0200 /* Support active manageability and circuit breaker */

+#define IGP3_PPC_JORDAN_EN 0x0001

+#define IGP3_PPC_JORDAN_GIGA_SPEED 0x0002

+#define IGP3_KMRN_PMC_EE_IDLE_LINK_DIS 0x0001

+#define IGP3_KMRN_PMC_K0S_ENTRY_LATENCY_MASK 0x001E

+#define IGP3_KMRN_PMC_K0S_MODE1_EN_GIGA 0x0020

+#define IGP3_KMRN_PMC_K0S_MODE1_EN_100 0x0040

+#define IGP3E1000_PHY_MISC_CTRL 0x1B /* Misc. Ctrl register */

+#define IGP3_PHY_MISC_DUPLEX_MANUAL_SET 0x1000 /* Duplex Manual Set */

+#define IGP3_KMRN_EXT_CTRL PHY_REG(770, 18)

+#define IGP3_KMRN_EC_DIS_INBAND 0x0080

+#define IGP03E1000_E_PHY_ID 0x02A80390

+#define IFE_E_PHY_ID 0x02A80330 /* 10/100 PHY */

+#define IFE_PLUS_E_PHY_ID 0x02A80320

+#define IFE_C_E_PHY_ID 0x02A80310

+#define IFE_PHY_EXTENDED_STATUS_CONTROL 0x10 /* 100BaseTx Extended Status, Control and Address */

+#define IFE_PHY_SPECIAL_CONTROL 0x11 /* 100BaseTx PHY special control register */

+#define IFE_PHY_RCV_FALSE_CARRIER 0x13 /* 100BaseTx Receive False Carrier Counter */

+#define IFE_PHY_RCV_DISCONNECT 0x14 /* 100BaseTx Receive Disconnet Counter */

+#define IFE_PHY_RCV_ERROT_FRAME 0x15 /* 100BaseTx Receive Error Frame Counter */

+#define IFE_PHY_RCV_SYMBOL_ERR 0x16 /* Receive Symbol Error Counter */

+#define IFE_PHY_PREM_EOF_ERR 0x17 /* 100BaseTx Receive Premature End Of Frame Error Counter */

+#define IFE_PHY_RCV_EOF_ERR 0x18 /* 10BaseT Receive End Of Frame Error Counter */

+#define IFE_PHY_TX_JABBER_DETECT 0x19 /* 10BaseT Transmit Jabber Detect Counter */

+#define IFE_PHY_EQUALIZER 0x1A /* PHY Equalizer Control and Status */

+#define IFE_PHY_SPECIAL_CONTROL_LED 0x1B /* PHY special control and LED configuration */

+#define IFE_PHY_MDIX_CONTROL 0x1C /* MDI/MDI-X Control register */

+#define IFE_PHY_HWI_CONTROL 0x1D /* Hardware Integrity Control (HWI) */

+#define IFE_PESC_REDUCED_POWER_DOWN_DISABLE 0x2000 /* Defaut 1 = Disable auto reduced power down */

+#define IFE_PESC_100BTX_POWER_DOWN 0x0400 /* Indicates the power state of 100BASE-TX */

+#define IFE_PESC_10BTX_POWER_DOWN 0x0200 /* Indicates the power state of 10BASE-T */

+#define IFE_PESC_POLARITY_REVERSED 0x0100 /* Indicates 10BASE-T polarity */

+#define IFE_PESC_PHY_ADDR_MASK 0x007C /* Bit 6:2 for sampled PHY address */

+#define IFE_PESC_SPEED 0x0002 /* Auto-negotiation speed result 1=100Mbs, 0=10Mbs */

+#define IFE_PESC_DUPLEX 0x0001 /* Auto-negotiation duplex result 1=Full, 0=Half */

+#define IFE_PESC_POLARITY_REVERSED_SHIFT 8

+#define IFE_PSC_DISABLE_DYNAMIC_POWER_DOWN 0x0100 /* 1 = Dyanmic Power Down disabled */

+#define IFE_PSC_FORCE_POLARITY 0x0020 /* 1=Reversed Polarity, 0=Normal */

+#define IFE_PSC_AUTO_POLARITY_DISABLE 0x0010 /* 1=Auto Polarity Disabled, 0=Enabled */

+#define IFE_PSC_JABBER_FUNC_DISABLE 0x0001 /* 1=Jabber Disabled, 0=Normal Jabber Operation */

+#define IFE_PSC_FORCE_POLARITY_SHIFT 5

+#define IFE_PSC_AUTO_POLARITY_DISABLE_SHIFT 4

+#define IFE_PMC_AUTO_MDIX 0x0080 /* 1=enable MDI/MDI-X feature, default 0=disabled */

+#define IFE_PMC_FORCE_MDIX 0x0040 /* 1=force MDIX-X, 0=force MDI */

+#define IFE_PMC_MDIX_STATUS 0x0020 /* 1=MDI-X, 0=MDI */

+#define IFE_PMC_AUTO_MDIX_COMPLETE 0x0010 /* Resolution algorthm is completed */

+#define IFE_PMC_MDIX_MODE_SHIFT 6

+#define IFE_PHC_MDIX_RESET_ALL_MASK 0x0000 /* Disable auto MDI-X */

+#define IFE_PHC_HWI_ENABLE 0x8000 /* Enable the HWI feature */

+#define IFE_PHC_ABILITY_CHECK 0x4000 /* 1= Test Passed, 0=failed */

+#define IFE_PHC_TEST_EXEC 0x2000 /* PHY launch test pulses on the wire */

+#define IFE_PHC_HIGHZ 0x0200 /* 1 = Open Circuit */

+#define IFE_PHC_LOWZ 0x0400 /* 1 = Short Circuit */

+#define IFE_PHC_LOW_HIGH_Z_MASK 0x0600 /* Mask for indication type of problem on the line */

+#define IFE_PHC_DISTANCE_MASK 0x01FF /* Mask for distance to the cable problem, in 80cm granularity */

+#define IFE_PHC_RESET_ALL_MASK 0x0000 /* Disable HWI */

+#define IFE_PSCL_PROBE_MODE 0x0020 /* LED Probe mode */

+#define IFE_PSCL_PROBE_LEDS_OFF 0x0006 /* Force LEDs 0 and 2 off */

+#define IFE_PSCL_PROBE_LEDS_ON 0x0007 /* Force LEDs 0 and 2 on */

+#define ICH8_FLASH_COMMAND_TIMEOUT 500 /* 500 ms , should be adjusted */

+#define ICH8_FLASH_CYCLE_REPEAT_COUNT 10 /* 10 cycles , should be adjusted */

+#define ICH8_FLASH_SEG_SIZE_256 256

+#define ICH8_FLASH_SEG_SIZE_4K 4096

+#define ICH8_FLASH_SEG_SIZE_64K 65536

+#define ICH8_CYCLE_READ 0x0

+#define ICH8_CYCLE_RESERVED 0x1

+#define ICH8_CYCLE_WRITE 0x2

+#define ICH8_CYCLE_ERASE 0x3

+#define ICH8_FLASH_GFPREG 0x0000

+#define ICH8_FLASH_HSFSTS 0x0004

+#define ICH8_FLASH_HSFCTL 0x0006

+#define ICH8_FLASH_FADDR 0x0008

+#define ICH8_FLASH_FDATA0 0x0010

+#define ICH8_FLASH_FRACC 0x0050

+#define ICH8_FLASH_FREG0 0x0054

+#define ICH8_FLASH_FREG1 0x0058

+#define ICH8_FLASH_FREG2 0x005C

+#define ICH8_FLASH_FREG3 0x0060

+#define ICH8_FLASH_FPR0 0x0074

+#define ICH8_FLASH_FPR1 0x0078

+#define ICH8_FLASH_SSFSTS 0x0090

+#define ICH8_FLASH_SSFCTL 0x0092

+#define ICH8_FLASH_PREOP 0x0094

+#define ICH8_FLASH_OPTYPE 0x0096

+#define ICH8_FLASH_OPMENU 0x0098

+#define ICH8_FLASH_REG_MAPSIZE 0x00A0

+#define ICH8_FLASH_SECTOR_SIZE 4096

+#define ICH8_GFPREG_BASE_MASK 0x1FFF

+#define ICH8_FLASH_LINEAR_ADDR_MASK 0x00FFFFFF

+/* ICH8 GbE Flash Hardware Sequencing Flash Status Register bit breakdown */

+/* Offset 04h HSFSTS */

+union ich8_hws_flash_status {

+ struct ich8_hsfsts {

+ uint16_t flcdone :1; /* bit 0 Flash Cycle Done */

+ uint16_t flcerr :1; /* bit 1 Flash Cycle Error */

+ uint16_t dael :1; /* bit 2 Direct Access error Log */

+ uint16_t berasesz :2; /* bit 4:3 Block/Sector Erase Size */

+ uint16_t flcinprog :1; /* bit 5 flash SPI cycle in Progress */

+ uint16_t reserved1 :2; /* bit 13:6 Reserved */

+ uint16_t reserved2 :6; /* bit 13:6 Reserved */

+ uint16_t fldesvalid :1; /* bit 14 Flash Descriptor Valid */

+ uint16_t flockdn :1; /* bit 15 Flash Configuration Lock-Down */

+ } hsf_status;

+ uint16_t regval;

+};

+/* ICH8 GbE Flash Hardware Sequencing Flash control Register bit breakdown */

+/* Offset 06h FLCTL */

+union ich8_hws_flash_ctrl {

+ struct ich8_hsflctl {

+ uint16_t flcgo :1; /* 0 Flash Cycle Go */

+ uint16_t flcycle :2; /* 2:1 Flash Cycle */

+ uint16_t reserved :5; /* 7:3 Reserved */

+ uint16_t fldbcount :2; /* 9:8 Flash Data Byte Count */

+ uint16_t flockdn :6; /* 15:10 Reserved */

+ } hsf_ctrl;

+ uint16_t regval;

+};

+/* ICH8 Flash Region Access Permissions */

+union ich8_hws_flash_regacc {

+ struct ich8_flracc {

+ uint32_t grra :8; /* 0:7 GbE region Read Access */

+ uint32_t grwa :8; /* 8:15 GbE region Write Access */

+ uint32_t gmrag :8; /* 23:16 GbE Master Read Access Grant */

+ uint32_t gmwag :8; /* 31:24 GbE Master Write Access Grant */

+ } hsf_flregacc;

+ uint16_t regval;

+};

/* Miscellaneous PHY bit definitions. */

#define PHY_PREAMBLE 0xFFFFFFFF

#define PHY_SOF 0x01