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authorJonathan Gray <jsg@cvs.openbsd.org>2010-06-27 20:13:05 +0000
committerJonathan Gray <jsg@cvs.openbsd.org>2010-06-27 20:13:05 +0000
commit97c473adbcea31108e6a401540b5fd9fa54bd1f4 (patch)
tree76e37209bea9c49b4d722e4776f3af4ebfb45bac /sys/dev/pci/if_em_hw.h
parentca99ab8a1fc9fe04e4f1e10f0019407601ecb9a8 (diff)
More PCH/82577 bits from FreeBSD, this does not include
all the workarounds but is enough to make things run at faster than 10 Mbit speeds, though these aren't always reflecting in ifmedia properly just yet. ok claudio@
Diffstat (limited to 'sys/dev/pci/if_em_hw.h')
-rw-r--r--sys/dev/pci/if_em_hw.h32
1 files changed, 31 insertions, 1 deletions
diff --git a/sys/dev/pci/if_em_hw.h b/sys/dev/pci/if_em_hw.h
index 9eb68b848c4..74808fc2124 100644
--- a/sys/dev/pci/if_em_hw.h
+++ b/sys/dev/pci/if_em_hw.h
@@ -31,7 +31,7 @@
*******************************************************************************/
-/* $OpenBSD: if_em_hw.h,v 1.40 2010/06/26 18:32:38 jsg Exp $ */
+/* $OpenBSD: if_em_hw.h,v 1.41 2010/06/27 20:13:04 jsg Exp $ */
/* $FreeBSD: if_em_hw.h,v 1.15 2005/05/26 23:32:02 tackerman Exp $ */
/* if_em_hw.h
@@ -1546,6 +1546,7 @@ struct em_hw {
#define E1000_CTRL_D_UD_POLARITY 0x00004000 /* Defined polarity of Dock/Undock indication in SDP[0] */
#define E1000_CTRL_FORCE_PHY_RESET 0x00008000 /* Reset both PHY ports, through PHYRST_N pin */
#define E1000_CTRL_EXT_LINK_EN 0x00010000 /* enable link status from external LINK_0 and LINK_1 pins */
+#define E1000_CTRL_EXT_PHYPDEN 0x00100000
#define E1000_CTRL_SWDPIN0 0x00040000 /* SWDPIN 0 value */
#define E1000_CTRL_SWDPIN1 0x00080000 /* SWDPIN 1 value */
#define E1000_CTRL_SWDPIN2 0x00100000 /* SWDPIN 2 value */
@@ -2646,6 +2647,7 @@ struct em_host_command_info {
#define BM_PHY_PAGE_SELECT 22 /* Page Select for BM */
#define BM_REG_BIAS1 29
#define BM_REG_BIAS2 30
+#define BM_PORT_CTRL_PAGE 769
#define IGP01E1000_IEEE_REGS_PAGE 0x0000
#define IGP01E1000_IEEE_RESTART_AUTONEG 0x3300
@@ -3480,4 +3482,32 @@ union ich8_hws_flash_regacc {
#define HV_OEM_BITS_GBE_DIS 0x0040 /* Gigabit Disable */
#define HV_OEM_BITS_RESTART_AN 0x0400 /* Restart Auto-negotiation */
+#define HV_KMRN_MODE_CTRL PHY_REG(769, 16)
+#define HV_KMRN_MDIO_SLOW 0x0400
+
+#define E1000_NVM_K1_CONFIG 0x1B /* NVM K1 Config Word */
+#define E1000_NVM_K1_ENABLE 0x1 /* NVM Enable K1 bit */
+
+#define E1000_KMRNCTRLSTA_OFFSET 0x001F0000
+#define E1000_KMRNCTRLSTA_OFFSET_SHIFT 16
+#define E1000_KMRNCTRLSTA_REN 0x00200000
+#define E1000_KMRNCTRLSTA_DIAG_OFFSET 0x3 /* Diagnostic */
+#define E1000_KMRNCTRLSTA_TIMEOUTS 0x4 /* Timeouts */
+#define E1000_KMRNCTRLSTA_INBAND_PARAM 0x9 /* InBand Parameters */
+#define E1000_KMRNCTRLSTA_DIAG_NELPBK 0x1000 /* Loopback mode */
+#define E1000_KMRNCTRLSTA_K1_CONFIG 0x7
+#define E1000_KMRNCTRLSTA_K1_ENABLE 0x0002
+
+
+/* Extended Configuration Control and Size */
+#define E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP 0x00000020
+#define E1000_EXTCNF_CTRL_LCD_WRITE_ENABLE 0x00000001
+#define E1000_EXTCNF_CTRL_OEM_WRITE_ENABLE 0x00000008
+#define E1000_EXTCNF_CTRL_SWFLAG 0x00000020
+#define E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_MASK 0x00FF0000
+#define E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_SHIFT 16
+#define E1000_EXTCNF_CTRL_EXT_CNF_POINTER_MASK 0x0FFF0000
+#define E1000_EXTCNF_CTRL_EXT_CNF_POINTER_SHIFT 16
+
+
#endif /* _EM_HW_H_ */