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authorChris Cappuccio <chris@cvs.openbsd.org>2000-07-07 18:42:18 +0000
committerChris Cappuccio <chris@cvs.openbsd.org>2000-07-07 18:42:18 +0000
commit025de15d15bfbc089e2c174c993641fe05d99f97 (patch)
tree6b9ee652b8f346080482b7b893cb885dd8ece1be /sys/dev/pci/pciide_amd_reg.h
parent1d419d20183a0f020426a726e32ea535ada648ed (diff)
From NetBSD:
Match Promise Ultra/100 controller (Ultra/100 drives will be used as Ultra/66 fow now) Work-around for a bug in revision D2 AMD controllers (They do not work correctly with Multiword-DMA mode, workaround is to disable MW DMA, but this bug does not affect all drives so there is an option PCIIDE_AMD756_ENABLEDMA to stop this behavior. You know you have this bug when your system hangs completely with this option.)
Diffstat (limited to 'sys/dev/pci/pciide_amd_reg.h')
-rw-r--r--sys/dev/pci/pciide_amd_reg.h16
1 files changed, 15 insertions, 1 deletions
diff --git a/sys/dev/pci/pciide_amd_reg.h b/sys/dev/pci/pciide_amd_reg.h
index f683e173bd7..dda05e3dee5 100644
--- a/sys/dev/pci/pciide_amd_reg.h
+++ b/sys/dev/pci/pciide_amd_reg.h
@@ -1,4 +1,4 @@
-/* $OpenBSD: pciide_amd_reg.h,v 1.1 2000/03/24 17:47:41 chris Exp $ */
+/* $OpenBSD: pciide_amd_reg.h,v 1.2 2000/07/07 18:42:17 chris Exp $ */
/*
* Copyright (c) 2000 David Sainty.
@@ -38,6 +38,20 @@
* available at: http://www.amd.com/products/cpg/athlon/techdocs/pdf/22548.pdf
*/
+/* Chip revisions */
+#define AMD756_CHIPREV_D2 3
+
+/* Chip revision tests */
+
+/*
+ * The AMD756 chip revision D2 has a bug affecting DMA (but not UDMA)
+ * modes. The workaround documented by AMD is to not use DMA on any
+ * drive which does not support UDMA modes.
+ *
+ * See: http://www.amd.com/products/cpg/athlon/techdocs/pdf/22591.pdf
+ */
+#define AMD756_CHIPREV_DISABLEDMA(rev) ((rev) <= AMD756_CHIPREV_D2)
+
/* Channel enable */
#define AMD756_CHANSTATUS_EN 0x40
#define AMD756_CHAN_EN(chan) (0x01 << (1 - (chan)))