rev 1.62

Possibloe fix for some bge chip revisions taking a long time to reset
(e.g., polling for a half-second or more at splnet(), blocking most
interrupts, durin an ifconfig down/ifconfig up).

Appears to help for a 5704C rev A3, which is the only chip I've
ever seen that had even a mild version of the reported problem.

rev 1.61

Check for BGE_PCI_PCISTATE register failing to revert on reset.
if it occurs, print a message indicating why the reset took so long.

From NetBSD

2 files changed, 22 insertions, 5 deletions

diff --git a/sys/dev/pci/if_bge.c b/sys/dev/pci/if_bge.c
index 12a9fbe8d62..8fe793ca27d 100644
--- a/sys/dev/pci/if_bge.c
+++ b/sys/dev/pci/if_bge.c
@@ -1,4 +1,4 @@
-/*	$OpenBSD: if_bge.c,v 1.44 2004/12/16 14:30:31 brad Exp $	*/
+/*	$OpenBSD: if_bge.c,v 1.45 2004/12/17 03:13:59 brad Exp $	*/
 /*
  * Copyright (c) 2001 Wind River Systems
  * Copyright (c) 1997, 1998, 1999, 2001
@@ -2053,7 +2053,7 @@ bge_reset(sc)
 	struct bge_softc *sc;
 {
 	struct pci_attach_args *pa = &sc->bge_pa;
-	u_int32_t cachesize, command, pcistate, reset;
+	u_int32_t cachesize, command, pcistate, new_pcistate, reset;
 	int i, val = 0;
 
 	/* Save some important PCI state. */
@@ -2113,6 +2113,7 @@ bge_reset(sc)
 	 * general communications memory at 0xB50.
 	 */
 	bge_writemem_ind(sc, BGE_SOFTWARE_GENCOMM, BGE_MAGIC_NUMBER);
+
 	/*
 	 * Poll the value location we just wrote until
 	 * we see the 1's complement of the magic number.
@@ -2141,11 +2142,18 @@ bge_reset(sc)
 	 * results.
 	 */
 	for (i = 0; i < BGE_TIMEOUT; i++) {
-		if (pci_conf_read(pa->pa_pc, pa->pa_tag, BGE_PCI_PCISTATE) ==
-		    pcistate)
+		new_pcistate = pci_conf_read(pa->pa_pc, pa->pa_tag,
+		    BGE_PCI_PCISTATE);
+		if ((new_pcistate & ~BGE_PCISTATE_RESERVED) ==
+		    (pcistate & ~BGE_PCISTATE_RESERVED))
 			break;
 		DELAY(10);
 	}
+	if ((new_pcistate & ~BGE_PCISTATE_RESERVED) != 
+	    (pcistate & ~BGE_PCISTATE_RESERVED)) {
+		printf("%s: pcistate failed to revert\n",
+		    sc->bge_dev.dv_xname);
+	}
 
 	/* Fix up byte swapping */
 	CSR_WRITE_4(sc, BGE_MODE_CTL, BGE_MODECTL_BYTESWAP_NONFRAME|
diff --git a/sys/dev/pci/if_bgereg.h b/sys/dev/pci/if_bgereg.h
index 0581a7d7ae9..045c206856e 100644
--- a/sys/dev/pci/if_bgereg.h
+++ b/sys/dev/pci/if_bgereg.h
@@ -1,4 +1,4 @@
-/* $OpenBSD: if_bgereg.h,v 1.16 2004/12/16 14:30:32 brad Exp $ */
+/* $OpenBSD: if_bgereg.h,v 1.17 2004/12/17 03:13:59 brad Exp $ */
 /*
  * Copyright (c) 2001 Wind River Systems
  * Copyright (c) 1997, 1998, 1999, 2001
@@ -311,6 +311,15 @@
 #define BGE_PCISTATE_PCI_TGT_RETRY_MAX	0x00000E00
 
 /*
+ * The following bits in PCI state register are reserved.
+ * If we check that the register values reverts on reset,
+ * do not check these bits. On some 5704C (rev A3) and some
+ * Altima chips, these bits do not revert until much later
+ * in the bge driver's bge_reset() chip-reset state machine.
+ */
+#define BGE_PCISTATE_RESERVED	((1 << 12) + (1 <<7))
+
+/*
  * PCI Clock Control register -- note, this register is read only
  * unless the CLOCKCTL_RW bit of the PCI Misc. Host Control
  * register is set.