remove some unused includes

2 files changed, 0 insertions, 657 deletions

diff --git a/sys/dev/pci/bt8370reg.h b/sys/dev/pci/bt8370reg.h
deleted file mode 100644
index 3414c79ca33..00000000000
--- a/sys/dev/pci/bt8370reg.h
+++ /dev/null
@@ -1,392 +0,0 @@
-/*	$OpenBSD: bt8370reg.h,v 1.3 2005/12/19 15:53:15 claudio Exp $ */
-
-/*
- * Copyright (c) 2004,2005  Internet Business Solutions AG, Zurich, Switzerland
- * Written by: Andre Oppermann <oppermann@accoom.net>
- *
- * Permission to use, copy, modify, and distribute this software for any
- * purpose with or without fee is hereby granted, provided that the above
- * copyright notice and this permission notice appear in all copies.
- *
- * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
- * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
- * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
- * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
- * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
- * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
- */
-
-/* Bt8370 Register definitions */
-/* Globals */
-#define	Bt8370_DID	0x000		/* Device Identification */
-#define	Bt8370_CR0	0x001		/* Primary control register */
-#define		CR0_RESET	0x80		/* Reset Framer */
-#define		CR0_E1_FAS	0x00		/* E1 FAS only */
-#define		CR0_E1_FAS_CRC	0x08		/* E1 FAS+CRC4 */
-#define		CR0_T1_SF	0x09		/* T1 SF */
-#define		CR0_T1_ESF	0x1B		/* T1 ESF+ForceCRC */
-#define	Bt8370_JAT_CR	0x002		/* Jitter attenuator conf */
-#define		JAT_CR_JEN	0x80		/* Jitter anntenuator enable */
-#define		JAT_CR_JFREE	0x40		/* Free running JCLK and CLADO */
-#define		JAT_CR_JDIR_TX	0x00		/* JAT in TX direction */
-#define		JAT_CR_JDIR_RX	0x20		/* JAT in RC direction */
-#define		JAT_CR_JAUTO	0x10		/* JCLK Acceleration */
-#define		JAT_CR_CENTER	0x80		/* Force JAT to center */
-#define		JAT_CR_JSIZE8	0x00		/* Elastic store size 8 bits */
-#define		JAT_CR_JSIZE16	0x01		/* Elastic store size 16 bits */
-#define		JAT_CR_JSIZE32	0x02		/* Elastic store size 32 bits */
-#define		JAT_CR_JSIZE64	0x03		/* Elastic store size 64 bits */
-#define		JAT_CR_JSIZE128	0x04		/* Elastic store size 128 bits */
-#define	Bt8370_IRR	0x003		/* Interrupt request register */
-/* Interrupt Status */
-#define	Bt8370_ISR7	0x004		/* Alarm 1 Interrupt Status */
-#define	Bt8370_ISR6	0x005		/* Alarm 2 Interrupt Status */
-#define	Bt8370_ISR5	0x006		/* Error Interrupt Status */
-#define	Bt8370_ISR4	0x007		/* Counter Overflow Interrupt Status */
-#define	Bt8370_ISR3	0x008		/* Timer Interrupt Status */
-#define	Bt8370_ISR2	0x009		/* Data Link 1 Interrupt Status */
-#define	Bt8370_ISR1	0x00A		/* Data Link 2 Interrupt Status */
-#define	Bt8370_ISR0	0x00B		/* Pattern Interrupt Status */
-/* Interrupt Enable */
-#define	Bt8370_IER7	0x00C		/* Alarm 1 Interrupt Enable register */
-#define	Bt8370_IER6	0x00D		/* Alarm 2 Interrupt Enable register */
-#define	Bt8370_IER5	0x00E		/* Error Interrupt Enable register */
-#define	Bt8370_IER4	0x00F		/* Count Overflow Interrupt Enable register */
-#define	Bt8370_IER3	0x010		/* Timer Interrupt Enable register */
-#define	Bt8370_IER2	0x011		/* Data Link 1 Interrupt Enable register */
-#define	Bt8370_IER1	0x012		/* Date Link 2 Interrupt Enable register */
-#define	Bt8370_IER0	0x013		/* Pattern Interrupt Enable register */
-/* Primary */
-#define	Bt8370_LOOP	0x014		/* Loopback Configuration register */
-#define		LOOP_PLOOP	0x08		/* Remote Payload Loopback */
-#define		LOOP_LLOOP	0x04		/* Remote Line Loopback */
-#define		LOOP_FLOOP	0x02		/* Local Framer Loopback */
-#define		LOOP_ALOOP	0x01		/* Local Analog Loopback */
-#define	Bt8370_DL3_TS	0x015		/* External Data Link Channel */
-#define	Bt8370_DL3_BIT	0x016		/* External Data Link Bit */
-#define	Bt8370_FSTAT	0x017		/* Offline Framer Status */
-#define		FSTAT_INVALID	0x10		/* No candidate */
-#define		FSTAT_FOUND	0x08		/* Frame Search Successful */
-#define		FSTAT_TIMEOUT	0x04		/* Framer Search Timeout */
-#define		FSTAT_ACTIVE	0x02		/* Framer Active */
-#define		FSTAT_RXTXN	0x01		/* RX/TX Reframe Operation */
-#define	Bt8370_PIO	0x018		/* Programmable Input/Output */
-#define		PIO_ONESEC_IO	0x80		/*  */
-#define		PIO_RDL_IO	0x40		/*  */
-#define		PIO_TDL_IO	0x20		/*  */
-#define		PIO_INDY_IO	0x10		/*  */
-#define		PIO_RFSYNC_IO	0x08		/*  */
-#define		PIO_RMSYNC_IO	0x04		/*  */
-#define		PIO_TFSYNC_IO	0x02		/*  */
-#define		PIO_TMSYNC_IO	0x01		/*  */
-#define	Bt8370_POE	0x019		/* Programmable Output Enable */
-#define		POE_TDL_OE	0x20		/*  */
-#define		POE_RDL_OE	0x10		/*  */
-#define		POE_INDY_OE	0x08		/*  */
-#define		POE_TCKO_OE	0x04		/*  */
-#define		POE_CLADO_OE	0x02		/*  */
-#define		POE_RCKO_OE	0x01		/*  */
-#define	Bt8370_CMUX	0x01A		/* Clock Input Mux */
-#define		CMUX_RSBCKI_RSBCKI	0x00	/*  */
-#define		CMUX_RSBCKI_TSBCKI	0x40	/*  */
-#define		CMUX_RSBCKI_CLADI	0x80	/*  */
-#define		CMUX_RSBCKI_CLADO	0xC0	/*  */
-#define		CMUX_TSBCKI_TSBCKI	0x00	/*  */
-#define		CMUX_TSBCKI_RSBCKI	0x10	/*  */
-#define		CMUX_TSBCKI_CLADI	0x20	/*  */
-#define		CMUX_TSBCKI_CLADO	0x30	/*  */
-#define		CMUX_CLADI_CLADI	0x00	/*  */
-#define		CMUX_CLADI_RCKO		0x04	/*  */
-#define		CMUX_CLADI_TSBCKI	0x08	/*  */
-#define		CMUX_CLADI_TCKI		0x0C	/*  */
-#define		CMUX_TCKI_TCKI		0x00	/*  */
-#define		CMUX_TCKI_RCKO		0x01	/*  */
-#define		CMUX_TCKI_RSBCKI	0x02	/*  */
-#define		CMUX_TCKI_CLADO		0x03	/*  */
-#define	Bt8370_TMUX	0x01B		/* Test Mux Configuration */
-#define	Bt8370_TEST	0x01C		/* Test Configuration */
-/* Receive LIU (RLIU) */
-#define	Bt8370_LIU_CR	0x020		/* LIU Configuration */
-#define		LIU_CR_RST_LIU	0x80		/* Reset RLIU */
-#define		LIU_CR_SQUELCH	0x40		/* Enable Squelch */
-#define		LIU_CR_FORCE_VGA 0x20		/* Internal Variable Gain Amp */
-#define		LIU_CR_RDIGI	0x10		/* Enable Receive Digital Inputs */
-#define		LIU_CR_ATTN0	0x00		/* Bridge Attenuation 0db */
-#define		LIU_CR_ATTN10	0x04		/* Bridge Attenuation -10db */
-#define		LIU_CR_ATTN20	0x08		/* Bridge Attenuation -20db */
-#define		LIU_CR_ATTN30	0x0C		/* Bridge Attenuation -30db */
-#define		LIU_CR_MAGIC	0x01		/* This one must be enabled */
-#define	Bt8370_RSTAT	0x021		/* Receive LIU Status */
-#define		RSTAT_CPDERR	0x80		/* CLAD Phase detector lost lock */
-#define		RSTAT_JMPTY	0x40		/* JAT Empty/Full */
-#define		RSTAT_ZCSUB	0x20		/* ZCS detected */
-#define		RSTAT_EXZ	0x10		/* Excessive Zeros */
-#define		RSTAT_BPV	0x08		/* Bipolar Violations */
-#define		RSTAT_EYEOPEN	0x02		/* Equalization State */
-#define		RSTAT_PRE_EQ	0x01		/* Pre-Equalizer Status */
-#define	Bt8370_RLIU_CR	0x022		/* Receive LIU Configuration */
-#define		RLIU_CR_FRZ_SHORT 0x80		/* Freeze Equalizer for short lines */
-#define		RLIU_CR_HI_CLICE  0x40		/* High Clock Slicer Threshold */
-#define		RLIU_CR_AGC32	0x00		/* AGC Observation Window 32bit */
-#define		RLIU_CR_AGC128	0x10		/* AGC Observation Window 128bit */
-#define		RLIU_CR_AGC512	0x20		/* AGC Observation Window 512bit */
-#define		RLIU_CR_AGC2048	0x30		/* AGC Observation Window 2048bit */
-#define		RLIU_CR_EQ_FRZ	0x08		/* Freeze EQ Coefficients */
-#define		RLIU_CR_OOR_BLOCK 0x04		/* Disable automatic RLBO */
-#define		RLIU_CR_RLBO	0x02		/* Receiver Line Build Out */
-#define		RLIU_CR_LONG_EYE  0x01		/* Eye Open Timeout 8192bit */
-#define	Bt8370_LPF	0x023		/* RPLL Low Pass Filter */
-#define	Bt8370_VGA_MAX	0x024		/* Variable Gain Amplifier Maximum */
-#define	Bt8370_EQ_DAT	0x025		/* Equalizer Coefficient Data register */
-#define	Bt8370_EQ_PTR	0x026		/* Equalizer Coefficient Table Pointer */
-#define	Bt8370_DSLICE	0x027		/* Data Slicer Threshold */
-#define	Bt8370_EQ_OUT	0x028		/* Equalizer Output Levels */
-#define	Bt8370_VGA	0x029		/* Variable Gain Amplifier Status */
-#define	Bt8370_PRE_EQ	0x02A		/* Pre-Equalizer */
-#define	Bt8370_COEFF	0x030 /* -037 *//* LMS Adjusted Equalizer Coefficient Status */
-#define	Bt8370_GAIN	0x038 /* -03C *//* Equalizer Gain Thresholds */
-/* Digital Reveiver (RCVR) */
-#define	Bt8370_RCR0	0x040		/* Receiver Configuration */
-#define		RCR0_HDB3	0x00		/* */
-#define		RCR0_B8ZS	0x00		/* */
-#define		RCR0_AMI	0x80		/* */
-#define		RCR0_RABORT	0x40		/* */
-#define		RCR0_RFORCE	0x20		/* */
-#define		RCR0_LFA_FAS	0x18		/* 3 consecutive FAS Errors */
-#define		RCR0_LFA_FASCRC	0x08		/* 3 consecutive FAS or 915 CRC Errors */
-#define		RCR0_LFA_26F	0x08		/* 2 out of 6 F bit Errors */
-#define		RCR0_RZCS_BPV	0x00		/* */
-#define		RCR0_RZCS_NBPV	0x01		/* */
-#define	Bt8370_RPATT	0x041		/* Receive Test Pattern Configuration */
-#define	Bt8370_RLB	0x042		/* Receive Loopback Code Detector Configuration */
-#define	Bt8370_LBA	0x043		/* Loopback Activate Code Pattern */
-#define	Bt8370_LBD	0x044		/* Loopback Deactivate Code Pattern */
-#define	Bt8370_RALM	0x045		/* Receive Alarm Signal Configuration */
-#define		RALM_FSNFAS	0x20		/* Include FS/NFAS in FERR and FRED */
-#define	Bt8370_LATCH	0x046		/* Alarm/Error/Counter Latch Configuration */
-#define		LATCH_STOPCNT	0x08		/* Stop Error Counter during RLOF,RLOS,RAIS */
-#define	Bt8370_ALM1	0x047		/* Alarm 1 Status */
-#define		ALM1_RMYEL	0x80		/* Receive Multifram Yellow Alarm */
-#define		ALM1_RYEL	0x40		/* Receive Yellow Alarm */
-#define		ALM1_RAIS	0x10		/* Reveive Alarm Indication Signal */
-#define		ALM1_RALOS	0x09		/* Receive Analog Loss of Signal */
-#define		ALM1_RLOS	0x04		/* Receive Loss of Signal */
-#define		ALM1_RLOF	0x02		/* Receive Loss of Frame Alignment */
-#define		ALM1_SIGFRZ	0x01		/* Signalling Freeze */
-#define	Bt8370_ALM2	0x048		/* Alarm 2 Status */
-#define		ALM2_LOOPDN	0x80		/*  */
-#define		ALM2_LOOPUP	0x40		/*  */
-#define		ALM2_TSHORT	0x10		/* Transmit Short Circuit */
-#define		ALM2_TLOC	0x08		/* Transmit Loss of clock */
-#define		ALM2_TLOF	0x02		/* Transmit Loss of Frame alignment */
-#define	Bt8370_ALM3	0x049		/* Alarm 3 Status */
-#define		ALM3_RMAIS	0x40		/* Receive TS16 Alarm Indication */
-#define		ALM3_SEF	0x20		/* Severely Errored Frame */
-#define		ALM3_SRED	0x10		/* Loss of CAS Alignment */
-#define		ALM3_MRED	0x08		/* Loss of MFAS Alignment */
-#define		ALM3_FRED	0x04		/* Loss of T1/FAS Alignment */
-#define		ALM3_LOF1	0x02		/* Reason for Loss of Frame Alignment */
-#define		ALM3_LOF0	0x01		/* Reason for Loss of Frame Alignment */
-/* Error/Alarm Counters */
-#define	Bt8370_FERR_LSB	0x050		/* Framing Bit Error Counter LSB */
-#define	Bt8370_FERR_MSB	0x051		/* ditto MSB */
-#define	Bt8370_CERR_LSB	0x052		/* CRC Error Counter LSB */
-#define	Bt8370_CERR_MSB	0x053		/* ditto MSB */
-#define	Bt8370_LCV_LSB	0x054		/* Line Code Violation Counter LSB*/
-#define	Bt8370_LCV_MSB	0x055		/* ditto MSB */
-#define	Bt8370_FEBE_LSB	0x056		/* Far End Block Error Counter LSB*/
-#define	Bt8370_FEBE_MSB	0x057		/* ditto MSB */
-#define	Bt8370_BERR_LSB	0x058		/* PRBS Bit Error Counter LSB */
-#define	Bt8370_BERR_MSB	0x059		/* ditto MSB */
-/* Receive Sa-Byte */
-#define	Bt8370_RSA4	0x05B		/* Receive Sa4 Byte Buffer */
-#define	Bt8370_RSA5	0x05C		/* ditto Sa5 */
-#define	Bt8370_RSA6	0x05D		/* ditto Sa6 */
-#define	Bt8370_RSA7	0x05E		/* ditto Sa7 */
-#define	Bt8370_RSA8	0x05F		/* ditto Sa8 */
-/* Transmit LIU (TLIU) */
-#define	Bt8370_SHAPE	0x060 /* -067 *//* Transmit Pulse Shape Configuration */
-#define	Bt8370_TLIU_CR	0x068		/* Transmit LIU Configuration */
-#define		TLIU_CR_120	0x4C		/* 120 Ohms, external term */
-#define		TLIU_CR_100	0x40		/* 100 Ohms, external term */
-/* Digital Transmitter (XMTR) */
-#define	Bt8370_TCR0	0x070		/* Transmit Framer Configuration */
-#define		TCR0_FAS	0x00		/* FAS Only */
-#define		TCR0_MFAS	0x04		/* FAS + MFAS*/
-#define		TCR0_SF		0x04		/* SF Only */
-#define		TCR0_ESF	0x01		/* ESF Only */
-#define		TCR0_ESFCRC	0x0D		/* ESF + Force CRC */
-#define	Bt8370_TCR1	0x071		/* Transmitter Configuration */
-#define		TCR1_TABORT	0x40		/* Disable TX Offline Framer */
-#define		TCR1_TFORCE	0x20		/* Force TX Reframe */
-#define		TCR1_HDB3	0x01		/* Line code HDB3 */
-#define		TCR1_B8ZS	0x01		/* Line code B8ZS */
-#define		TCR1_AMI	0x00		/* Line code AMI */
-#define		TCR1_3FAS	0x10		/* 3 consecutive FAS Errors */
-#define		TCR1_26F	0x10		/* 2 out of 6 Frame Bit Errors */
-#define	Bt8370_TFRM	0x072		/* Transmit Frame Format */
-#define		TFRM_MYEL	0x20		/* Insert MultiFrame Yellow Alarm */
-#define		TFRM_YEL	0x10		/* Insert Yellow Alarm */
-#define		TFRM_MF		0x08		/* Insert MultiFrame Alignment */
-#define		TFRM_FE		0x04		/* Insert FEBE */
-#define		TFRM_CRC	0x02		/* Insert CRC4 */
-#define		TFRM_FBIT	0x01		/* Insert F bit or FAS/NAS alignment */
-#define	Bt8370_TERROR	0x073		/* Transmit Error Insert */
-#define	Bt8370_TMAN	0x074		/* Transmit Manual Sa-Byte/FEBE Configuration */
-#define		TMAN_MALL	0xF8		/* All Sa Bytes Manual */
-#define	Bt8370_TALM	0x075		/* Transmit Alarm Signal Configuration */
-#define		TALM_AMYEL	0x20		/* Automatic MultiFrame Yellow Alarm transmit */
-#define		TALM_AYEL	0x10		/* Automatic Yellow Alarm transmit */
-#define		TALM_AAIS	0x08		/* Automatic AIS Alarm transmit */
-#define	Bt8370_TPATT	0x076		/* Transmit Test Pattern Configuration */
-#define	Bt8370_TLB	0x077		/* Transmit Inband Loopback Code Configuration */
-#define	Bt8370_LBP	0x078		/* Transmit Inband Loopback Code Pattern */
-/* Transmit Sa-Byte */
-#define	Bt8370_TSA4	0x07B		/* Transmit Sa4 Byte Buffer */
-#define	Bt8370_TSA5	0x07C		/* ditto Sa5 */
-#define	Bt8370_TSA6	0x07D		/* ditto Sa6 */
-#define	Bt8370_TSA7	0x07E		/* ditto Sa7 */
-#define	Bt8370_TSA8	0x07F		/* ditto Sa8 */
-/* Clock Rate Adapter (CLAD) */
-#define	Bt8370_CLAD_CR	0x090		/* Clock Rate Adapter Configuration */
-#define		CLAD_CR_CEN	0x80		/* Enable CLAD phase detector */
-#define		CLAD_CR_XSEL_1X	0x00		/* Line rate multiplier 1X */
-#define		CLAD_CR_XSEL_2X	0x10		/* Line rate multiplier 2X */
-#define		CLAD_CR_XSEL_4X	0x20		/* Line rate multiplier 4X */
-#define		CLAD_CR_XSEL_8X	0x30		/* Line rate multiplier 8X */
-#define		CLAD_CR_LFGAIN	0x05		/* Loop filter gain */
-#define	Bt8370_CSEL	0x091		/* CLAD Frequency Select */
-#define		CSEL_VSEL_1536	0x60		/* 1536kHz */
-#define		CSEL_VSEL_1544	0x50		/* 1544kHz */
-#define		CSEL_VSEL_2048	0x10		/* 2048kHz */
-#define		CSEL_VSEL_4096	0x20		/* 4096kHz */
-#define		CSEL_VSEL_8192	0x30		/* 8192kHz */
-#define		CSEL_OSEL_1536	0x06		/* 1536kHz */
-#define		CSEL_OSEL_1544	0x05		/* 1544kHz */
-#define		CSEL_OSEL_2048	0x01		/* 2048kHz */
-#define		CSEL_OSEL_4096	0x02		/* 4096kHz */
-#define		CSEL_OSEL_8192	0x03		/* 8192kHz */
-#define	Bt8370_CPHASE	0x092		/* CLAD Phase Detector Scale Factor */
-#define	Bt8370_CTEST	0x093		/* CLAD Test */
-/* Bit Oriented Protocol Transceiver (BOP) */
-#define	Bt8370_BOP	0x0A0		/* Bit Oriented Protocol Transceiver */
-#define	Bt8370_TBOP	0x0A1		/* Transmit BOP Code Word */
-#define	Bt8370_RBOP	0x0A2		/* Receive BOP Code Word */
-#define	Bt8370_BOP_STAT	0x0A3		/* BOP Status */
-/* Data Link #1 */
-#define	Bt8370_DL1_TS	0x0A4		/* DL1 Time Slot Enable */
-#define	Bt8370_DL1_BIT	0x0A5		/* DL1 Bit Enable */
-#define	Bt8370_DL1_CTL	0x0A6		/* DL1 Control */
-#define	Bt8370_RDL1_FFC	0x0A7		/* RDL #1 FIFO Fill Control */
-#define	Bt8370_RDL1	0x0A8		/* Receive Data Link FIFO #1 */
-#define	Bt8370_RDL1_STAT 0x0A9		/* RDL #1 Status */
-#define	Bt8370_PRM1	0x0AA		/* Performance Report Message */
-#define	Bt8370_TDL1_FEC	0x0AB		/* TDL #1 FIFO Empty Control */
-#define	Bt8370_TDL1_EOM	0x0AC		/* TDL #1 End of Message Control */
-#define	Bt8370_TDL1	0x0AD		/* Transmit Data Link FIFO #1*/
-#define	Bt8370_TDL1_STAT 0x0AE		/* TDL #1 Status */
-/* Data Link #2 */
-#define	Bt8370_DL2_TS	0x0AF		/* DL2 Time Slot Enable */
-#define	Bt8370_DL2_BIT	0x0B0		/* DL2 Bit Enable */
-#define	Bt8370_DL2_CTL	0x0B1		/* DL2 Control */
-#define	Bt8370_RDL2_FFC	0x0B2		/* RDL #2 FIFO Fill Control */
-#define	Bt8370_RDL2	0x0B3		/* Receive Data Link FIFO #2 */
-#define	Bt8370_RDL2_STAT 0x0B4		/* RDL #2 Status */
-#define	Bt8370_TDL2_FEC	0x0B6		/* TDL #2 FIFO Empty Control */
-#define	Bt8370_TDL2_EOM	0x0B7		/* TDL #2 End of Message Control */
-#define	Bt8370_TDL2	0x0B8		/* Transmit Data Link FIFO #2*/
-#define	Bt8370_TDL2_STAT 0x0B9		/* TDL #2 Status */
-/* Test */
-#define	Bt8370_TEST1	0x0BA		/* DLINK Test Configuration */
-#define	Bt8370_TEST2	0x0BB		/* DLINK Test Status */
-#define	Bt8370_TEST3	0x0BC		/* DLINK Test Status */
-#define	Bt8370_TEST4	0x0BD		/* DLINK Test Control #1 or Configuration #2 */
-#define	Bt8370_TEST5	0x0BE		/* DLINK Test Control #2 or Configuration #2 */
-/* System Bus Interface (SBI) */
-#define	Bt8370_SBI_CR	0x0D0		/* System Bus Interface Configuration */
-#define		SBI_CR_X2CLK	0x80		/* Times 2 clock */
-#define		SBI_CR_SBI_OE	0x40		/* Enable SBI */
-#define		SBI_CR_1536	0x08		/* 1536, 24TS*/
-#define		SBI_CR_1544	0x07		/* 1544, 24TS + F bit */
-#define		SBI_CR_2048	0x06		/* 2048, 32TS */
-#define		SBI_CR_4096_A	0x04		/* 4096 Group A */
-#define		SBI_CR_4096_B	0x05		/* 4096 Group B */
-#define		SBI_CR_8192_A	0x00		/* 8192 Group A */
-#define		SBI_CR_8192_B	0x01		/* 8192 Group B */
-#define		SBI_CR_8192_C	0x02		/* 8192 Group C */
-#define		SBI_CR_8192_D	0x03		/* 8192 Group D */
-#define	Bt8370_RSB_CR	0x0D1		/* Receive System Bus Configuration */
-#define		RSB_CR_BUS_RSB	0x80		/* Multiple devices on bus */
-#define		RSB_CR_SIG_OFF	0x40		/* Inhibit RPCMO Signal reinsertion */
-#define		RSB_CR_RPCM_NEG	0x20		/* RSB falling edge */
-#define		RSB_CR_RSYN_NEG	0x10		/* RFSYNC falling edge */
-#define		RSB_CR_BUS_FRZ	0x08		/* Multiple devices on bus */
-#define		RSB_CR_RSB_CTR	0x04		/* Force RSLIP Center */
-#define		RSB_CR_RSBI_NORMAL	0x00	/* Normal Slip Buffer Mode */
-#define		RSB_CR_RSBI_ELASTIC	0x02	/* Receive Slip Buffer Elastic Mode */
-#define		RSB_CR_RSBI_BYPASS	0x03	/* Bypass Slip Buffer */
-#define	Bt8370_RSYNC_BIT 0x0D2		/* Receive System Bus Sync Bit Offset */
-#define	Bt8370_RSYNC_TS	0x0D3		/* Receive System Bus Sync Time Slot Offset */
-#define	Bt8370_TSB_CR	0x0D4		/* Transmit System Bus Configuration */
-#define		TSB_CR_BUS_TSB	0x80		/* Bused TSB output */
-#define		TSB_CR_TPCM_NEG	0x20		/* TINDO falling edge */
-#define		TSB_CR_TSYN_NEG	0x10		/* TFSYNC falling edge */
-#define		TSB_CR_TSB_CTR	0x04		/* Force TSLIP Center */
-#define		TSB_CR_TSB_NORMAL	0x00	/* Normal Slip Buffer Mode */
-#define		TSB_CR_TSB_ELASTIC	0x02	/* Send Slip Buffer Elastic Mode */
-#define		TSB_CR_TSB_BYPASS	0x03	/* Bypass Slip Buffer */
-#define	Bt8370_TSYNC_BIT 0x0D5		/* Transmit System Bus Sync Bit Offset */
-#define	Bt8370_TSYNC_TS	0x0D6		/* Transmit System Bus Sync Time Slot Offset */
-#define	Bt8370_RSIG_CR	0x0D7		/* Receive Signaling Configuration */
-#define		RSIG_CR_FRZ_OFF	0x04		/* Manual Signaling Update FRZ */
-#define		RSIG_CR_THRU	0x01		/* Transparent Robbed Bit Signaling */
-#define	Bt8370_RSYNC_FRM 0x0D8		/* Signaling Reinsertion Frame Offset */
-#define	Bt8370_SSTAT	0x0D9		/* Slip Buffer Status */
-#define		SSTAT_TSDIR	0x80		/* Transmit Slip Direction */
-#define		SSTAT_TFSLIP	0x40		/* Controlled Slip Event */
-#define		SSTAT_TUSLIP	0x20		/* Uncontrolled Slip Event */
-#define		SSTAT_RSDIR	0x08		/* Receive Slip Direction */
-#define		SSTAT_RFSLIP	0x04		/* Controlled Slip Event */
-#define		SSTAT_RUSLIP	0x02		/* Uncontrolled Slip Event */
-#define	Bt8370_STACK	0x0DA		/* Receive Signaling Stack */
-#define	Bt8370_RPHASE	0x0DB		/* RSLIP Phase Status */
-#define	Bt8370_TPHASE	0x0DC		/* TSLIP Phase Status */
-#define	Bt8370_PERR	0x0DD		/* RAM Parity Status */
-#define	Bt8370_SBCn	0x0E0 /* -0FF *//* System Bus Per-Channel Control */
-#define		SBCn_INSERT	0x40		/* Insert RX Signaling on RPCMO */
-#define		SBCn_SIG_LP	0x20		/* Local Signaling Loopback */
-#define		SBCn_RLOOP	0x10		/* Local Loopback */
-#define		SBCn_RINDO	0x08		/* Activate RINDO time slot indicator */
-#define		SBCn_TINDO	0x04		/* Activate TINDO time slot indicator */
-#define		SBCn_TSIG_AB	0x02		/* AB Signaling */
-#define		SBCn_ASSIGN	0x01		/* Enable System Bus Time Slot */
-/* Buffer Memory */
-#define	Bt8370_TPCn	0x100		/* Transmit Per-Channel Control */
-#define		TPCn_CLEAR	0x00		/* Clear Channel Mode */
-#define		TPCn_EMFBIT	0x80		/* TB7ZS/EMFBIT */
-#define		TPCn_TLOOP	0x40		/* Remote DS0 Channel Loopback */
-#define		TPCn_TIDLE	0x20		/* Transmit Idle */
-#define		TPCn_TLOCAL	0x10		/* Transmit Local Signaling */
-#define		TPCn_TSIGA	0x08		/* ABCD signaling value */
-#define		TPCn_TSIGB	0x04		/* ABCD signaling value */
-#define		TPCn_TSIGC	0x02		/* ABCD signaling value */
-#define		TPCn_TSIGD	0x01		/* ABCD signaling value */
-#define		TPCn_TSIGO	TPCn_TSIGA	/* Transmit Signaling Output */
-#define		TPCn_RSIGO	TPCn_TSIGB	/* Receive Signaling Output */
-#define	Bt8370_TSIGn	0x120		/* Transmit Signaling Buffer */
-#define	Bt8370_TSLIP_LOn 0x140		/* Transmit PCM Slip Buffer */
-#define	Bt8370_TSLIP_HIn 0x160		/* Transmit PCM Slip Buffer */
-#define	Bt8370_RPCn	0x180		/* Receive Per-Channel Control */
-#define		RPCn_CLEAR	0x00		/* Clear Channel Mode */
-#define		RPCn_RSIG_AB	0x80		/* AB Signaling */
-#define		RPCn_RIDLE	0x40		/* Time Slot Idle */
-#define		RPCn_SIG_STK	0x20		/* Receive Signal Stack */
-#define		RPCn_RLOCAL	0x10		/* Enable Local Signaling Output */
-#define		RPCn_RSIGA	0x08		/* Local Receive Signaling */
-#define		RPCn_RSIGB	0x04		/* Local Receive Signaling */
-#define		RPCn_RSIGC	0x02		/* Local Receive Signaling */
-#define		RPCn_RSIGD	0x01		/* Local Receive Signaling */
-#define	Bt8370_RSIGn	0x1A0		/* Receive Signaling Buffer */
-#define	Bt8370_RSLIP_LOn 0x1C0		/* Receive PCM Slip Buffer */
-#define	Bt8370_RSLIP_HIn 0x1E0		/* Receive PCM Slip Buffer */
diff --git a/sys/dev/pci/pciide_i31244_reg.h b/sys/dev/pci/pciide_i31244_reg.h
deleted file mode 100644
index bf7ea9415f0..00000000000
--- a/sys/dev/pci/pciide_i31244_reg.h
+++ /dev/null
@@ -1,265 +0,0 @@
-/*	$OpenBSD: pciide_i31244_reg.h,v 1.2 2006/11/19 20:09:59 brad Exp $	*/
-/*	$NetBSD: pciide_i31244_reg.h,v 1.2 2005/02/11 21:12:32 rearnsha Exp $	*/
-
-/*
- * Copyright (c) 2002 Wasabi Systems, Inc.
- * All rights reserved.
- *
- * Written by Jason R. Thorpe for Wasabi Systems, Inc.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in the
- *    documentation and/or other materials provided with the distribution.
- * 3. All advertising materials mentioning features or use of this software
- *    must display the following acknowledgement:
- *	This product includes software developed for the NetBSD Project by
- *	Wasabi Systems, Inc.
- * 4. The name of Wasabi Systems, Inc. may not be used to endorse
- *    or promote products derived from this software without specific prior
- *    written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
- * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
- * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL WASABI SYSTEMS, INC
- * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- */
-
-#ifndef _DEV_PCI_PCIIDE_I31244_REG_H_
-#define	_DEV_PCI_PCIIDE_I31244_REG_H_
-
-/*
- * Register definitions for the Intel i31244 Serial ATA Controller.
- */
-
-/*
- * In DPA mode, the i31244 has a single 64-bit BAR.
- */
-#define	ARTISEA_PCI_DPA_BASE	PCI_MAPREG_START
-
-/*
- * Extended Control and Status Register 0
- */
-#define	ARTISEA_PCI_SUECSR0	0x98
-#define	SUECSR0_LED0_ONLY	(1U << 28)	/* activity on LED0 only */
-#define	SUECSR0_SFSS		(1U << 16)	/* Superset Features
-						   Secondary Select */
-
-#define ARTISEA_PCI_SUDCSCR	0xa0
-#define SUDCSCR_DMA_WCAE	0x02		/* Write cache align enable */
-#define SUDCSCR_DMA_RCAE	0x01		/* Read cache align enable */
-
-/*
- * DPA mode shared registers.
- */
-#define	ARTISEA_SUPDIPR		0x00	/* DPA interrupt pending register */
-#define	SUPDIPR_PORTSHIFT(x)	((x) * 8)
-#define	SUPDIPR_PHY_CS		(1U << 0)	/* PHY change state */
-#define	SUPDIPR_PHY_RDY		(1U << 1)	/* PHY ready */
-#define	SUPDIPR_FIFO_ERR	(1U << 2)	/* FIFO error */
-#define	SUPDIPR_ERR_RCVD	(1U << 3)	/* ERR received */
-#define	SUPDIPR_U_FIS_R		(1U << 4)	/* unrecog. FIS reception */
-#define	SUPDIPR_DATA_I		(1U << 5)	/* data integrity */
-#define	SUPDIPR_CRC_ED		(1U << 6)	/* CRC error detected */
-#define	SUPDIPR_IDE		(1U << 7)	/* IDE interrupt */
-
-#define	ARTISEA_SUPDIMR		0x04	/* DPA interrupt mask register */
-	/* See SUPDIPR bits. */
-
-/*
- * DPA mode offset to per-port registers.
- */
-#define	ARTISEA_DPA_PORT_BASE(x) (((x) + 1) * 0x200)
-
-/*
- * DPA mode per-port registers.
- */
-#define	ARTISEA_SUPDDR		0x00	/* DPA data port register */
-	/* ATA/ATAPI compatible */
-
-#define	ARTISEA_SUPDER		0x04	/* DPA error register */
-	/* ATA/ATAPI compatible */
-
-#define	ARTISEA_SUPDFR		0x06	/* DPA features register */
-	/* ATA/ATAPI compatible */
-
-#define	ARTISEA_SUPDCSR		0x08	/* DPA sector count register */
-	/* ATA/ATAPI compatible */
-
-#define	ARTISEA_SUPDSNR		0x0c	/* DPA sector number register */
-	/* ATA/ATAPI compatible */
-
-#define	ARTISEA_SUPDCLR		0x10	/* DPA cylinder low register */
-	/* ATA/ATAPI compatible */
-
-#define	ARTISEA_SUPDCHR		0x14	/* DPA cylinder high register */
-	/* ATA/ATAPI compatible */
-
-#define	ARTISEA_SUPDDHR		0x18	/* DPA device/head register */
-	/* ATA/ATAPI compatible */
-
-#define	ARTISEA_SUPDSR		0x1c	/* DPA status register */
-	/* ATA/ATAPI compatible */
-
-#define	ARTISEA_SUPDCR		0x1d	/* DPA command register */
-	/* ATA/ATAPI compatible */
-
-#define	ARTISEA_SUPDASR		0x28	/* DPA alt. status register */
-	/* ATA/ATAPI compatible */
-
-#define	ARTISEA_SUPDDCTLR	0x29	/* DPA device control register */
-	/* ATA/ATAPI compatible */
-
-#define	ARTISEA_SUPDUDDTPR	0x64	/* DPA upper DMA desc. table pointer */
-
-#define	ARTISEA_SUPDUDDPR	0x6c	/* DPA upper DMA data buffer pointer */
-
-#define	ARTISEA_SUPDDCMDR	0x70	/* DPA DMA command register */
-	/* Almost compatible with PCI IDE, but not quite. */
-#define	SUPDDCMDR_START		(1U << 0)	/* start DMA transfer (c) */
-#define	SUPDDCMDR_WRITE		(1U << 3)	/* write *to memory* (c) */
-#define	SUPDDCMDR_DP_DMA_ACT	(1U << 8)	/* first party DMA active */
-#define	SUPDDCMDR_FP_DMA_DIR	(1U << 9)	/* 1 = host->device */
-
-#define	ARTISEA_SUPDDSR		0x72	/* DPA DMA status register */
-	/* PCI IDE compatible */
-
-#define	ARTISEA_SUPDDDTPR	0x74	/* DPA DMA desc. table pointer */
-
-#define	ARTISEA_SUPERSET_DPA_OFF 0x100	/* offset to Superset regs: DPA mode */
-
-#define	ARTISEA_SUPDSSSR	0x000	/* DPA SATA SStatus register */
-#define	SUPDSSSR_IPM_NP		(0 << 8)	/* device not present */
-#define	SUPDSSSR_IPM_ACT	(1U << 8)	/* active state */
-#define	SUPDSSSR_IPM_PARTIAL	(2U << 8)	/* partial power mgmt */
-#define	SUPDSSSR_IPM_SLUMBER	(6U << 8)	/* slumber power mgmt */
-#define	SUPDSSSR_SPD_NP		(0 << 4)	/* device not present */
-#define	SUPDSSSR_SPD_G1		(1U << 4)	/* Generation 1 speed */
-#define	SUPDSSSR_DET_NP		(0 << 0)	/* device not present */
-#define	SUPDSSSR_DET_PHY_CNE	(1U << 0)	/* PHY comm. not established */
-#define	SUPDSSSR_DET_PHY_CE	(3U << 0)	/* PHY comm. established */
-#define	SUPDSSSR_DET_PHY_LOOP	(4U << 0)	/* loopback mode */
-
-#define	ARTISEA_SUPDSSER	0x004	/* DPA SATA SError register */
-#define	SUPDSSER_DIAG_F		(1U << 25)	/* invalid FIS type */
-#define	SUPDSSER_DIAG_T		(1U << 24)	/* not implemented */
-#define	SUPDSSER_DIAG_S		(1U << 23)	/* not implemented */
-#define	SUPDSSER_DIAG_H		(1U << 22)	/* handshake error */
-#define	SUPDSSER_DIAG_C		(1U << 21)	/* CRC error */
-#define	SUPDSSER_DIAG_D		(1U << 20)	/* disparity error */
-#define	SUPDSSER_DIAG_B		(1U << 19)	/* not implemented */
-#define	SUPDSSER_DIAG_W		(1U << 18)	/* comm wake */
-#define	SUPDSSER_DIAG_I		(1U << 17)	/* not implemented */
-#define	SUPDSSER_DIAG_N		(1U << 16)	/* PHY RDY state change */
-#define	SUPDSSER_ERR_E		(1U << 11)	/* internal error */
-#define	SUPDSSER_ERR_P		(1U << 10)	/* protocol error */
-#define	SUPDSSER_ERR_C		(1U << 9)	/* non-recovered comm. */
-#define	SUPDSSER_ERR_T		(1U << 8)	/* non-recovered TDIE */
-#define	SUPDSSER_ERR_M		(1U << 1)	/* recovered comm. */
-#define	SUPDSSER_ERR_I		(1U << 0)	/* not implemented */
-
-#define	ARTISEA_SUPDSSCR	0x008	/* DPA SATA SControl register */
-#define	SUPDSSCR_IPM_ANY	(0 << 8)	/* no IPM mode restrictions */
-#define	SUPDSSCR_IPM_NO_PARTIAL	(1U << 8)	/* no PARTIAL mode */
-#define	SUPDSSCR_IPM_NO_SLUMBER	(2U << 8)	/* no SLUMBER mode */
-#define	SUPDSSCR_IPM_NONE	(3U << 8)	/* no PM allowed */
-#define	SUPDSSCR_SPD_ANY	(0 << 4)	/* no speed restrictions */
-#define	SUPDSSCR_SPD_G1		(1U << 4)	/* <= Generation 1 */
-#define	SUPDSSCR_DET_NORM	(0 << 0)	/* normal operation */
-#define	SUPDSSCR_DET_INIT	(1U << 0)	/* comm. init */
-#define	SUPDSSCR_DET_DISABLE	(4U << 0)	/* disable interface */
-
-#define	ARTISEA_SUPDSDBR	0x00c	/* DPA Set Device Bits register */
-
-#define	ARTISEA_SUPDPFR		0x040	/* DPA PHY feature register */
-#define	SUPDPFR_SSCEN		(1U << 16)	/* SSC enable */
-#define	SUPDPFR_FVS		(1U << 14)	/* full voltage swing */
-
-#define	ARTISEA_SUPDBFCSR	0x044	/* DPA BIST FIS ctrl/stat register */
-#define	SUPDBFCSR_PAT_D21_5	(0 << 30)	/* D21.5s */
-#define	SUPDBFCSR_PAT_D24_3	(1U << 30)	/* D24.3s */
-#define	SUPDBFCSR_PAT_D10_2	(2U << 30)	/* D10.2 / K28.5 */
-#define	SUPDBFCSR_PAT_COUNT	(3U << 30)	/* counting */
-#define	SUPDBFCSR_CS_D21_5	(0 << 28)
-#define	SUPDBFCSR_CS_D24_3	(1U << 28)
-#define	SUPDBFCSR_CS_D10_2	(2U << 28)
-#define	SUPDBFCSR_CS_COUNT	(3U << 30)
-#define	SUPDBFCSR_CLEAR_ERRS	(1U << 25)	/* clear errors/frames */
-#define	SUPDBFCSR_CE		(1U << 24)	/* BIST check enable */
-#define	SUPDBFCSR_PE		(1U << 23)	/* BIST pattern enable */
-#define	SUPDBFCSR_K28_5		((1U << 16) |				\
-				 (1U << 8)	/* send K28.5s */
-#define	SUPDBFCSR_BIST_ACT_RX	(1U << 15)	/* BIST Act. FIS was rx'd */
-#define	SUPDBFCSR_BIST_ACT_RX_TO (1U << 14)	/* ...with transmit-only */
-#define	SUPDBFCSR_BIST_ACT_RX_AB (1U << 13)	/* ...with align-bypass */
-#define	SUPDBFCSR_BIST_ACT_RX_SB (1U << 12)	/* ...with scrambling-bypass */
-#define	SUPDBFCSR_BIST_ACT_RX_RT (1U << 11)	/* ...with retimed */
-#define	SUPDBFCSR_BIST_ACT_RX_P  (1U << 10)	/* ...with primitive */
-#define	SUPDBFCSR_BIST_ACT_RX_AFEL (1U << 9)	/* ...with AFE loopback */
-#define	SUPDBFCSR_BIST_ACT_TX	(1U << 7)	/* send BIST Act. FIS */
-#define	SUPDBFCSR_BIST_ACT_TX_TO (1U << 6)	/* ...with transmit-only */
-#define	SUPDBFCSR_BIST_ACT_TX_AB (1U << 5)	/* ...with align-bypass */
-#define	SUPDBFCSR_BIST_ACT_TX_SB (1U << 4)	/* ...with scrambling-bypass */
-#define	SUPDBFCSR_BIST_ACT_TX_RT (1U << 3)	/* ...with retimed */
-#define	SUPDBFCSR_BIST_ACT_TX_P  (1U << 2)	/* ...with primitive */
-#define	SUPDBFCSR_BIST_ACT_TX_AFEL (1U << 1)	/* ...with AFE loopback */
-#define	SUPDBFCSR_INIT_NE_TO	(1U << 0)	/* init. near-end tx-only */
-
-#define	ARTISEA_SUPDBER		0x048	/* DPA BIST errors register */
-
-#define	ARTISEA_SUPDBFR		0x04c	/* DPA BIST frames register */
-
-#define	ARTISEA_SUPDHBDLR	0x050	/* DPA Host BIST data low register */
-
-#define	ARTISEA_SUPDHBDHR	0x054	/* DPA Host BIST data high register */
-
-#define	ARTISEA_SUPDDBDLR	0x058	/* DPA Device BIST data low */
-
-#define	ARTISEA_SUPDDBDHR	0x05c	/* DPA Device BIST data high */
-
-#define	ARTISEA_SUPDDSFCSR	0x068	/* DPA DMA setup FIS ctrl/stat */
-#define	SUPDDSFCSR_DIR		(1U << 31)	/* First Party setup FIS
-						   word 0 direction bit
-						   (1 == tx -> rx) */
-#define	SUPDDSFCSR_INTR		(1U << 30)	/* rcvd's First Party setup
-						   FIS with I bit set */
-#define	SUPDDSFCSR_START_SETUP	(1U << 28)	/* send DMA setup FIS */
-#define	SUPDDSFCSR_EN_FP_AP	(1U << 27)	/* enab. FP DMA auto-process */
-#define	SUPDDSFCSR_ABORT_TSM	(1U << 24)	/* abort xport/link SMs */
-
-#define	ARTISEA_SUPDHDBILR	0x06c	/* DPA Host DMA Buff. Id low */
-
-#define	ARTISEA_SUPDHDBIHR	0x070	/* DPA Host DMA Buff. Id high */
-
-#define	ARTISEA_SUPDHRDR0	0x074	/* DPA Host Resvd. DWORD 0 */
-
-#define	ARTISEA_SUPDHDBOR	0x078	/* DPA Host DMA Buff. offset */
-
-#define	ARTISEA_SUPDHDTCR	0x07c	/* DPA Host DMA xfer count */
-
-#define	ARTISEA_SUPDHRDR1	0x080	/* DPA Host Resvd. DWORD 1 */
-
-#define	ARTISEA_SUPDDDBILR	0x084	/* DPA Device DMA Buff. Id low */
-
-#define	ARTISEA_SUPDDDBIHR	0x088	/* DPA Device DMA Buff. Id high */
-
-#define	ARTISEA_SUPDDRDR0	0x08c	/* DPA Device Resvd. DWORD 0 */
-
-#define	ARTISEA_SUPDDDBOR	0x090	/* DPA Device DMA Buff. offset */
-
-#define	ARTISEA_SUPDDTCR	0x094	/* DPA Device DMA xfer count */
-
-#define	ARTISEA_SUPDDRDR1	0x09c	/* DPA Device Resvd. DWORD 1 */
-
-#endif /* _DEV_PCI_PCIIDE_I31244_REG_H_ */