o There's no such thing as a source overrun, remove the definition

o enable illegal read/write interrupts on 7811 (mainly for debugging)

2 files changed, 27 insertions, 13 deletions

diff --git a/sys/dev/pci/hifn7751.c b/sys/dev/pci/hifn7751.c
index b4653fecd31..bbfc7ccf704 100644
--- a/sys/dev/pci/hifn7751.c
+++ b/sys/dev/pci/hifn7751.c
@@ -1,4 +1,4 @@
-/*	$OpenBSD: hifn7751.c,v 1.111 2002/01/08 23:17:24 jason Exp $	*/
+/*	$OpenBSD: hifn7751.c,v 1.112 2002/01/09 01:53:39 jason Exp $	*/
 
 /*
  * Invertex AEON / Hifn 7751 driver
@@ -718,15 +718,21 @@ hifn_init_pci_registers(sc)
 	    HIFN_DMACSR_R_ABORT | HIFN_DMACSR_R_DONE | HIFN_DMACSR_R_LAST |
 	    HIFN_DMACSR_R_WAIT | HIFN_DMACSR_R_OVER |
 	    HIFN_DMACSR_S_ABORT | HIFN_DMACSR_S_DONE | HIFN_DMACSR_S_LAST |
-	    HIFN_DMACSR_S_WAIT | HIFN_DMACSR_S_OVER |
+	    HIFN_DMACSR_S_WAIT |
 	    HIFN_DMACSR_C_ABORT | HIFN_DMACSR_C_DONE | HIFN_DMACSR_C_LAST |
 	    HIFN_DMACSR_C_WAIT |
-	    HIFN_DMACSR_C_EIRQ |
-	    ((sc->sc_flags & HIFN_HAS_PUBLIC) ? HIFN_DMACSR_PUBDONE : 0));
+	    HIFN_DMACSR_ENGINE |
+	    ((sc->sc_flags & HIFN_HAS_PUBLIC) ?
+		HIFN_DMACSR_PUBDONE : 0) |
+	    ((sc->sc_flags & HIFN_IS_7811) ?
+		HIFN_DMACSR_ILLW | HIFN_DMACSR_ILLR : 0));
+
 	sc->sc_d_busy = sc->sc_r_busy = sc->sc_s_busy = sc->sc_c_busy = 0;
 	sc->sc_dmaier |= HIFN_DMAIER_R_DONE | HIFN_DMAIER_C_ABORT |
-	    HIFN_DMAIER_S_OVER | HIFN_DMAIER_D_OVER | HIFN_DMAIER_R_OVER |
-	    HIFN_DMAIER_S_ABORT | HIFN_DMAIER_D_ABORT | HIFN_DMAIER_R_ABORT;
+	    HIFN_DMAIER_D_OVER | HIFN_DMAIER_R_OVER |
+	    HIFN_DMAIER_S_ABORT | HIFN_DMAIER_D_ABORT | HIFN_DMAIER_R_ABORT |
+	    ((sc->sc_flags & HIFN_IS_7811) ?
+		HIFN_DMAIER_ILLW | HIFN_DMAIER_ILLR : 0);
 	sc->sc_dmaier &= ~HIFN_DMAIER_C_WAIT;
 	WRITE_REG_1(sc, HIFN_1_DMA_IER, sc->sc_dmaier);
 
@@ -1632,11 +1638,17 @@ hifn_intr(arg)
 		WRITE_REG_1(sc, HIFN_1_PUB_STATUS,
 		    READ_REG_1(sc, HIFN_1_PUB_STATUS) | HIFN_PUBSTS_DONE);
 
-	restart = dmacsr & (HIFN_DMACSR_S_OVER | HIFN_DMACSR_D_OVER |
-	    HIFN_DMACSR_R_OVER);
+	restart = dmacsr & (HIFN_DMACSR_D_OVER | HIFN_DMACSR_R_OVER);
 	if (restart)
 		printf("%s: overrun %x\n", sc->sc_dv.dv_xname, dmacsr);
 
+	if (sc->sc_flags & HIFN_IS_7811) {
+		if (dmacsr & HIFN_DMACSR_ILLR)
+			printf("%s: illegal read\n", sc->sc_dv.dv_xname);
+		if (dmacsr & HIFN_DMACSR_ILLW)
+			printf("%s: illegal write\n", sc->sc_dv.dv_xname);
+	}
+
 	restart = dmacsr & (HIFN_DMACSR_C_ABORT | HIFN_DMACSR_S_ABORT |
 	    HIFN_DMACSR_D_ABORT | HIFN_DMACSR_R_ABORT);
 	if (restart) {
diff --git a/sys/dev/pci/hifn7751reg.h b/sys/dev/pci/hifn7751reg.h
index f87564c2170..66184063558 100644
--- a/sys/dev/pci/hifn7751reg.h
+++ b/sys/dev/pci/hifn7751reg.h
@@ -1,4 +1,4 @@
-/*	$OpenBSD: hifn7751reg.h,v 1.32 2002/01/08 23:17:24 jason Exp $	*/
+/*	$OpenBSD: hifn7751reg.h,v 1.33 2002/01/09 01:53:39 jason Exp $	*/
 
 /*
  * Invertex AEON / Hifn 7751 driver
@@ -232,7 +232,8 @@ typedef struct hifn_desc {
 #define	HIFN_DMACSR_S_DONE	0x00001000	/* Source Ring Done */
 #define	HIFN_DMACSR_S_LAST	0x00000800	/* Source Ring Last */
 #define	HIFN_DMACSR_S_WAIT	0x00000400	/* Source Ring Waiting */
-#define	HIFN_DMACSR_S_OVER	0x00000200	/* Source Ring Overflow */
+#define	HIFN_DMACSR_ILLW	0x00000200	/* Illegal write (7811 only) */
+#define	HIFN_DMACSR_ILLR	0x00000100	/* Illegal read (7811 only) */
 #define	HIFN_DMACSR_C_CTRL	0x000000c0	/* Command Ring Control */
 #define	HIFN_DMACSR_C_CTRL_NOP	0x00000000	/* Command Control: no-op */
 #define	HIFN_DMACSR_C_CTRL_DIS	0x00000040	/* Command Control: disable */
@@ -242,7 +243,7 @@ typedef struct hifn_desc {
 #define	HIFN_DMACSR_C_LAST	0x00000008	/* Command Ring Last */
 #define	HIFN_DMACSR_C_WAIT	0x00000004	/* Command Ring Waiting */
 #define	HIFN_DMACSR_PUBDONE	0x00000002	/* Public op done (7951 only) */
-#define	HIFN_DMACSR_C_EIRQ	0x00000001	/* Command Ring Engine IRQ */
+#define	HIFN_DMACSR_ENGINE	0x00000001	/* Command Ring Engine IRQ */
 
 /* DMA Interrupt Enable Register (HIFN_1_DMA_IER) */
 #define	HIFN_DMAIER_D_ABORT	0x20000000	/* Destination Ring PCIAbort */
@@ -259,12 +260,13 @@ typedef struct hifn_desc {
 #define	HIFN_DMAIER_S_DONE	0x00001000	/* Source Ring Done */
 #define	HIFN_DMAIER_S_LAST	0x00000800	/* Source Ring Last */
 #define	HIFN_DMAIER_S_WAIT	0x00000400	/* Source Ring Waiting */
-#define	HIFN_DMAIER_S_OVER	0x00000200	/* Source Ring Overflow */
+#define	HIFN_DMAIER_ILLW	0x00000200	/* Illegal write (7811 only) */
+#define	HIFN_DMAIER_ILLR	0x00000100	/* Illegal read (7811 only) */
 #define	HIFN_DMAIER_C_ABORT	0x00000020	/* Command Ring PCI Abort */
 #define	HIFN_DMAIER_C_DONE	0x00000010	/* Command Ring Done */
 #define	HIFN_DMAIER_C_LAST	0x00000008	/* Command Ring Last */
 #define	HIFN_DMAIER_C_WAIT	0x00000004	/* Command Ring Waiting */
-#define	HIFN_DMAIER_PUBDONE	0x00000002	/* public op done (7951 only */
+#define	HIFN_DMAIER_PUBDONE	0x00000002	/* public op done (7951 only) */
 #define	HIFN_DMAIER_ENGINE	0x00000001	/* Engine IRQ */
 
 /* DMA Configuration Register (HIFN_1_DMA_CNFG) */